coreboot-gerrit October 2022

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[L] Change in coreboot[master]: [WIP] util/cbmem: add parsing of TPM logs per standard
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel. Hello Michał Żygowski, Maciej Pijanowski, Krystian Hebel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68749 to review the following change. Change subject: [WIP] util/cbmem: add parsing of TPM logs per standard ...................................................................... [WIP] util/cbmem: add parsing of TPM logs per standard coreboot is made to export the range allocated for the log. The range is helpful as there is no easy way to determine the size of the log from its header without parsing vendor info. Change-Id: Ib76dc7dec56dd1789a219539a1ac05a958f47a5c Ticket: https://ticket.coreboot.org/issues/425 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/commonlib/include/commonlib/tpm_log_defs.h M src/lib/coreboot_table.c M src/security/tpm/tspi.h M src/security/tpm/tspi/log-tpm12.c M src/security/tpm/tspi/log-tpm2.c M util/cbmem/cbmem.c 8 files changed, 339 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/68749/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 6970c63..4c56e0a 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -62,6 +62,7 @@ #define CBMEM_ID_TCPA_LOG 0x54435041 /* TPM log in coreboot-specific format */ #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 /* TPM1 ACPI log */ #define CBMEM_ID_TPM_LOG 0x54504D4C /* TPM log per specification (either one) */ +#define CBMEM_ID_TPM_LOG_REF 0x544C4752 /* Memory range allocated for CBMEM_ID_TPM_LOG */ #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 /* TPM2 ACPI log */ #define CBMEM_ID_TPM_PPI 0x54505049 @@ -139,6 +140,7 @@ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ { CBMEM_ID_TCPA_TCG_LOG, "TCPA TCGLOG" }, \ { CBMEM_ID_TPM_LOG, "TPM STD LOG" }, \ + { CBMEM_ID_TPM_LOG_REF, "TPM LOG REF" }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ { CBMEM_ID_TPM2_TCG_LOG, "TPM2 TCGLOG" }, \ { CBMEM_ID_TPM_PPI, "TPM PPI " }, \ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 3f7ff2d..ce215cd 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -87,6 +87,7 @@ LB_TAG_TYPE_C_INFO = 0x0042, LB_TAG_ACPI_RSDP = 0x0043, LB_TAG_PCIE = 0x0044, + LB_TAG_TPM_STD_LOG = 0x0045, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, diff --git a/src/commonlib/include/commonlib/tpm_log_defs.h b/src/commonlib/include/commonlib/tpm_log_defs.h index 18dc82b..97746b4 100644 --- a/src/commonlib/include/commonlib/tpm_log_defs.h +++ b/src/commonlib/include/commonlib/tpm_log_defs.h @@ -6,8 +6,29 @@ #include <stdint.h> #include <commonlib/helpers.h> +#define TCPA_SPEC_ID_EVENT_SIGNATURE "Spec ID Event00" #define TCG_EFI_SPEC_ID_EVENT_SIGNATURE "Spec ID Event03" +struct tcpa_log_entry { + uint32_t pcr; + uint32_t event_type; + uint8_t digest[20]; + uint32_t event_data_size; + uint8_t event[0]; +} __packed; + +struct tcpa_spec_entry { + struct tcpa_log_entry entry; + uint8_t signature[16]; + uint32_t platform_class; + uint8_t spec_version_minor; + uint8_t spec_version_major; + uint8_t spec_errata; + uint8_t reserved; + uint8_t vendor_info_size; + uint8_t vendor_info[0]; +} __packed; + #define TPM2_ALG_ERROR 0x0000 #define TPM2_ALG_HMAC 0x0005 #define TPM2_ALG_NULL 0x0010 @@ -45,6 +66,28 @@ #define EV_NONHOST_INFO 0x00000011 #define EV_OMIT_BOOT_DEVICE_EVENTS 0x00000012 +union tpm_hash_digest { + uint8_t sha1[SHA1_DIGEST_SIZE]; + uint8_t sha256[SHA256_DIGEST_SIZE]; + uint8_t sm3_256[SM3_256_DIGEST_SIZE]; + uint8_t sha384[SHA384_DIGEST_SIZE]; + uint8_t sha512[SHA512_DIGEST_SIZE]; +}; + +struct tpm_hash_algorithm { + uint16_t hashAlg; + union tpm_hash_digest digest; +} __packed; + +struct tcg_pcr_event2_header { + uint32_t pcr_index; + uint32_t event_type; + uint32_t digest_count; + uint8_t digests[0]; + /* uint32_t event_size; */ + /* uint8_t event[0]; */ +} __packed; + struct tpm_digest_sizes { uint16_t alg_id; uint16_t digest_size; @@ -67,4 +110,26 @@ /* uint8_t vendor_info[vendor_info_size]; */ } __packed; +static const char *tpm_event_types[] __maybe_unused = { + [EV_PREBOOT_CERT] = "Reserved", + [EV_POST_CODE] = "POST code", + [EV_UNUSED] = "Unused", + [EV_NO_ACTION] = "No action", + [EV_SEPARATOR] = "Separator", + [EV_ACTION] = "Action", + [EV_EVENT_TAG] = "Event tag", + [EV_S_CRTM_CONTENTS] = "S-CRTM contents", + [EV_S_CRTM_VERSION] = "S-CRTM version", + [EV_CPU_MICROCODE] = "CPU microcode", + [EV_PLATFORM_CONFIG_FLAGS] = "Platform configuration flags", + [EV_TABLE_OF_DEVICES] = "Table of devices", + [EV_COMPACT_HASH] = "Compact hash", + [EV_IPL] = "IPL", + [EV_IPL_PARTITION_DATA] = "IPL partition data", + [EV_NONHOST_CODE] = "Non-host code", + [EV_NONHOST_CONFIG] = "Non-host configuration", + [EV_NONHOST_INFO] = "Non-host information", + [EV_OMIT_BOOT_DEVICE_EVENTS] = "Omit boot device events", +}; + #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 2a7ccc5..d4b3bd9 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -23,6 +23,7 @@ #include <spi_flash.h> #include <smmstore.h> #include <types.h> +#include <security/tpm/tspi.h> #if CONFIG(USE_OPTION_TABLE) #include <option_table.h> @@ -289,6 +290,25 @@ } } +static void lb_tpm_std_log(struct lb_header *header) +{ + struct lb_range *lb_range; + const struct tcpa_log_ref *range = cbmem_find(CBMEM_ID_TPM_LOG_REF); + + if (range == NULL) + return; /* The section is not present */ + + lb_range = (struct lb_range *)lb_new_record(header); + if (lb_range == NULL) { + printk(BIOS_ERR, "No more room in coreboot table!\n"); + return; + } + lb_range->tag = LB_TAG_TPM_STD_LOG; + lb_range->size = sizeof(*lb_range); + lb_range->range_start = range->start; + lb_range->range_size = range->size; +} + static struct lb_mainboard *lb_mainboard(struct lb_header *header) { struct lb_record *rec; @@ -488,6 +508,9 @@ /* Serialize resource map into mem table types (LB_MEM_*) */ bootmem_write_memory_table(lb_memory(head)); + /* Record reference to TPM log composed according to specification (either one) */ + lb_tpm_std_log(head); + /* Record our motherboard */ lb_mainboard(head); diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 20b97f4..fe2a396 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -18,6 +18,11 @@ #define TPM_PCR_MAX_LEN 64 #define HASH_DATA_CHUNK_SIZE 1024 +struct tcpa_log_ref { + uint64_t start; + uint32_t size; +}; + /** * Get the pointer to the single instance of global * tcpa log data, and initialize it when necessary diff --git a/src/security/tpm/tspi/log-tpm12.c b/src/security/tpm/tspi/log-tpm12.c index f110978..ab9197f 100644 --- a/src/security/tpm/tspi/log-tpm12.c +++ b/src/security/tpm/tspi/log-tpm12.c @@ -26,6 +26,7 @@ if (cbmem_possibly_online()) { size_t tcpa_log_len; struct spec_id_event_data *hdr; + struct tcpa_log_ref *tcpa_ref; tclt = cbmem_find(CBMEM_ID_TPM_LOG); if (tclt) @@ -51,6 +52,10 @@ tclt->max_entries = MAX_TCPA_LOG_ENTRIES; tclt->num_entries = 0; + + tcpa_ref = cbmem_add(CBMEM_ID_TPM_LOG_REF, sizeof(*tcpa_ref)); + tcpa_ref->start = (uintptr_t)tclt; + tcpa_ref->size = tcpa_log_len; } return tclt; diff --git a/src/security/tpm/tspi/log-tpm2.c b/src/security/tpm/tspi/log-tpm2.c index 1d911db..e5b6bd5 100644 --- a/src/security/tpm/tspi/log-tpm2.c +++ b/src/security/tpm/tspi/log-tpm2.c @@ -48,6 +48,7 @@ if (cbmem_possibly_online()) { size_t tcpa_log_len; struct tcg_efi_spec_id_event *hdr; + struct tcpa_log_ref *tcpa_ref; tclt = cbmem_find(CBMEM_ID_TPM_LOG); if (tclt) @@ -77,6 +78,10 @@ tclt->vendor_info_size = sizeof(tclt->max_entries) + sizeof(tclt->num_entries); tclt->max_entries = MAX_TCPA_LOG_ENTRIES; tclt->num_entries = 0; + + tcpa_ref = cbmem_add(CBMEM_ID_TPM_LOG_REF, sizeof(*tcpa_ref)); + tcpa_ref->start = (uintptr_t)tclt; + tcpa_ref->size = tcpa_log_len; } return tclt; diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index c537a7a..694c9e6 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -22,6 +22,7 @@ #include <commonlib/loglevel.h> #include <commonlib/timestamp_serialized.h> #include <commonlib/tcpa_log_serialized.h> +#include <commonlib/tpm_log_defs.h> #include <commonlib/coreboot_tables.h> #ifdef __OpenBSD__ @@ -268,6 +269,7 @@ static struct lb_cbmem_ref timestamps; static struct lb_cbmem_ref console; static struct lb_cbmem_ref tcpa_log; +static struct lb_range tpm_std_log; static struct lb_memory_range cbmem; /* This is a work-around for a nasty problem introduced by initially having @@ -291,6 +293,13 @@ return ret; } +static struct lb_range parse_range(const struct lb_range *range) +{ + struct lb_range ret; + aligned_memcpy(&ret, range, sizeof(ret)); + return ret; +} + static void parse_memory_tags(const struct lb_memory *mem) { int num_entries; @@ -346,6 +355,11 @@ debug(" Found TSC info.\n"); tsc_freq_khz = ((struct lb_tsc_info *)lbr_p)->freq_khz; continue; + case LB_TAG_TPM_STD_LOG: { + debug(" Found TPM standard log table.\n"); + tpm_std_log = parse_range((struct lb_range *)lbr_p); + continue; + } case LB_TAG_FORWARD: { int ret; /* @@ -843,6 +857,202 @@ unmap_memory(&timestamp_mapping); } +static void print_hex(uint8_t *hex, size_t len) +{ + unsigned int i; + for (i = 0; i < len; i++) + printf("%02x", *(hex + i)); + printf("\n"); +} + +static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log) +{ + static uint8_t zero_block[sizeof(struct tcpa_spec_entry)]; + + uintptr_t current; + uint32_t counter = 0; + + printf("TCPA log:\n"); + printf("\tSpecification: %d.%d%d", + spec_log->spec_version_major, + spec_log->spec_version_minor, + spec_log->spec_errata); + printf("\tPlatform class: %s\n", + le32toh(spec_log->platform_class) == 0 ? "PC Client" : + le32toh(spec_log->platform_class) == 1 ? "Server" : "Unknown"); + + current = (uintptr_t)&spec_log->vendor_info[spec_log->vendor_info_size]; + while (memcmp((const void *)current, (const void *)zero_block, sizeof(zero_block))) { + uint32_t len; + struct tcpa_log_entry *log_entry = (void *)current; + uint32_t event_type = le32toh(log_entry->event_type); + + printf("TCPA log entry %u:\n", ++counter); + printf("\tPCR: %d\n", le32toh(log_entry->pcr)); + if (event_type >= ARRAY_SIZE(tpm_event_types)) + printf("\tEvent type: Unknown (0x%x)\n", event_type); + else + printf("\tEvent type: %s\n", tpm_event_types[event_type]); + printf("\tDigest: "); + print_hex(log_entry->digest, SHA1_DIGEST_SIZE); + current += sizeof(struct tcpa_log_entry); + len = le32toh(log_entry->event_data_size); + if (len != 0) { + current += len; + printf("\tEvent data: %.*s\n", len, log_entry->event); + } else { + printf("\tEvent data not provided\n"); + } + } +} + +static uint32_t print_tpm2_digests(struct tcg_pcr_event2_header *log_entry) +{ + unsigned int i; + uintptr_t current = (uintptr_t)log_entry->digests; + + for (i = 0; i < le32toh(log_entry->digest_count); i++) { + struct tpm_hash_algorithm *hash = (struct tpm_hash_algorithm *)current; + switch (le16toh(hash->hashAlg)) { + case TPM2_ALG_SHA1: + printf("\t\t SHA1: "); + print_hex(hash->digest.sha1, SHA1_DIGEST_SIZE); + current += sizeof(hash->hashAlg) + SHA1_DIGEST_SIZE; + break; + case TPM2_ALG_SHA256: + printf("\t\t SHA256: "); + print_hex(hash->digest.sha256, SHA256_DIGEST_SIZE); + current += sizeof(hash->hashAlg) + SHA256_DIGEST_SIZE; + break; + case TPM2_ALG_SHA384: + printf("\t\t SHA384: "); + print_hex(hash->digest.sha384, SHA384_DIGEST_SIZE); + current += sizeof(hash->hashAlg) + SHA384_DIGEST_SIZE; + break; + case TPM2_ALG_SHA512: + printf("\t\t SHA512: "); + print_hex(hash->digest.sha512, SHA512_DIGEST_SIZE); + current += sizeof(hash->hashAlg) + SHA512_DIGEST_SIZE; + break; + case TPM2_ALG_SM3_256: + printf("\t\t SM3: "); + print_hex(hash->digest.sm3_256, SM3_256_DIGEST_SIZE); + current += sizeof(hash->hashAlg) + SM3_256_DIGEST_SIZE; + break; + default: + die("Unknown hash algorithm\n"); + } + } + + return current - (uintptr_t)&log_entry->digest_count; +} + +static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log) +{ + static uint8_t zero_block[12]; /* Only PCR index, event type and digest count */ + + uintptr_t current; + uint32_t counter = 0; + + printf("TPM2 log:\n"); + printf("\tSpecification: %d.%d%d\n", + tpm2_log->spec_version_major, + tpm2_log->spec_version_minor, + tpm2_log->spec_errata); + printf("\tPlatform class: %s\n", + le32toh(tpm2_log->platform_class) == 0 ? "PC Client" : + le32toh(tpm2_log->platform_class) == 1 ? "Server" : "Unknown"); + + /* Start after the first variable-sized part of the header */ + current = (uintptr_t)&tpm2_log->digest_sizes[le32toh(tpm2_log->num_of_algorithms)]; + /* current is at `uint8_t vendor_info_size` here */ + current += 1 + *(uint8_t *)current; + + while (memcmp((const void *)current, (const void *)zero_block, sizeof(zero_block))) { + uint32_t len; + struct tcg_pcr_event2_header *log_entry = (void *)current; + uint32_t event_type = le32toh(log_entry->event_type); + + printf("TPM2 log entry %u:\n", ++counter); + printf("\tPCR: %d\n", le32toh(log_entry->pcr_index)); + if (event_type >= ARRAY_SIZE(tpm_event_types)) + printf("\tEvent type: Unknown (0x%x)\n", event_type); + else + printf("\tEvent type: %s\n", tpm_event_types[event_type]); + + current = (uintptr_t)&log_entry->digest_count; + if (le32toh(log_entry->digest_count) > 0) { + printf("\tDigests:\n"); + current += print_tpm2_digests(log_entry); + } else { + printf("\tNo digests in this log entry\n"); + current += sizeof(log_entry->digest_count); + } + /* Now event size and event are left to be parsed */ + len = le32toh(*(uint32_t *)current); + current += sizeof(uint32_t); + if (len != 0) { + printf("\tEvent data: %d %.*s\n", len, len, (const char *)current); + current += len; + } else { + printf("\tEvent data not provided\n"); + } + } +} + +/* Dump the tcpa log table in format from specification */ +static void dump_tcpa_std_log(void) +{ + const struct tcpa_spec_entry *tspec_entry; + const struct tcg_efi_spec_id_event *tcg_spec_entry; + uint64_t addr; + size_t size; + struct mapping log_mapping; + + if (tpm_std_log.tag != LB_TAG_TPM_STD_LOG) { + fprintf(stderr, "No TPM log found in coreboot table.\n"); + return; + } + + addr = tpm_std_log.range_start; + size = tpm_std_log.range_size; + + tspec_entry = map_memory(&log_mapping, addr, size); + if (!tspec_entry) + die("Unable to map TCPA log header\n"); + + if (!strcmp((const char *)tspec_entry->signature, TCPA_SPEC_ID_EVENT_SIGNATURE)) { + if (tspec_entry->spec_version_major == 1 && + tspec_entry->spec_version_minor == 2 && + tspec_entry->spec_errata >= 1 && + le32toh(tspec_entry->entry.event_type) == EV_NO_ACTION) { + parse_tpm12_log(tspec_entry); + } else { + fprintf(stderr, "Unknown TCPA log specification\n"); + } + unmap_memory(&log_mapping); + return; + } + + unmap_memory(&log_mapping); + tcg_spec_entry = map_memory(&log_mapping, addr, size); + + if (!strcmp((const char *)tcg_spec_entry->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE)) { + if (tcg_spec_entry->spec_version_major == 2 && + tcg_spec_entry->spec_version_minor == 0 && + le32toh(tcg_spec_entry->event_type) == EV_NO_ACTION) { + parse_tpm2_log(tcg_spec_entry); + } else { + fprintf(stderr, "Unknown TPM2 log specification.\n"); + } + unmap_memory(&log_mapping); + return; + } + + fprintf(stderr, "Unknown TPM log specification: %s\n", + (const char *)tcg_spec_entry->signature); +} + /* dump the tcpa log table */ static void dump_tcpa_log(void) { @@ -1676,8 +1886,12 @@ if (timestamp_type != TIMESTAMPS_PRINT_NONE) dump_timestamps(timestamp_type); - if (print_tcpa_log) - dump_tcpa_log(); + if (print_tcpa_log) { + if (tpm_std_log.tag != LB_TAG_UNUSED) + dump_tcpa_std_log(); + else + dump_tcpa_log(); + } unmap_memory(&lbtable_mapping); -- To view, visit https://review.coreboot.org/c/coreboot/+/68749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib76dc7dec56dd1789a219539a1ac05a958f47a5c Gerrit-Change-Number: 68749 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: [WIP] security/tpm: add TPM log format as per 2.0 spec
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel. Hello Michał Żygowski, Maciej Pijanowski, Krystian Hebel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68748 to review the following change. Change subject: [WIP] security/tpm: add TPM log format as per 2.0 spec ...................................................................... [WIP] security/tpm: add TPM log format as per 2.0 spec Used by default for all boards with TPM2 which don't specify log format explicitly. Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Ticket: https://ticket.coreboot.org/issues/422 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- A src/commonlib/include/commonlib/tpm_log_defs.h M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc A src/security/tpm/tpm2_log_serialized.h M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.h A src/security/tpm/tspi/log-tpm2.c 7 files changed, 425 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/68748/1 diff --git a/src/commonlib/include/commonlib/tpm_log_defs.h b/src/commonlib/include/commonlib/tpm_log_defs.h new file mode 100644 index 0000000..18dc82b --- /dev/null +++ b/src/commonlib/include/commonlib/tpm_log_defs.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __TPM_LOG_DEFS_H__ +#define __TPM_LOG_DEFS_H__ + +#include <stdint.h> +#include <commonlib/helpers.h> + +#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE "Spec ID Event03" + +#define TPM2_ALG_ERROR 0x0000 +#define TPM2_ALG_HMAC 0x0005 +#define TPM2_ALG_NULL 0x0010 +#define TPM2_ALG_SHA1 0x0004 +#define TPM2_ALG_SHA256 0x000B +#define TPM2_ALG_SHA384 0x000C +#define TPM2_ALG_SHA512 0x000D +#define TPM2_ALG_SM3_256 0x0012 + +#define SHA1_DIGEST_SIZE 20 +#define SHA256_DIGEST_SIZE 32 +#define SHA384_DIGEST_SIZE 48 +#define SHA512_DIGEST_SIZE 64 +#define SM3_256_DIGEST_SIZE 32 + +#define MAX_HASH_COUNT 4 + +#define EV_PREBOOT_CERT 0x00000000 +#define EV_POST_CODE 0x00000001 +#define EV_UNUSED 0x00000002 +#define EV_NO_ACTION 0x00000003 +#define EV_SEPARATOR 0x00000004 +#define EV_ACTION 0x00000005 +#define EV_EVENT_TAG 0x00000006 +#define EV_S_CRTM_CONTENTS 0x00000007 +#define EV_S_CRTM_VERSION 0x00000008 +#define EV_CPU_MICROCODE 0x00000009 +#define EV_PLATFORM_CONFIG_FLAGS 0x0000000A +#define EV_TABLE_OF_DEVICES 0x0000000B +#define EV_COMPACT_HASH 0x0000000C +#define EV_IPL 0x0000000D +#define EV_IPL_PARTITION_DATA 0x0000000E +#define EV_NONHOST_CODE 0x0000000F +#define EV_NONHOST_CONFIG 0x00000010 +#define EV_NONHOST_INFO 0x00000011 +#define EV_OMIT_BOOT_DEVICE_EVENTS 0x00000012 + +struct tpm_digest_sizes { + uint16_t alg_id; + uint16_t digest_size; +} __packed; + +struct tcg_efi_spec_id_event { + uint32_t pcr_index; + uint32_t event_type; + uint8_t digest[20]; + uint32_t event_size; + uint8_t signature[16]; + uint32_t platform_class; + uint8_t spec_version_minor; + uint8_t spec_version_major; + uint8_t spec_errata; + uint8_t uintn_size; + uint32_t num_of_algorithms; + struct tpm_digest_sizes digest_sizes[0]; /* variable number of members */ + /* uint8_t vendor_info_size; */ + /* uint8_t vendor_info[vendor_info_size]; */ +} __packed; + +#endif diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 254a951..81506b4 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -105,12 +105,16 @@ config USE_TPM_LOG_TPM12 bool default n +config USE_TPM_LOG_TPM2 + bool + default n choice prompt "TPM event log format" depends on TPM_MEASURED_BOOT default TPM_LOG_CB if USE_TPM_LOG_CB default TPM_LOG_TPM12 if TPM1 || USE_TPM_LOG_TPM12 + default TPM_LOG_TPM2 if TPM2 || USE_TPM_LOG_TPM2 config TPM_LOG_CB bool "coreboot's custom format" @@ -121,6 +125,28 @@ help Log per TPM 1.2 specification. See "TCG PC Client Specific Implementation Specification for Conventional BIOS". +config TPM_LOG_TPM2 + bool "TPM 2.0 format" + help + Log per TPM 2.0 specification. + See "TCG PC Client Platform Firmware Profile Specification". + +endchoice + +choice + prompt "TPM2 hashing algorithm" + depends on TPM_MEASURED_BOOT && TPM_LOG_TPM2 + default TPM_HASH_SHA1 if TPM1 + default TPM_HASH_SHA256 if TPM2 + +config TPM_HASH_SHA1 + bool "SHA1" +config TPM_HASH_SHA256 + bool "SHA256" +config TPM_HASH_SHA384 + bool "SHA384" +config TPM_HASH_SHA512 + bool "SHA512" endchoice diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index 4540534..f4a5634 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -67,4 +67,10 @@ postcar-$(CONFIG_TPM_LOG_TPM12) += tspi/log-tpm12.c bootblock-$(CONFIG_TPM_LOG_TPM12) += tspi/log-tpm12.c +ramstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c +romstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c +verstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c +postcar-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c +bootblock-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c + endif # CONFIG_TPM_MEASURED_BOOT diff --git a/src/security/tpm/tpm2_log_serialized.h b/src/security/tpm/tpm2_log_serialized.h new file mode 100644 index 0000000..45f939d --- /dev/null +++ b/src/security/tpm/tpm2_log_serialized.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __TPM2_LOG_SERIALIZED_H__ +#define __TPM2_LOG_SERIALIZED_H__ + +#include <stdint.h> + +#include <commonlib/helpers.h> +#include <commonlib/tpm_log_defs.h> + +#define MAX_TCPA_LOG_ENTRIES 50 +#define TCPA_PCR_HASH_NAME 50 +#define TCPA_PCR_HASH_LEN 10 +/* Assumption of 2K TCPA log size reserved for CAR/SRAM, but depends on hash */ +#define MAX_PRERAM_TCPA_LOG_ENTRIES 15 + +/* + * TPM2.0 log entries can't be generally represented as C structures due to + * varying number of digests and their sizes. However, it works as long as + * we're only using single kind of digests. + */ +#if CONFIG(TPM_LOG_CB) && CONFIG(TPM1) +# define TCPA_DIGEST_MAX_LENGTH SHA1_DIGEST_SIZE +#elif CONFIG(TPM_LOG_CB) && CONFIG(TPM2) +# define TCPA_DIGEST_MAX_LENGTH SHA256_DIGEST_SIZE +#elif CONFIG(TPM_LOG_TPM12) +# define TCPA_DIGEST_MAX_LENGTH SHA1_DIGEST_SIZE +#elif CONFIG(TPM_LOG_TPM2) +# if CONFIG(TPM_HASH_SHA1) +# define TCPA_DIGEST_MAX_LENGTH SHA1_DIGEST_SIZE +# endif +# if CONFIG(TPM_HASH_SHA256) +# define TCPA_DIGEST_MAX_LENGTH SHA256_DIGEST_SIZE +# endif +# if CONFIG(TPM_HASH_SHA384) +# define TCPA_DIGEST_MAX_LENGTH SHA384_DIGEST_SIZE +# endif +# if CONFIG(TPM_HASH_SHA512) +# define TCPA_DIGEST_MAX_LENGTH SHA512_DIGEST_SIZE +# endif +#endif + +#ifndef TCPA_DIGEST_MAX_LENGTH +# error "Misconfiguration: failed to determine TPM hashing algorithm" +#endif + +/* TCG_PCR_EVENT2 */ +struct tcpa_entry { + uint32_t pcr; + uint32_t event_type; + uint32_t digest_count; + uint16_t digest_type; + uint8_t digest[TCPA_DIGEST_MAX_LENGTH]; + uint32_t name_length; + char name[TCPA_PCR_HASH_NAME]; +} __packed; + +struct tcpa_table { + struct tcg_efi_spec_id_event header; /* TCG_PCR_EVENT actually */ + struct tpm_digest_sizes digest_sizes[1]; + uint8_t vendor_info_size; + uint16_t max_entries; + uint16_t num_entries; + struct tcpa_entry entries[0]; /* Variable number of entries */ +} __packed; + +#endif diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 09b7fc0..20b97f4 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -11,6 +11,8 @@ #include <commonlib/tcpa_log_serialized.h> #elif CONFIG(TPM_LOG_TPM12) #include "tpm12_log_serialized.h" +#elif CONFIG(TPM_LOG_TPM2) +#include "tpm2_log_serialized.h" #endif #define TPM_PCR_MAX_LEN 64 diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index ddc25e5..5cdc0e3 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -22,6 +22,19 @@ # define TPM_MEASURE_ALGO VB2_HASH_SHA256 #elif CONFIG(TPM_LOG_TPM12) # define TPM_MEASURE_ALGO VB2_HASH_SHA1 +#elif CONFIG(TPM_LOG_TPM2) +# if CONFIG(TPM_HASH_SHA1) +# define TPM_MEASURE_ALGO VB2_HASH_SHA1 +# endif +# if CONFIG(TPM_HASH_SHA256) +# define TPM_MEASURE_ALGO VB2_HASH_SHA256 +# endif +# if CONFIG(TPM_HASH_SHA384) +# define TPM_MEASURE_ALGO VB2_HASH_SHA384 +# endif +# if CONFIG(TPM_HASH_SHA512) +# define TPM_MEASURE_ALGO VB2_HASH_SHA512 +# endif #endif #ifndef TPM_MEASURE_ALGO diff --git a/src/security/tpm/tspi/log-tpm2.c b/src/security/tpm/tspi/log-tpm2.c new file mode 100644 index 0000000..1d911db --- /dev/null +++ b/src/security/tpm/tspi/log-tpm2.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Unlike log.c this implements TCPA log according to TPM2 specification + * rather then using coreboot-specific log format. + * + * First entry is in TPM1.2 format and serves as a header, the rest are in + * a newer (agile) format which supports SHA256 and multiple hashes, but we + * store only one hash. + * + * This is defined in "TCG EFI Protocol Specification". + */ + +#include <endian.h> +#include <console/console.h> +#include <security/tpm/tspi.h> +#include <security/tpm/tspi/crtm.h> +#include <region_file.h> +#include <string.h> +#include <symbols.h> +#include <cbmem.h> +#include <bootstate.h> +#include <vb2_sha.h> + +static uint16_t tpmalg_from_vb2_hash(enum vb2_hash_algorithm hash_type) +{ + switch (hash_type) { + case VB2_HASH_SHA1: + return TPM2_ALG_SHA1; + case VB2_HASH_SHA256: + return TPM2_ALG_SHA256; + case VB2_HASH_SHA384: + return TPM2_ALG_SHA384; + case VB2_HASH_SHA512: + return TPM2_ALG_SHA512; + + default: + return 0xFF; + } +} + +static struct tcpa_table *tcpa_cbmem_init(void) +{ + static struct tcpa_table *tclt; + if (tclt) + return tclt; + + if (cbmem_possibly_online()) { + size_t tcpa_log_len; + struct tcg_efi_spec_id_event *hdr; + + tclt = cbmem_find(CBMEM_ID_TPM_LOG); + if (tclt) + return tclt; + + tcpa_log_len = sizeof(struct tcpa_table) + + MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); + tclt = cbmem_add(CBMEM_ID_TPM_LOG, tcpa_log_len); + if (!tclt) + return NULL; + + memset(tclt, 0, tcpa_log_len); + hdr = &tclt->header; + + hdr->event_type = htole32(EV_NO_ACTION); + hdr->event_size = htole32(37); + strcpy((char *)hdr->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE); + hdr->platform_class = htole32(0x00); // client platform + hdr->spec_version_minor = 0x00; + hdr->spec_version_major = 0x02; + hdr->spec_errata = 0x00; + hdr->uintn_size = 0x02; // 64-bit UINT + hdr->num_of_algorithms = htole32(1); + hdr->digest_sizes[0].alg_id = htole16(tpmalg_from_vb2_hash(TPM_MEASURE_ALGO)); + hdr->digest_sizes[0].digest_size = htole16(vb2_digest_size(TPM_MEASURE_ALGO)); + + tclt->vendor_info_size = sizeof(tclt->max_entries) + sizeof(tclt->num_entries); + tclt->max_entries = MAX_TCPA_LOG_ENTRIES; + tclt->num_entries = 0; + } + + return tclt; +} + +struct tcpa_table *tcpa_log_init(void) +{ + static struct tcpa_table *tclt; + + /* We are dealing here with pre CBMEM environment. + * If cbmem isn't available use CAR or SRAM */ + if (!cbmem_possibly_online() && + !CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) + return (struct tcpa_table *)_tpm_tcpa_log; + else if (ENV_ROMSTAGE && + !CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) { + tclt = tcpa_cbmem_init(); + if (!tclt) + return (struct tcpa_table *)_tpm_tcpa_log; + } else { + tclt = tcpa_cbmem_init(); + } + + return tclt; +} + +void tcpa_log_dump(void *unused) +{ + int i, j; + struct tcpa_table *tclt; + int hash_size; + const char *alg_name; + + tclt = tcpa_log_init(); + if (!tclt) + return; + + hash_size = vb2_digest_size(TPM_MEASURE_ALGO); + alg_name = vb2_get_hash_algorithm_name(TPM_MEASURE_ALGO); + + printk(BIOS_INFO, "coreboot TCPA measurements:\n\n"); + for (i = 0; i < tclt->num_entries; i++) { + struct tcpa_entry *tce = &tclt->entries[i]; + + printk(BIOS_INFO, " PCR-%u ", le32toh(tce->pcr)); + + for (j = 0; j < hash_size; j++) + printk(BIOS_INFO, "%02x", tce->digest[j]); + + printk(BIOS_INFO, " %s [%s]\n", alg_name, tce->name); + } + printk(BIOS_INFO, "\n"); +} + +void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, + enum vb2_hash_algorithm digest_algo, + const uint8_t *digest, + const size_t digest_len) +{ + struct tcpa_table *tclt; + struct tcpa_entry *tce; + + tclt = tcpa_log_init(); + if (!tclt) { + printk(BIOS_WARNING, "TCPA: Log non-existent!\n"); + return; + } + + if (digest_algo != TPM_MEASURE_ALGO) { + printk(BIOS_WARNING, "TCPA: digest is of unsupported type: %s\n", + vb2_get_hash_algorithm_name(digest_algo)); + return; + } + + if (digest_len != vb2_digest_size(TPM_MEASURE_ALGO)) { + printk(BIOS_WARNING, "TCPA: digest has invalid length: %d\n", (int)digest_len); + return; + } + + if (tclt->num_entries >= tclt->max_entries) { + printk(BIOS_WARNING, "TCPA: TCPA log table is full\n"); + return; + } + + if (!name) { + printk(BIOS_WARNING, "TCPA: TCPA entry name not set\n"); + return; + } + + tce = &tclt->entries[tclt->num_entries++]; + + tce->pcr = htole32(pcr); + tce->event_type = htole32(EV_ACTION); + + tce->digest_count = htole32(1); + tce->digest_type = htole16(tpmalg_from_vb2_hash(TPM_MEASURE_ALGO)); + memcpy(tce->digest, digest, vb2_digest_size(TPM_MEASURE_ALGO)); + + tce->name_length = htole32(TCPA_PCR_HASH_NAME); + strncpy(tce->name, name, TCPA_PCR_HASH_NAME - 1); +} + +void tcpa_preram_log_clear(void) +{ + printk(BIOS_INFO, "TCPA: Clearing coreboot TCPA log\n"); + struct tcpa_table *tclt = (struct tcpa_table *)_tpm_tcpa_log; + tclt->max_entries = MAX_TCPA_LOG_ENTRIES; + tclt->num_entries = 0; +} + +#if !CONFIG(VBOOT_RETURN_FROM_VERSTAGE) +static void recover_tcpa_log(int is_recovery) +{ + struct tcpa_table *preram_log = (struct tcpa_table *)_tpm_tcpa_log; + struct tcpa_table *ram_log = NULL; + int i; + + if (preram_log->num_entries > MAX_PRERAM_TCPA_LOG_ENTRIES) { + printk(BIOS_WARNING, + "TCPA: Pre-RAM TCPA log is too full, possible corruption\n"); + return; + } + + ram_log = tcpa_cbmem_init(); + if (!ram_log) { + printk(BIOS_WARNING, "TCPA: CBMEM not available something went wrong\n"); + return; + } + + for (i = 0; i < preram_log->num_entries; i++) { + struct tcpa_entry *tce = &ram_log->entries[ram_log->num_entries++]; + + tce->pcr = preram_log->entries[i].pcr; + tce->event_type = preram_log->entries[i].event_type; + + tce->digest_count = preram_log->entries[i].digest_count; + tce->digest_type = preram_log->entries[i].digest_type; + memcpy(tce->digest, preram_log->entries[i].digest, sizeof(tce->digest)); + + tce->name_length = preram_log->entries[i].name_length; + strncpy(tce->name, preram_log->entries[i].name, TCPA_PCR_HASH_NAME - 1); + } +} +CBMEM_CREATION_HOOK(recover_tcpa_log); +#endif + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, tcpa_log_dump, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/68748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Gerrit-Change-Number: 68748 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: [WIP] security/tpm: add TPM log format as per 1.2 spec
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

1 0

[M] Change in coreboot[master]: [WIP] security/tpm: make log format configurable via Kconfig
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Tarun Tuli, Michał Żygowski, Maciej Pijanowski, Jason Nien, Subrata Banik, Christian Walter, Kapil Porwal, Tim Wawrzynczak, Nick Vaccaro, Martin Roth, Krystian Hebel. Hello Michał Żygowski, Maciej Pijanowski, Krystian Hebel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68746 to review the following change. Change subject: [WIP] security/tpm: make log format configurable via Kconfig ...................................................................... [WIP] security/tpm: make log format configurable via Kconfig This commit doesn't add any new format options, just makes selecting existing format explicit. It also adds an indirection through NEED_VBOOT_COMPATIBILITY option to be able to add more similar changes in the future without touching the boards. Modifying Google boards that have TPM to select coreboot-specific format as they are likely to depend on it. Ticket: https://ticket.coreboot.org/issues/422 Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/mainboard/google/asurada/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/cherry/Kconfig M src/mainboard/google/corsola/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/daisy/Kconfig M src/mainboard/google/dedede/Kconfig M src/mainboard/google/drallion/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/foster/Kconfig M src/mainboard/google/gale/Kconfig M src/mainboard/google/geralt/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/gru/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kukui/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/nyan_big/Kconfig M src/mainboard/google/nyan_blaze/Kconfig M src/mainboard/google/oak/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/peach_pit/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/google/puff/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/rex/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/smaug/Kconfig M src/mainboard/google/storm/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/veyron/Kconfig M src/mainboard/google/veyron_mickey/Kconfig M src/mainboard/google/veyron_rialto/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/google/zork/Kconfig M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.h 52 files changed, 106 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/68746/1 diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 46a0327..db9aa72 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -26,6 +26,7 @@ select SPI_TPM if VBOOT select TPM_GOOGLE_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select NEED_VBOOT_COMPATIBILITY select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index f503d46..434e66d 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -13,6 +13,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select SOC_INTEL_BROADWELL config BOARD_GOOGLE_AURON_PAINE diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index a2c435b..901a133 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -10,6 +10,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_ITE_IT8772F diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index f342432..f258238 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -31,6 +31,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 49ac7d2..115a942 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select NORTHBRIDGE_INTEL_SANDYBRIDGE select SANDYBRIDGE_VBOOT_IN_ROMSTAGE select SERIRQ_CONTINUOUS_MODE # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index 2816f9b..c236a47 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -27,6 +27,7 @@ select I2C_TPM if VBOOT select TPM_GOOGLE_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select NEED_VBOOT_COMPATIBILITY select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select COMMONLIB_STORAGE diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 65d26ef..b48efb8 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -36,6 +36,7 @@ select SPI_TPM if VBOOT select TPM_GOOGLE_TI50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select NEED_VBOOT_COMPATIBILITY select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select DRIVER_ANALOGIX_ANX7625 diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index ac679c7..512d89e 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_HAS_CHROMEOS select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN select SOC_INTEL_BRASWELL select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index 1ccc61f..04a0f79 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -16,6 +16,7 @@ select HAVE_LINEAR_FRAMEBUFFER select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY config MAINBOARD_DIR default "google/daisy" diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 84626ef..c346ace 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -24,6 +24,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_CSE_LITE_SKU diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 916a235..0ed4b19 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -16,6 +16,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select MAINBOARD_USES_IFD_EC_REGION select SMBIOS_SERIAL_FROM_VPD if VPD select SOC_INTEL_COMETLAKE_1 diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 0579c0d..39b9f8b 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -20,6 +20,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select SOC_INTEL_KABYLAKE select SYSTEM_TYPE_CONVERTIBLE select TPM_GOOGLE_CR50 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 8b7811c..d7352b4 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select NO_FADT_8042 select SOC_INTEL_KABYLAKE select SPD_READ_BY_WORD diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index 6a2d28e..77a1c4f 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -13,6 +13,7 @@ select SPI_FLASH_WINBOND select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY config VBOOT select VBOOT_VBNV_FLASH diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig index 76ecb65..adab31c 100644 --- a/src/mainboard/google/gale/Kconfig +++ b/src/mainboard/google/gale/Kconfig @@ -17,6 +17,7 @@ select DRIVERS_UART select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY config VBOOT select VBOOT_DISABLE_DEV_ON_RECOVERY diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig index 11a2d7b..3783af9 100644 --- a/src/mainboard/google/geralt/Kconfig +++ b/src/mainboard/google/geralt/Kconfig @@ -28,6 +28,7 @@ select I2C_TPM if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT select TPM_GOOGLE_TI50 if VBOOT + select NEED_VBOOT_COMPATIBILITY config MAINBOARD_DIR string diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index ff6b1ea..a31683f 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -18,6 +18,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select SOC_INTEL_SKYLAKE select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 23926b6..e67169c 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -48,6 +48,7 @@ select SPI_TPM if GRU_HAS_TPM2 select MAINBOARD_HAS_TPM1 if !GRU_HAS_TPM2 select MAINBOARD_HAS_TPM2 if GRU_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 50bcfa9..252bbb7 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -36,6 +36,7 @@ select I2C_TPM select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 3522787..05e6226 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -21,6 +21,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_DTT diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index a95ac06..d9dd9a3 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -30,6 +30,7 @@ select I2C_TPM if !BOARD_GOOGLE_PIGLIN && !BOARD_GOOGLE_SENOR select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_SENOR + select NEED_VBOOT_COMPATIBILITY config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES if !BOARD_GOOGLE_SENOR diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 4cbad81..554f133 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -9,6 +9,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select SOC_INTEL_BROADWELL select SUPERIO_ITE_IT8772F diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 10524fe..aa891b1 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -25,6 +25,7 @@ select HAVE_ACPI_RESUME select DRIVERS_GENERIC_BH720 select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select DRIVERS_GENERIC_ADAU7002 select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 86dd8f9..e306e68 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -34,6 +34,7 @@ select SPI_TPM if VBOOT select TPM_GOOGLE_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select NEED_VBOOT_COMPATIBILITY select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index e6e4b0b..0877b6d 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 04acaed..eb6bbe7 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -16,6 +16,7 @@ select SPI_FLASH_WINBOND select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select DRIVERS_AS3722_RTC config VBOOT diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 9f4edac..bc6bc21 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -16,6 +16,7 @@ select SPI_FLASH_WINBOND select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select DRIVERS_AS3722_RTC config VBOOT diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 03535e9..d421612 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -15,6 +15,7 @@ select EC_GOOGLE_CHROMEEC_SPI select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 88e37ba..e1eb5ef 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -20,6 +20,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select NO_BOOTBLOCK_CONSOLE select SOC_ESPI select SOC_INTEL_GEMINILAKE diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index dd6df3e..94f33d9 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select NORTHBRIDGE_INTEL_SANDYBRIDGE select SANDYBRIDGE_VBOOT_IN_ROMSTAGE # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index 64abb7c..c389e4a 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -15,6 +15,7 @@ select DRIVER_PARADE_PS8625 select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select MISSING_BOARD_RESET config MAINBOARD_DIR diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 3007bcb..3aee07e 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -13,6 +13,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select SOC_INTEL_KABYLAKE select TPM_GOOGLE_CR50 diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig index 1fe0de5..7a22009 100644 --- a/src/mainboard/google/puff/Kconfig +++ b/src/mainboard/google/puff/Kconfig @@ -23,6 +23,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index f8af00f..a9febe3 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -11,6 +11,7 @@ select MAINBOARD_HAS_CHROMEOS select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select SOC_INTEL_BAYTRAIL config BOARD_GOOGLE_BANJO diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 47d1114..3994894 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -17,6 +17,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select SAR_ENABLE select SOC_INTEL_APOLLOLAKE select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index b56fd58..6395f19 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -18,6 +18,7 @@ select I2C_TPM select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_BASEBOARD_REX diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 37c72ad..b6832c3 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -15,6 +15,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select MAINBOARD_USES_IFD_EC_REGION select SAR_ENABLE select SMBIOS_SERIAL_FROM_VPD if VPD diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index cb1932f..fdf3419 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -35,6 +35,7 @@ select I2C_TPM select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select SOC_AMD_MENDOCINO select SOC_AMD_COMMON_BLOCK_ACPI_DPTC if !BOARD_GOOGLE_WINTERHOLD && !BOARD_GOOGLE_MORTHAL select SOC_AMD_COMMON_BLOCK_USE_ESPI diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 437797c..d9a89ca 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index e57da4a..4724ab6 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -18,6 +18,7 @@ select MAINBOARD_DO_DSI_INIT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select DRIVERS_TI_TPS65913_RTC config VBOOT diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index c5ce74b..d329dc0 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -15,6 +15,7 @@ select DRIVERS_UART select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY config VBOOT select VBOOT_DISABLE_DEV_ON_RECOVERY diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 152c57f..4766a79 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY select NORTHBRIDGE_INTEL_SANDYBRIDGE select SANDYBRIDGE_VBOOT_IN_ROMSTAGE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index e409aee..206a512 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -45,6 +45,7 @@ select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_BUBS + select NEED_VBOOT_COMPATIBILITY select SPI_TPM if !BOARD_GOOGLE_BUBS select TPM_GOOGLE_CR50 if !BOARD_GOOGLE_BUBS diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index dbd2b87..63ff70d 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -28,6 +28,7 @@ select SPI_FLASH_WINBOND select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY config VBOOT select VBOOT_VBNV_FLASH diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 2c46965..a950fce 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -13,6 +13,7 @@ select SPI_FLASH_WINBOND select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY config VBOOT select VBOOT_VBNV_FLASH diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 916d8a6..d1a6b5a 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -13,6 +13,7 @@ select SPI_FLASH_WINBOND select I2C_TPM select MAINBOARD_HAS_TPM1 + select NEED_VBOOT_COMPATIBILITY config VBOOT select VBOOT_VBNV_FLASH diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 926a0ca..b93649bf 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -32,6 +32,7 @@ select I2C_TPM if BOARD_GOOGLE_VOLTEER2_TI50 select SPI_TPM if !BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_TIGERLAKE diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 25d4ca4..a7f3637 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -41,6 +41,7 @@ select I2C_TPM select TPM_GOOGLE_CR50 select MAINBOARD_HAS_TPM2 + select NEED_VBOOT_COMPATIBILITY select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index fc339a2..bc52d1a 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -94,6 +94,27 @@ help Enables measured boot (experimental) +# Enable this option to preserve vboot-specific behaviour +config NEED_VBOOT_COMPATIBILITY + bool + default n + +config USE_TPM_LOG_CB + bool + default NEED_VBOOT_COMPATIBILITY + +choice + prompt "TPM event log format" + depends on TPM_MEASURED_BOOT + default TPM_LOG_CB if USE_TPM_LOG_CB + +config TPM_LOG_CB + bool "coreboot's custom format" + help + Custom coreboot-specific format of the log derived from TPM1 log format. + +endchoice + config TPM_MEASURED_BOOT_INIT_BOOTBLOCK bool depends on TPM_MEASURED_BOOT && !VBOOT diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index 8f633a8..7083c00 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -55,10 +55,10 @@ ramstage-y += tspi/crtm.c postcar-y += tspi/crtm.c -ramstage-y += tspi/log.c -romstage-y += tspi/log.c -verstage-y += tspi/log.c -postcar-y += tspi/log.c -bootblock-y += tspi/log.c +ramstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c +romstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c +verstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c +postcar-$(CONFIG_TPM_LOG_CB) += tspi/log.c +bootblock-$(CONFIG_TPM_LOG_CB) += tspi/log.c endif # CONFIG_TPM_MEASURED_BOOT diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 7157b4d..aae7cb4 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -4,10 +4,13 @@ #define TSPI_H_ #include <security/tpm/tss.h> -#include <commonlib/tcpa_log_serialized.h> #include <commonlib/region.h> #include <vb2_api.h> +#if CONFIG(TPM_LOG_CB) +#include <commonlib/tcpa_log_serialized.h> +#endif + #define TPM_PCR_MAX_LEN 64 #define HASH_DATA_CHUNK_SIZE 1024 diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index bd5bc57..5615d64 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -16,7 +16,15 @@ */ #define TPM_RUNTIME_DATA_PCR 3 -#define TPM_MEASURE_ALGO (CONFIG(TPM1) ? VB2_HASH_SHA1 : VB2_HASH_SHA256) +#if CONFIG(TPM_LOG_CB) && CONFIG(TPM1) +# define TPM_MEASURE_ALGO VB2_HASH_SHA1 +#elif CONFIG(TPM_LOG_CB) && CONFIG(TPM2) +# define TPM_MEASURE_ALGO VB2_HASH_SHA256 +#endif + +#ifndef TPM_MEASURE_ALGO +# error "Misconfiguration: failed to determine TPM hashing algorithm" +#endif /** * Measure digests cached in TCPA log entries into PCRs -- To view, visit https://review.coreboot.org/c/coreboot/+/68746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55 Gerrit-Change-Number: 68746 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: [WIP] security/tpm: improve tlcl_extend() signature
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Krystian Hebel. Hello Michał Żygowski, Maciej Pijanowski, Krystian Hebel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68745 to review the following change. Change subject: [WIP] security/tpm: improve tlcl_extend() signature ...................................................................... [WIP] security/tpm: improve tlcl_extend() signature Until now tcg-2.0/tss.c was just assuming certain buffer size and hash algorithm. Change it to accept digest type, which the call sites know. Also drop `uint8_t *out_digest` parameter which was always `NULL` and was handled only by tcg-1.2 code. Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c 5 files changed, 54 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/68745/1 diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index 24133d9..8eefc11 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -171,7 +171,7 @@ tce->name, tce->pcr); int result = tlcl_extend(tce->pcr, tce->digest, - NULL); + TPM_MEASURE_ALGO); if (result != TPM_SUCCESS) { printk(BIOS_ERR, "TPM: Writing digest" " of %s into PCR failed with error" diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 7bf8d6c..54ba343 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -233,7 +233,7 @@ } printk(BIOS_DEBUG, "TPM: Extending digest for `%s` into PCR %d\n", name, pcr); - result = tlcl_extend(pcr, digest, NULL); + result = tlcl_extend(pcr, digest, digest_algo); if (result != TPM_SUCCESS) { printk(BIOS_ERR, "TPM: Extending hash for `%s` into PCR %d failed.\n", name, pcr); diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index f68e1f4..a85503d 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -10,6 +10,7 @@ #define TSS_H_ #include <types.h> +#include <vb2_sha.h> #include <security/tpm/tss/common/tss_common.h> #include <security/tpm/tss_errors.h> @@ -187,8 +188,8 @@ /** * Perform a TPM_Extend. */ -uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, - uint8_t *out_digest); +uint32_t tlcl_extend(int pcr_num, const uint8_t *digest_data, + enum vb2_hash_algorithm digest_algo); /** * Disable platform hierarchy. Specific to TPM2. The TPM error code is returned. diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index 52bc272..bd45e1b 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -331,25 +331,17 @@ return tlcl_write(TPM_NV_INDEX0, NULL, 0); } -uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, - uint8_t *out_digest) +uint32_t tlcl_extend(int pcr_num, const uint8_t *digest_data, + enum vb2_hash_algorithm digest_algo) { struct s_tpm_extend_cmd cmd; uint8_t response[kTpmResponseHeaderLength + kPcrDigestLength]; - uint32_t result; memcpy(&cmd, &tpm_extend_cmd, sizeof(cmd)); to_tpm_uint32(cmd.buffer + tpm_extend_cmd.pcrNum, pcr_num); - memcpy(cmd.buffer + cmd.inDigest, in_digest, kPcrDigestLength); + memcpy(cmd.buffer + cmd.inDigest, digest_data, kPcrDigestLength); - result = tlcl_send_receive(cmd.buffer, response, sizeof(response)); - if (result != TPM_SUCCESS) - return result; - - if (out_digest) - memcpy(out_digest, response + kTpmResponseHeaderLength, - kPcrDigestLength); - return result; + return tlcl_send_receive(cmd.buffer, response, sizeof(response)); } uint32_t tlcl_get_permissions(uint32_t index, uint32_t *permissions) diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 5d6cbf8..d228c7f 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -118,21 +118,40 @@ return TPM_SUCCESS; } -/* - * The caller will provide the digest in a 32 byte buffer, let's consider it a - * sha256 digest. - */ -uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, - uint8_t *out_digest) +static TPM_ALG_ID tpmalg_from_vb2_hash(enum vb2_hash_algorithm hash_type) +{ + switch (hash_type) { + case VB2_HASH_SHA1: + return TPM_ALG_SHA1; + case VB2_HASH_SHA256: + return TPM_ALG_SHA256; + case VB2_HASH_SHA384: + return TPM_ALG_SHA384; + case VB2_HASH_SHA512: + return TPM_ALG_SHA512; + + default: + return TPM_ALG_ERROR; + } +} + +uint32_t tlcl_extend(int pcr_num, const uint8_t *digest_data, + enum vb2_hash_algorithm digest_type) { struct tpm2_pcr_extend_cmd pcr_ext_cmd; struct tpm2_response *response; + TPM_ALG_ID alg; + + alg = tpmalg_from_vb2_hash(digest_type); + if (alg == TPM_ALG_ERROR) + return TPM_E_HASH_ERROR; pcr_ext_cmd.pcrHandle = HR_PCR + pcr_num; pcr_ext_cmd.digests.count = 1; - pcr_ext_cmd.digests.digests[0].hashAlg = TPM_ALG_SHA256; - memcpy(pcr_ext_cmd.digests.digests[0].digest.sha256, in_digest, - sizeof(pcr_ext_cmd.digests.digests[0].digest.sha256)); + pcr_ext_cmd.digests.digests[0].hashAlg = alg; + /* Always copying to sha512 as it's the largest one */ + memcpy(pcr_ext_cmd.digests.digests[0].digest.sha512, digest_data, + vb2_digest_size(digest_type)); response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); -- To view, visit https://review.coreboot.org/c/coreboot/+/68745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4 Gerrit-Change-Number: 68745 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: coreboot_tables: Drop uart PCI addr
by Arthur Heymans (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68767 to review the following change. Change subject: coreboot_tables: Drop uart PCI addr ...................................................................... coreboot_tables: Drop uart PCI addr This field is unused by all payloads. Only edk2 used this to fill in a different struct but even there the entries goes unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/uart/Kconfig M src/drivers/uart/pl011.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/lib/coreboot_table.c M src/mainboard/emulation/qemu-power8/uart.c M src/soc/intel/quark/Kconfig M src/soc/mediatek/common/uart.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/qcs405/uart.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5420/uart.c M src/soc/ti/am335x/uart.c 17 files changed, 15 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/68767/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index a8fd5cd..5f6a223 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -191,14 +191,6 @@ * decisions as to which dividers to select and their values * to eventually arrive at the desired console baud-rate. */ u32 input_hertz; - - /* UART PCI address: bus, device, function - * 1 << 31 - Valid bit, PCI UART in use - * Bus << 20 - * Device << 15 - * Function << 12 - */ - u32 uart_pci_addr; }; struct cb_console { diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 3f7ff2d..6b5eb59 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -197,14 +197,6 @@ * decisions as to which dividers to select and their values * to eventually arrive at the desired console baud-rate. */ uint32_t input_hertz; - - /* UART PCI address: bus, device, function - * 1 << 31 - Valid bit, PCI UART in use - * Bus << 20 - * Device << 15 - * Function << 12 - */ - uint32_t uart_pci_addr; }; struct lb_console { diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index beba401..a2a7f9f 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -75,14 +75,3 @@ default n help Use uart_platform_refclk to specify the input clock value. - -config UART_PCI_ADDR - hex "UART's PCI bus, device, function address" - default 0x0 - help - Specify zero if the UART is connected to another bus type. - For PCI based UARTs, build the value as: - * 1 << 31 - Valid bit, PCI UART in use - * Bus << 20 - * Device << 15 - * Function << 12 diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 0a73d82..3653262 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -43,7 +43,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index aa8c969..79df37c 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -114,7 +114,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 1834095..79e786b 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -146,7 +146,6 @@ else serial.regwidth = sizeof(uint8_t); serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 2a7ccc5..4df7039 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -109,7 +109,6 @@ serial->baud = new_serial->baud; serial->regwidth = new_serial->regwidth; serial->input_hertz = new_serial->input_hertz; - serial->uart_pci_addr = new_serial->uart_pci_addr; } void lb_add_console(uint16_t consoletype, void *data) diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index 4b1bf32..a2f9116 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -37,7 +37,6 @@ serial.baud = 115200; serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2ecdd37..9783c1d 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -63,14 +63,6 @@ default 3 depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 -# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12 -# Valid bit, PCI UART in use: 1 << 31 -config UART_PCI_ADDR - hex - default 0x800a1000 if ENABLE_BUILTIN_HSUART0 - default 0x800a5000 if ENABLE_BUILTIN_HSUART1 - depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 - ##### # Debug support # The following options provide debug support for the Quark coreboot diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index ba3c71a..11c3452 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -167,7 +167,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = UART_HZ; - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index aba8dd9..77d6de2 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -122,7 +122,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index 98c3d4c..b2cdf67 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -109,7 +109,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 9c50611..c04a773 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -265,7 +265,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 97f9e76..007a980 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -266,7 +266,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index ef03c04..7943651 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -140,7 +140,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index 16a4b11..1268183 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -131,7 +131,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = 0; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c index e3648a9..136d785 100644 --- a/src/soc/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -178,7 +178,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 2; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -- To view, visit https://review.coreboot.org/c/coreboot/+/68767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Gerrit-Change-Number: 68767 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/Kconfig: Add a prompt string for MAINBOARD_PART_NUMBER
by Patrick Georgi (Code Review) 24 Oct '22

24 Oct '22

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68496 ) Change subject: mb/Kconfig: Add a prompt string for MAINBOARD_PART_NUMBER ...................................................................... mb/Kconfig: Add a prompt string for MAINBOARD_PART_NUMBER For some nissa variants, there are build configurations that need to use different blobs, but otherwise are identical. Currently, they use the same choice of board config and configure blob paths appropriately. This avoids duplication within the Kconfig file, but the resulting firmware images can be difficult to distinguish, since they report the same FRID. Add a prompt string for MAINBOARD_PART_NUMBER so it can be overridden and round-tripped through make oldconfig, allowing customisation of the reported FRID and other MAINBOARD_PART_NUMBER-derived values with minimal overhead. BUG=b:253966060 BRANCH=None TEST=CL:3960290 MAINBOARD_PART_NUMBER configs apply successfully Signed-off-by: Sam McNally <sammc(a)chromium.org> Change-Id: I3497d7fa1c04c8fa2592025c771d9dbc65632e6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68496 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/Kconfig 1 file changed, 31 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Reka Norman: Looks good to me, approved diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 8f9b48c..aec996a 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -14,7 +14,7 @@ string config MAINBOARD_PART_NUMBER - string + string "Mainboard part number" config MAINBOARD_VENDOR string "Mainboard vendor name" -- To view, visit https://review.coreboot.org/c/coreboot/+/68496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3497d7fa1c04c8fa2592025c771d9dbc65632e6e Gerrit-Change-Number: 68496 Gerrit-PatchSet: 3 Gerrit-Owner: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/superiotool/nuvoton.c: fix NCT6687D PP LDN typo
by 9elements QA (Code Review) 24 Oct '22

24 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68710 ) Change subject: util/superiotool/nuvoton.c: fix NCT6687D PP LDN typo ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 3 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130433 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130432 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130431 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130430 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130429 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130428 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130427 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130426 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130425 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130424 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130423 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130422 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130421 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130420 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130419 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130418 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca Gerrit-Change-Number: 68710 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 10:56:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/clevo/tgl-u: Avoid indirect includes
by Elyes Haouas (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Felix Singer, Michael Niewöhner. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68701 ) Change subject: mb/clevo/tgl-u: Avoid indirect includes ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68701/comment/87f1622b_ff0d4b38 PS1, Line 7: Clean up includes > Well, IMO "Add missing includes" is not technically correct, since with missing includes that code w […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Gerrit-Change-Number: 68701 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 24 Oct 2022 10:45:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/google/chromec: Host event support of DTTS
by EricKY Cheng (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, Isaac Lee, Tim Wawrzynczak, Jon Murphy, Martin Roth, Tim Van Patten, Moises Garcia, Eric Peers, Karthik Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Isaac Lee, Tim Wawrzynczak, Jon Murphy, Martin Roth, Moises Garcia, Eric Peers, Tim Van Patten, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67793 to look at the new patch set (#11). Change subject: ec/google/chromec: Host event support of DTTS ...................................................................... ec/google/chromec: Host event support of DTTS DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for host event 1/2/9/29. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/67793/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/67793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 Gerrit-Change-Number: 67793 Gerrit-PatchSet: 11 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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