coreboot-gerrit October 2022

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[M] Change in coreboot[master]: coreboot_tables: Drop uart PCI addr
by Arthur Heymans (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Hung-Te Lin, Julius Werner, Arthur Heymans, ron minnich. Arthur Heymans has uploaded a new patch set (#2) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/68767 ) Change subject: coreboot_tables: Drop uart PCI addr ...................................................................... coreboot_tables: Drop uart PCI addr This field is unused by all payloads. Only edk2 used this to fill in a different struct but even there the entries goes unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/uart/Kconfig M src/drivers/uart/pl011.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/lib/coreboot_table.c M src/mainboard/emulation/qemu-power8/uart.c M src/soc/intel/quark/Kconfig M src/soc/mediatek/common/uart.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/qcs405/uart.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5420/uart.c M src/soc/ti/am335x/uart.c M tests/lib/coreboot_table-test.c 18 files changed, 15 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/68767/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Gerrit-Change-Number: 68767 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Add Raptor Lake device IDs
by Kane Chen (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Grace Kao, Tim Wawrzynczak, Nick Vaccaro, Curtis Chen, Lawrence Chang. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68565 ) Change subject: soc/intel/alderlake: Add Raptor Lake device IDs ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54 Gerrit-Change-Number: 68565 Gerrit-PatchSet: 7 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Grace Kao <grace.kao(a)intel.corp-partner.google.com> Gerrit-Attention: Grace Kao <grace.kao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 12:55:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/{adl, cmn}: Allow config to select the OCP W/A
by Tarun Tuli (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Subrata Banik, Kangheui Won, Reka Norman, Tim Wawrzynczak, Nick Vaccaro, Meera Ravindranath. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68309 ) Change subject: soc/intel/{adl, cmn}: Allow config to select the OCP W/A ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Gerrit-Change-Number: 68309 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 12:48:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in qc_blobs[master]: sc7280/boot/shrm: Update qclib blobs binaries from 35 to 40
by Sudheer Amrabadi (Code Review) 24 Oct '22

24 Oct '22

Sudheer Amrabadi has uploaded this change for review. ( https://review.coreboot.org/c/qc_blobs/+/68769 ) Change subject: sc7280/boot/shrm: Update qclib blobs binaries from 35 to 40 ...................................................................... sc7280/boot/shrm: Update qclib blobs binaries from 35 to 40 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org> Change-Id: Ieb376e45ac0f32d2d24a12ebd1c075e509b5b64b --- M sc7280/boot/Pmic.bin M sc7280/boot/QcLib.elf M sc7280/boot/Release_Notes.txt M sc7280/boot/dcb.bin M sc7280/shrm/Release_Notes.txt M sc7280/shrm/shrm.elf 6 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/qc_blobs refs/changes/69/68769/1 diff --git a/sc7280/boot/Pmic.bin b/sc7280/boot/Pmic.bin index a3944f6..b04563f 100644 --- a/sc7280/boot/Pmic.bin +++ b/sc7280/boot/Pmic.bin Binary files differ diff --git a/sc7280/boot/QcLib.elf b/sc7280/boot/QcLib.elf index 4bae3f8..edd30a9 100644 --- a/sc7280/boot/QcLib.elf +++ b/sc7280/boot/QcLib.elf Binary files differ diff --git a/sc7280/boot/Release_Notes.txt b/sc7280/boot/Release_Notes.txt index 0e85da9..913208d 100644 --- a/sc7280/boot/Release_Notes.txt +++ b/sc7280/boot/Release_Notes.txt @@ -1,3 +1,25 @@ +================== Release 00040 ================================ +This Release Notes file covers these blobs: + * dcb.bin + * Pmic.bin + * QcLib.elf + +Version : 00040 + +Release Date : Oct,2022 + +Supported Silicon : SC7280 + +Changes since last version: + * LLVM upgrade to 15.0.0 + +Above Bins were used to generate coreboot image. + +No special instructions, requirements or dependencies, files must be +present in this folder to be pulled in during coreboot build + +Errata : Nothing to report + ================== Release 00035 ================================ This Release Notes file covers these blobs: * dcb.bin diff --git a/sc7280/boot/dcb.bin b/sc7280/boot/dcb.bin index 1456dab..275cf0c 100644 --- a/sc7280/boot/dcb.bin +++ b/sc7280/boot/dcb.bin Binary files differ diff --git a/sc7280/shrm/Release_Notes.txt b/sc7280/shrm/Release_Notes.txt index ff18e62..d034381 100644 --- a/sc7280/shrm/Release_Notes.txt +++ b/sc7280/shrm/Release_Notes.txt @@ -1,3 +1,22 @@ +================== Release 00040 ================================ +This Release Notes file covers these blobs: + * shrm.elf +Version : 00040 + +Release Date : Oct,2022 + +Supported Silicon : SC7280 + +Changes since last version: + * LLVM upgrade to 15.0.0 + +Above Bins were used to generate coreboot image. + +No special instructions, requirements or dependencies, files must be +present in this folder to be pulled in during coreboot build + +Errata : Nothing to report + ================== Release 00035 ================================ This Release Notes file covers these blobs: * shrm.elf diff --git a/sc7280/shrm/shrm.elf b/sc7280/shrm/shrm.elf index a8fc013..a47c20a 100644 --- a/sc7280/shrm/shrm.elf +++ b/sc7280/shrm/shrm.elf Binary files differ -- To view, visit https://review.coreboot.org/c/qc_blobs/+/68769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: Ieb376e45ac0f32d2d24a12ebd1c075e509b5b64b Gerrit-Change-Number: 68769 Gerrit-PatchSet: 1 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: lib/coreboot_table: Simplify API to set up lb_serial
by build bot (Jenkins) (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Hung-Te Lin, Julius Werner, ron minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68768 ) Change subject: lib/coreboot_table: Simplify API to set up lb_serial ...................................................................... Patch Set 1: (1 comment) File src/lib/coreboot_table.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161156): https://review.coreboot.org/c/coreboot/+/68768/comment/848cf52b_3656e26c PS1, Line 114: lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, header);; Statements terminations use 1 semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/68768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Gerrit-Change-Number: 68768 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 12:45:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: lib/coreboot_table: Simplify API to set up lb_serial
by Arthur Heymans (Code Review) 24 Oct '22

24 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68768 ) Change subject: lib/coreboot_table: Simplify API to set up lb_serial ...................................................................... lib/coreboot_table: Simplify API to set up lb_serial Instead of having callbacks into serial console code to set up the coreboot table have the code provide the struct as a return value. This makes it easier to reuse the information as the return value can be used in a different context (e.g. when filling in a FDT). This also removes boilerplate code to set up lb_console entries by setting entry based on the type in struct lb_uart. Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/uart/pl011.c M src/drivers/uart/sifive.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/mainboard/emulation/qemu-power8/uart.c M src/soc/mediatek/common/uart.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/common/qupv3_uart.c M src/soc/qualcomm/common/uart_bitbang.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/uart.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5420/uart.c M src/soc/ti/am335x/uart.c 18 files changed, 66 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/68768/1 diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 3653262..a4a0aa4 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -35,7 +35,7 @@ return read8(&regs->dr); } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; @@ -43,7 +43,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index 31181aa..a9d3db8 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -100,7 +100,9 @@ return 1; } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { + struct lb_serial = {}; + return lb_serial; /* TODO */ } diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 79df37c..0bd9fcd 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -106,7 +106,7 @@ uart8250_tx_flush(uart_platform_base(idx)); } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_IO_MAPPED; @@ -114,7 +114,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); + return serial; } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 79e786b..34adefe 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -133,7 +133,7 @@ uart8250_mem_tx_flush(base); } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; @@ -146,7 +146,6 @@ else serial.regwidth = sizeof(uint8_t); serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 6188ce0..52958ba 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -19,8 +19,7 @@ void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count); -void uart_fill_lb(void *data); -void lb_add_serial(struct lb_serial *serial, void *data); +struct lb_serial get_lb_serial(void); void lb_add_console(uint16_t consoletype, void *data); enum cb_err lb_fill_pcie(struct lb_pcie *pcie); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 4df7039..0d5c150 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -96,19 +96,23 @@ return mem; } -void lb_add_serial(struct lb_serial *new_serial, void *data) +static void lb_add_serial(struct lb_header *header) { - struct lb_header *header = (struct lb_header *)data; struct lb_serial *serial; + struct lb_serial new_serial = get_lb_serial(); + /* Use the base address as a proxy for an invalid struct */ + if (new_serial.baseaddr == 0) + return; serial = (struct lb_serial *)lb_new_record(header); + memcpy(serial, &new_serial, sizeof(*serial)); serial->tag = LB_TAG_SERIAL; serial->size = sizeof(*serial); - serial->type = new_serial->type; - serial->baseaddr = new_serial->baseaddr; - serial->baud = new_serial->baud; - serial->regwidth = new_serial->regwidth; - serial->input_hertz = new_serial->input_hertz; + if (serial->type == LB_SERIAL_TYPE_IO_MAPPED) + lb_add_console(LB_TAG_CONSOLE_SERIAL8250, header); + else + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, header);; + } void lb_add_console(uint16_t consoletype, void *data) @@ -492,7 +496,7 @@ /* Record the serial ports and consoles */ if (CONFIG(CONSOLE_SERIAL)) - uart_fill_lb(head); + lb_add_serial(head); if (CONFIG(CONSOLE_USB)) lb_add_console(LB_TAG_CONSOLE_EHCI, head); diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index a2f9116..1feaf8c 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -28,7 +28,7 @@ { } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; @@ -37,7 +37,6 @@ serial.baud = 115200; serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 11c3452..adcae07 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -159,7 +159,7 @@ mtk_uart_tx_flush(); } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; @@ -167,7 +167,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = UART_HZ; - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 77d6de2..23888d7 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -114,7 +114,7 @@ tegra124_uart_tx_flush(uart_ptr); } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; @@ -122,7 +122,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index b2cdf67..35217a9 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -101,7 +101,7 @@ return tegra210_uart_rx_byte(); } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; @@ -109,7 +109,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/soc/qualcomm/common/qupv3_uart.c b/src/soc/qualcomm/common/qupv3_uart.c index 2086c1d..2348cd0 100644 --- a/src/soc/qualcomm/common/qupv3_uart.c +++ b/src/soc/qualcomm/common/qupv3_uart.c @@ -140,7 +140,7 @@ return (uintptr_t)qup[idx].regs; } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial = {0}; @@ -150,5 +150,5 @@ serial.regwidth = 4; serial.input_hertz = SRC_XO_HZ; - lb_add_serial(&serial, data); + return serial; } diff --git a/src/soc/qualcomm/common/uart_bitbang.c b/src/soc/qualcomm/common/uart_bitbang.c index 943dcf8..54e1cb6 100644 --- a/src/soc/qualcomm/common/uart_bitbang.c +++ b/src/soc/qualcomm/common/uart_bitbang.c @@ -5,9 +5,10 @@ #include <boot/coreboot_tables.h> #include <soc/uart.h> -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { - + struct lb_serial serial = {}; + return serial; } static void set_tx(int line_state) diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index c04a773..236ab64 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -256,7 +256,7 @@ } /* TODO: Implement function */ -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; @@ -265,7 +265,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 15a0998..9459ddf 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -368,6 +368,8 @@ } /* TODO: Implement function */ -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { + struct lb_serial serial = {}; + return serial; } diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 007a980..527567e 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -257,7 +257,7 @@ } #endif -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; @@ -266,7 +266,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 7943651..5907f8d3 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -132,7 +132,7 @@ exynos5_uart_tx_flush(uart); } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; @@ -140,7 +140,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index 1268183..45974fa 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -123,7 +123,7 @@ /* Exynos5250 implements this too. */ } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; @@ -131,7 +131,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } diff --git a/src/soc/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c index 136d785..12fa0c5 100644 --- a/src/soc/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -170,7 +170,7 @@ { } -void uart_fill_lb(void *data) +struct lb_serial get_lb_serial(void) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; @@ -178,7 +178,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 2; serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return serial; } -- To view, visit https://review.coreboot.org/c/coreboot/+/68768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Gerrit-Change-Number: 68768 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP] Documentation/measured_boot.md: document new TPM options
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Krystian Hebel. Hello Michał Żygowski, Maciej Pijanowski, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68752 to look at the new patch set (#2). Change subject: [WIP] Documentation/measured_boot.md: document new TPM options ...................................................................... [WIP] Documentation/measured_boot.md: document new TPM options Change-Id: I6dae8e95c59b440c75e13473eefc4c2cf4fd369b Ticket: https://ticket.coreboot.org/issues/426 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M Documentation/security/vboot/measured_boot.md 1 file changed, 95 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/68752/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dae8e95c59b440c75e13473eefc4c2cf4fd369b Gerrit-Change-Number: 68752 Gerrit-PatchSet: 2 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: [WIP] Documentation/measured_boot.md: document new TPM options
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Krystian Hebel. Hello Michał Żygowski, Maciej Pijanowski, Krystian Hebel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68752 to review the following change. Change subject: [WIP] Documentation/measured_boot.md: document new TPM options ...................................................................... [WIP] Documentation/measured_boot.md: document new TPM options Change-Id: I6dae8e95c59b440c75e13473eefc4c2cf4fd369b Ticket: https://ticket.coreboot.org/issues/426 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M Documentation/security/vboot/measured_boot.md 1 file changed, 95 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/68752/1 diff --git a/Documentation/security/vboot/measured_boot.md b/Documentation/security/vboot/measured_boot.md index 8601bcc..07144d1 100644 --- a/Documentation/security/vboot/measured_boot.md +++ b/Documentation/security/vboot/measured_boot.md @@ -49,20 +49,43 @@ [srtm]: srtm.png ### TCPA eventlog -coreboot makes use of its own TCPA log implementation. Normally the eventlog -specification can be found via the TCG homepage: +There are three supported formats of event logs: +* coreboot-specific format. +* [TPM1.2 Specification][TPM12] (section 3.3.3). +* [TPM2.0 Specification][TPM20] (section 3.3.4). -[UEFI Specification](https://trustedcomputinggroup.org/resource/tcg-efi-platform-… +[TPM12]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementa… +[TPM20]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05… -[BIOS Specification](https://www.trustedcomputinggroup.org/wp-content/uploads/TCG… +#### coreboot-specific format +```c +struct tcpa_entry { + uint32_t pcr; /* PCR number. */ + char digest_type[10]; /* Hash algorithm name. */ + uint8_t digest[64]; /* Digest (tail can be unused). */ + uint32_t digest_length; /* Number of digest bytes used. */ + char name[50]; /* Description of what was hashed. */ +} __packed; -Both of them are not representing firmware measurements in a generalized way. -Therefore we have to implement our own solution. +struct tcpa_table { + uint16_t max_entries; + uint16_t num_entries; + struct tcpa_entry entries[0]; +} __packed; +``` -We decided to provide an easy to understand TCPA log which can be read out -from the operating system and firmware itself. +Single hash per PCR. No magic number or any other way of recognizing it. +Endianness isn't specified. -#### Table Format +In principle can hold any hash with 512 bits or less. In practice, +SHA-1 (for TPM1) and SHA-256 (TPM2) are used. + +Can be parsed by `cbmem`. + +Use NEED_VBOOT_COMPATIBILITY or USE_TPM_LOG_CB kconfig option to select this +format. + +##### Console dump format The first column describes the PCR index used for measurement. The second column is the hash of the raw data. The third column contains the hash algorithm used in the operation. The last column provides @@ -70,6 +93,42 @@ came from, CBFS or FMAP, then the name used to look up the data (region or file name). +#### TPM 1.2 format +Single hash per PCR (always SHA-1). First entry serves as a header, provides +ID and version. Always little endian. + +Can be parsed by at least `cbmem` and Linux (exports in both text and binary +forms). + +Data in vendor info section of the header: +```c +uint16_t max_entries; +uint16_t num_entries; +``` +In endianness of the firmware. Not meant to be stable. + +Use USE_TPM_LOG_TPM12 kconfig option to select this format. + +#### TPM 2.0 format +One or more hashes per PCR, but implementation is limited to single hash (SHA-1, +SHA-256, SHA-384 or SHA-512). First entry is overall compatible with TPM 1.2 and +serves as a header with ID, version and number of hashing algorithms used. +Always little endian. + +Can be parsed by at least `cbmem`, Linux (exports only binary form) and +[Skiboot][skiboot]. + +[skiboot]: https://github.com/open-power/skiboot/ + +Data in vendor info section of the header: +```c +uint16_t max_entries; +uint16_t num_entries; +``` +In endianness of the firmware. Not meant to be stable. + +Use USE_TPM_LOG_TPM2 kconfig option to select this format. + #### Example: ```bash PCR-2 e8f2b57c9ec5ea06d1bbd3240a753974d4c3e7c8cd305c20a8ea26eed906dc89 SHA256 [FMAP: COREBOOT CBFS: bootblock] @@ -120,28 +179,23 @@ environment is necessary. ## Platform Configuration Register -Normally PCR 0-7 are reserved for firmware usage. In coreboot we use just 4 PCR -banks in order to store the measurements. coreboot uses the SHA-1 or SHA-256 -hash algorithm depending on the TPM specification for measurements. PCR-4 to -PCR-7 are left empty. +Normally PCR 0-7 are reserved for firmware usage. In coreboot we use just 3 or 4 +PCR banks in order to store the measurements. PCR-4 to PCR-7 are left empty. -### PCR-0 -_Hash:_ SHA1 +### If NEED_VBOOT_COMPATIBILITY kconfig option is selected by the mainboard +vboot-specific (non-standard) PCR usage. -_Description:_ Google vboot GBB flags. +* PCR-0 - SHA1 of Google vboot GBB flags. +* PCR-1 - SHA1/SHA256 of Google vboot GBB HWID. +* PCR-2 - SHA1/SHA256 of Core Root of Trust for Measurement which includes all stages, + data and blobs. +* PCR-3 - SHA1/SHA256 of runtime data like hwinfo.hex or MRC cache. -### PCR-1 -_Hash:_ SHA1/SHA256 +### If NEED_VBOOT_COMPATIBILITY kconfig option is NOT selected by the mainboard +See [TPM1.2 Specification][TPM12] (section 3.3.3) and +[TPM2.0 Specification][TPM20] (section 3.3.4) for PCR assignment information. -_Description:_ Google vboot GBB HWID. - -### PCR-2 -_Hash:_ SHA1/SHA256 - -_Description:_ Core Root of Trust for Measurement which includes all stages, -data and blobs. - -### PCR-3 -_Hash:_ SHA1/SHA256 - -_Description:_ Runtime data like hwinfo.hex or MRC cache. +* PCR-1 - SHA1 of Google vboot GBB flags, SHA1/SHA256 of Google vboot GBB HWID. +* PCR-2 - SHA1/SHA256 of Core Root of Trust for Measurement which includes all stages, + data and blobs. +* PCR-3 - SHA1/SHA256 of runtime data like hwinfo.hex or MRC cache. -- To view, visit https://review.coreboot.org/c/coreboot/+/68752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dae8e95c59b440c75e13473eefc4c2cf4fd369b Gerrit-Change-Number: 68752 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [WIP] Documentation/measured_boot.md: fix SRTM/DRTM explanations
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

1 0

[M] Change in coreboot[master]: [WIP] security/tpm: make use of PCRs configurable via Kconfig
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Christian Walter, Julius Werner, Krystian Hebel, Yu-Ping Wu. Hello Michał Żygowski, Maciej Pijanowski, Krystian Hebel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68750 to review the following change. Change subject: [WIP] security/tpm: make use of PCRs configurable via Kconfig ...................................................................... [WIP] security/tpm: make use of PCRs configurable via Kconfig At this moment, only GBB flags are moved from PCR-0 to PCR-1 when vboot-compatibility is not enabled. Change-Id: Ib3a192d902072f6f8d415c2952a36522b5bf09f9 Ticket: https://ticket.coreboot.org/issues/424 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/security/tpm/Kconfig M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/crtm.h M src/security/vboot/vboot_logic.c 4 files changed, 39 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/68750/1 diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 81506b4..d3bf1ff 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -166,4 +166,20 @@ Runtime data whitelist of cbfs filenames. Needs to be a space delimited list +config PCR_BOOT_MODE + int + default 0 if NEED_VBOOT_COMPATIBILITY + default 1 +config PCR_HWID + int + default 1 +config PCR_CRTM + int + default 2 +# PCR for measuring data which changes during runtime +# e.g. CMOS, NVRAM... +config PCR_RUNTIME_DATA + int + default 3 + endmenu # Trusted Platform Module (tpm) diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index 8eefc11..aea0069 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -44,7 +44,7 @@ struct region_device fmap; if (fmap_locate_area_as_rdev("FMAP", &fmap) == 0) { - if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "FMAP: FMAP")) { + if (tpm_measure_region(&fmap, CONFIG_PCR_CRTM, "FMAP: FMAP")) { printk(BIOS_ERR, "TSPI: Couldn't measure FMAP into CRTM!\n"); return VB2_ERROR_UNKNOWN; @@ -58,7 +58,7 @@ struct region_device bootblock_fmap; if (fmap_locate_area_as_rdev("BOOTBLOCK", &bootblock_fmap) == 0) { if (tpm_measure_region(&bootblock_fmap, - TPM_CRTM_PCR, + CONFIG_PCR_CRTM, "FMAP: BOOTBLOCK")) return VB2_ERROR_UNKNOWN; } @@ -77,7 +77,7 @@ /* Since none of the above conditions are met let the SOC code measure the * bootblock. This accomplishes for cases where the bootblock is treated * in a special way (e.g. part of IFWI or located in a different CBFS). */ - if (tspi_soc_measure_bootblock(TPM_CRTM_PCR)) { + if (tspi_soc_measure_bootblock(CONFIG_PCR_CRTM)) { printk(BIOS_INFO, "TSPI: Couldn't measure bootblock into CRTM on SoC level!\n"); return VB2_ERROR_UNKNOWN; @@ -122,7 +122,7 @@ switch (type) { case CBFS_TYPE_MRC_CACHE: - pcr_index = TPM_RUNTIME_DATA_PCR; + pcr_index = CONFIG_PCR_RUNTIME_DATA; break; /* * mrc.bin is code executed on CPU, so it @@ -132,13 +132,13 @@ case CBFS_TYPE_STAGE: case CBFS_TYPE_SELF: case CBFS_TYPE_FIT_PAYLOAD: - pcr_index = TPM_CRTM_PCR; + pcr_index = CONFIG_PCR_CRTM; break; default: if (is_runtime_data(name)) - pcr_index = TPM_RUNTIME_DATA_PCR; + pcr_index = CONFIG_PCR_RUNTIME_DATA; else - pcr_index = TPM_CRTM_PCR; + pcr_index = CONFIG_PCR_CRTM; break; } diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index 5cdc0e3..7084fc8 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -8,14 +8,6 @@ #include <types.h> #include <vb2_sha.h> -/* CRTM */ -#define TPM_CRTM_PCR 2 - -/* PCR for measuring data which changes during runtime - * e.g. CMOS, NVRAM... - */ -#define TPM_RUNTIME_DATA_PCR 3 - #if CONFIG(TPM_LOG_CB) && CONFIG(TPM1) # define TPM_MEASURE_ALGO VB2_HASH_SHA1 #elif CONFIG(TPM_LOG_CB) && CONFIG(TPM2) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2230b5ab..1951447 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -187,8 +187,8 @@ static uint32_t extend_pcrs(struct vb2_context *ctx) { - return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || - vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); + return vboot_extend_pcr(ctx, CONFIG_PCR_BOOT_MODE, BOOT_MODE_PCR) || + vboot_extend_pcr(ctx, CONFIG_PCR_HWID, HWID_DIGEST_PCR); } #define EC_EFS_BOOT_MODE_VERIFIED_RW 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/68750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a192d902072f6f8d415c2952a36522b5bf09f9 Gerrit-Change-Number: 68750 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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