coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/clevo/tgl-u: Avoid indirect includes
by Michael Niewöhner (Code Review) 24 Oct '22

24 Oct '22

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68701 ) Change subject: mb/clevo/tgl-u: Avoid indirect includes ...................................................................... mb/clevo/tgl-u: Avoid indirect includes Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68701 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c M src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c 2 files changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c index ebe499d..d8739a2 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/azalia_device.h> +#include <stdint.h> const u32 cim_verb_data[] = { /* Realtek ALC293 */ diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c index 14e81fe..a1cfb037 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/meminit.h> +#include <stdbool.h> #include <variant/romstage.h> void variant_configure_fspm(FSPM_UPD *memupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/68701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Gerrit-Change-Number: 68701 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/clevo/tgl-u: Avoid indirect includes
by Michael Niewöhner (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Felix Singer, Elyes Haouas. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68701 ) Change subject: mb/clevo/tgl-u: Avoid indirect includes ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Gerrit-Change-Number: 68701 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 24 Oct 2022 20:04:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: coreboot_tables: Drop uart PCI addr
by Elyes Haouas (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Arthur Heymans, Hung-Te Lin, Bill XIE, Sean Rhodes, Paul Menzel, Julius Werner, ron minnich. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68767 ) Change subject: coreboot_tables: Drop uart PCI addr ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Gerrit-Change-Number: 68767 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 19:42:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: treewide: Add 'IWYU pragma: export' comment
by Elyes Haouas (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Nico Huber, Martin L Roth, Paul Menzel, Angel Pons, Julius Werner, Kyösti Mälkki. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68332 ) Change subject: treewide: Add 'IWYU pragma: export' comment ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68332/comment/fb9a8914_a467c53a PS11, Line 11: > How did you find all these files? here: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/Do… -- To view, visit https://review.coreboot.org/c/coreboot/+/68332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Gerrit-Change-Number: 68332 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 19:37:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/google/kahlee: use override devicetrees for variants
by 9elements QA (Code Review) 24 Oct '22

24 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68634 ) Change subject: mb/google/kahlee: use override devicetrees for variants ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130524 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130523 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130522 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130521 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130520 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130519 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130518 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130517 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130516 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130515 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130514 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130513 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130512 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130511 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130510 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130509 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 Gerrit-Change-Number: 68634 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 19:28:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP]src/soc/intel/alderlake: Add IBECC to Alderlake
by Maximilian Brune (Code Review) 24 Oct '22

24 Oct '22

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68756 ) Change subject: [WIP]src/soc/intel/alderlake: Add IBECC to Alderlake ...................................................................... [WIP]src/soc/intel/alderlake: Add IBECC to Alderlake Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/68756/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 4cb6066..47a2bf7 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -19,6 +19,41 @@ #include <soc/vr_config.h> #include <stdint.h> +/* Define config parameters for In-Band ECC (IBECC). */ +#define MAX_IBECC_REGIONS 8 + +/* In-Band ECC Operation Mode */ +enum ibecc_mode { + IBECC_MODE_PER_REGION, + IBECC_MODE_NONE, + IBECC_MODE_ALL +}; + +/* Error Injection Control */ +//enum ibecc_err_injection_control { +// IBECC_ERR_INJ_NONE, +// IBECC_ERR_INJ_ +//}; + +struct ibecc_config { + bool enable; + enum ibecc_mode mode; + bool range_enable[MAX_IBECC_REGIONS]; + uint16_t range_base[MAX_IBECC_REGIONS]; + uint16_t range_mask[MAX_IBECC_REGIONS]; + /* IBECC Error Injection Control + 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable + Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject + Uncorrectable Error on insertion counter */ + //uint8_t err_injection_control; + ///* Address to match against for ECC error injection */ + //uint64_t err_injection_address; + ///* Mask to match against for ECC error injection */ + //uint64_t err_injection_mask; + ///* Number of transactions between ECC error injection */ + //uint32_t err_injection_count; +}; + /* Types of different SKUs */ enum soc_intel_alderlake_power_limits { ADL_P_142_242_282_15W_CORE, @@ -271,6 +306,9 @@ /* TCC activation offset */ uint32_t tcc_offset; + /* In-Band ECC (IBECC) configuration */ + struct ibecc_config ibecc; + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. * When enabled memory will be training at two different frequencies. * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index c0bdb0d..63a1d60 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -366,6 +366,20 @@ for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) fill_fspm_params[i](m_cfg, config); + + /* In-Band ECC configuration */ + if (config->ibecc.enable) { + m_cfg->Ibecc = !!config->ibecc.enable; + m_cfg->IbeccOperationMode = config->ibecc.mode; + if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable, + config->ibecc.range_enable); + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeBase, + config->ibecc.range_base); + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeMask, + config->ibecc.range_mask); + } + } } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/68756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e Gerrit-Change-Number: 68756 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP] security/tpm: improve tlcl_extend() signature
by Sergii Dmytruk (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel. Hello Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68745 to look at the new patch set (#2). Change subject: [WIP] security/tpm: improve tlcl_extend() signature ...................................................................... [WIP] security/tpm: improve tlcl_extend() signature Until now tcg-2.0/tss.c was just assuming certain buffer size and hash algorithm. Change it to accept digest type, which the call sites know. Also drop `uint8_t *out_digest` parameter which was always `NULL` and was handled only by tcg-1.2 code. Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c M src/vendorcode/eltan/security/mboot/mboot.c 6 files changed, 56 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/68745/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4 Gerrit-Change-Number: 68745 Gerrit-PatchSet: 2 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/{adl, cmn}: Allow config to select the OCP workaround
by Subrata Banik (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Kangheui Won, Paul Menzel, Reka Norman, Tim Wawrzynczak, Nick Vaccaro, Meera Ravindranath. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68309 ) Change subject: soc/intel/{adl, cmn}: Allow config to select the OCP workaround ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/68309/comment/0e2faa4c_5311c652 PS2, Line 432: W/A > Please write it out? Workaround? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/68309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Gerrit-Change-Number: 68309 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 18:27:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/{adl, cmn}: Allow config to select the OCP workaround
by Subrata Banik (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Subrata Banik, Kangheui Won, Reka Norman, Tim Wawrzynczak, Nick Vaccaro, Meera Ravindranath. Hello build bot (Jenkins), Tarun Tuli, Frans Hendriks, Kangheui Won, Reka Norman, Tim Wawrzynczak, Nick Vaccaro, Meera Ravindranath, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68309 to look at the new patch set (#4). Change subject: soc/intel/{adl, cmn}: Allow config to select the OCP workaround ...................................................................... soc/intel/{adl, cmn}: Allow config to select the OCP workaround This patch introduces a config option for SoC code to choose the applicable SoC workaround. For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE` to apply UFS OCP timeout disable workaround. At present ADL SoC only selects so, and in future MTL and others should check with Intel prior selecting this kconfig. It's the placeholder to add more workaround in required going forward. BUG=none TEST=Able to build and boot Google/Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi/ufs.asl 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/68309/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Gerrit-Change-Number: 68309 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` config
by Subrata Banik (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Ivy Jian, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68771 ) Change subject: mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` config ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68771/comment/9be5cd65_c8bd6873 PS1, Line 15: remaining intact. > Please remove the trailing space. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/68771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c Gerrit-Change-Number: 68771 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 18:23:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit October 2022