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Change subject: soc/intel/xeon_sp: Add functions to store/restore uart state in smm
......................................................................
Patch Set 5: Code-Review+2
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
......................................................................
soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
Enable GPP clk req disabling for disabled PCIe devices. If a clk req
line is enabled for a PCIe device that is not actually present and
enabled then the L1SS could get confused and cause issues with
suspending the SoC.
BUG=b:250009974
TEST=Ran on skyrim proto device, verified that clk reqs are set
appropriately
Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
---
M src/mainboard/amd/chausie/Makefile.inc
M src/mainboard/google/skyrim/Makefile.inc
M src/soc/amd/mendocino/Kconfig
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/fch.c
5 files changed, 27 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/68139/6
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Factor out common GPP clk req code
......................................................................
soc/amd/cezanne: Factor out common GPP clk req code
Factor out the `gpp_dxio_update_clk_req_config` function as it will be
useful for other AMD SoCs.
BUG=b:250009974
TEST=Ran on nipperkin device, verified clk req settings match enabled
devices
Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
A src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
M src/soc/amd/common/block/pci/Kconfig
M src/soc/amd/common/block/pci/Makefile.inc
A src/soc/amd/common/block/pci/pcie_clk_req.c
7 files changed, 142 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/68138/6
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Change subject: mb/google/glados/var/lars: Set SKU ID based on VPD
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/glados/variants/lars/variant.c:
https://review.coreboot.org/c/coreboot/+/68754/comment/b9133f25_58923fd3
PS1, Line 86: LILI
> Is the spelling all upper case?
Chromebook hardware IDs are typically displayed as all uppercase
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Change subject: mb/google/glados/var/lars: Set SKU ID based on VPD
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/glados/variants/lars/variant.c:
https://review.coreboot.org/c/coreboot/+/68754/comment/b3070eef_aa10808d
PS1, Line 86: LILI
Is the spelling all upper case?
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Change subject: soc/intel/{adl, cmn}: Allow config to select the OCP W/A
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/68309/comment/b4632fcc_978afe98
PS2, Line 432: W/A
Please write it out? Workaround?
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Change subject: mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboard
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68626/comment/bd8d26a3_b2b2128e
PS1, Line 10: a converged firmware image
What is a “converged firmware image”?
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Change subject: treewide: Add 'IWYU pragma: export' comment
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68332/comment/1c3c6ad7_00a12450
PS11, Line 11:
How did you find all these files?
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