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[L] Change in coreboot[master]: drivers/ipmi/ocp: add PCIe SEL support
by Jonathan Zhang (Code Review) 24 Oct '22

24 Oct '22

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68758 ) Change subject: drivers/ipmi/ocp: add PCIe SEL support ...................................................................... drivers/ipmi/ocp: add PCIe SEL support Add Kconfig SOC_RAS_BMS_SEL and corresponding support for genearating PCIe error SEL records and sending them to BMC. Add PCIe error definitions. Build the ipmi kcs driver in SMM. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65 --- M src/drivers/ipmi/Makefile.inc M src/drivers/ipmi/ocp/Kconfig M src/drivers/ipmi/ocp/Makefile.inc M src/drivers/ipmi/ocp/ipmi_ocp.h A src/drivers/ipmi/ocp/ipmi_sel.c 5 files changed, 251 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/68758/1 diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 85f3dde..28ff78c 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -8,3 +8,4 @@ romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops_premem.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops.c +smm-$(CONFIG_SOC_RAS_BMC_SEL) += ipmi_kcs.c diff --git a/src/drivers/ipmi/ocp/Kconfig b/src/drivers/ipmi/ocp/Kconfig index 7899e69..a381a34 100644 --- a/src/drivers/ipmi/ocp/Kconfig +++ b/src/drivers/ipmi/ocp/Kconfig @@ -3,3 +3,9 @@ default n help This implements OCP specific IPMI command + +config IPMI_BMC_SEL + bool + default n + help + This implements OCP specific command to generate/send SEL record diff --git a/src/drivers/ipmi/ocp/Makefile.inc b/src/drivers/ipmi/ocp/Makefile.inc index c77ee4a..fc56364 100644 --- a/src/drivers/ipmi/ocp/Makefile.inc +++ b/src/drivers/ipmi/ocp/Makefile.inc @@ -1,4 +1,5 @@ ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c ifeq ($(CONFIG_IPMI_OCP),y) romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ocp_romstage.c +smm-$(CONFIG_IPMI_BMC_SEL) += ipmi_sel.c endif diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.h b/src/drivers/ipmi/ocp/ipmi_ocp.h index bd15aa3..a51c53d 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.h +++ b/src/drivers/ipmi/ocp/ipmi_ocp.h @@ -4,6 +4,7 @@ #define __IPMI_OCP_H #include <commonlib/bsd/cb_err.h> +#include <device/pci_type.h> #define IPMI_NETFN_OEM 0x30 #define IPMI_OEM_SET_PPIN 0x77 @@ -33,6 +34,145 @@ uint8_t boot_dev4; } __packed; +struct pci_dev_fn { + u32 func:15; + u32 dev:5; + u32 bus:12; +}; + +struct ipmi_pci_dev_fn { + uint16_t func:3; + uint16_t dev:5; + uint16_t bus:8; +}; + +struct ipmi_sel_pcie_dev_err { + uint16_t record_id; + uint8_t record_type; + uint8_t general_info; + uint32_t timestamp; + uint16_t aux_loc; + struct ipmi_pci_dev_fn bdf; + uint16_t primary_err_count; + uint8_t secondary_id; + uint8_t primary_id; +} __packed; + +struct iio_port_location { + uint8_t socket:4; + uint8_t sled:2; + uint8_t rsvd:2; +}; + +struct ipmi_sel_iio_err { + uint16_t record_id; + uint8_t record_type; + uint8_t general_info; + uint32_t timestamp; + struct iio_port_location loc; + uint8_t iio_stack_num; + uint8_t rsvd0; + uint8_t rsvd1; + uint8_t iio_err_id; + uint8_t rsvd2; + uint8_t rsvd3; + uint8_t rsvd4; +} __packed; + + +enum fail_type { + PCIE_DPC_EVNT = 0, + PCIE_LER_EVNT = 1, + PCIE_LRTRN_REC = 2, + PCIE_CRC_RETRY = 3, + PCIE_CRPT_DATA_CONTMT = 4, + PCIE_ECRC_EVNT = 5, +}; + +struct ipmi_sel_pcie_dev_fail { + uint16_t record_id; + uint8_t record_type; + uint8_t general_info; + uint32_t timestamp; + enum fail_type type; + uint8_t rsvd0; + uint16_t failure_details1; /* if DPC, DPC sts reg of root port */ + uint16_t failure_details2; /* if DPC, source ID of root port */ + uint8_t rsvd1; + uint8_t rsvd2; +} __packed; + +struct ipmi_config_rsp { + uint8_t board_sku_id; + uint8_t board_rev_id; + uint8_t slot_id; + uint8_t slot_config_id; +} __packed; + +#define SEL_RECORD_ID 0x01 +#define SEL_PCIE_DEV_ERR 0x20 +#define SEL_PCIE_IIO_ERR 0x23 +#define SEL_PCIE_DEV_FAIL_ID 0x29 + +/* PCIE Unified Messages */ + +/* PCIE CE */ +#define RECEIVER_ERROR 0x00 +#define BAD_TLP 0x01 +#define BAD_DLLP 0x02 +#define REPLAY_TIME_OUT 0x03 +#define REPLAY_NUMBER_ROLLOVER 0x04 +#define ADVISORY_NONFATAL_ERROR_STATUS 0x05 +#define CORRECTED_INTERNAL_ERROR_STATUS 0x06 +#define HEADER_LOG_OVERFLOW_STATUS 0x07 + +/* PCIE UCE */ +#define PCI_EXPRESS_DATA_LINK_PROTOCOL_ERROR 0x20 +#define SURPRISE_DOWN_ERROR 0x21 +#define RECEIVED_PCI_EXPRESS_POISONED_TLP 0x22 +#define PCI_EXPRESS_FLOW_CONTROL_PROTOCOL_ERROR 0x23 +#define COMPLETION_TIMEOUT_ON_NP_TRANSACTIONS_OUTSTANDING_ON_PCI_EXPRESS_DMI 0x24 +#define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_TO_BE_COMPLETER_ABORTED 0x25 +#define RECEIVED_PCI_EXPRESS_UNEXPECTED_COMPLETION 0x26 +#define PCI_EXPRESS_RECEIVER_OVERFLOW 0x27 +#define PCI_EXPRESS_MALFORMED_TLP 0x28 +#define ECRC_ERROR_STATUS 0x29 +#define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_UNSUPPORTED 0x2A +#define ACS_VIOLATION 0x2B +#define UNCORRECTABLE_INTERNAL_ERROR_STATUS 0x2C +#define MC_BLOCKED_TLP 0x2D +#define ATOMICOP_EGRESS_BLOCKED_STATUS 0x2E +#define TLP_PREFIX_BLOCKED_ERROR_STATUS 0x2F +#define POISONED_TLP_EGRESS_BLOCKED 0x30 + +/* Root error status (from PCIE spec) */ +#define RECEIVED_ERR_COR_MESSAGE_FROM_DOWNSTREAM_DEVICE 0x50 +#define RECEIVED_ERR_NONFATAL_MESSAGE_FROM_DOWNSTREAM_DEVICE 0x51 +#define RECEIVED_ERR_FATAL_MESSAGE_FROM_DOWNSTREAM_DEVICE 0x52 + +/* DPC Trigger Reason */ +#define DPC_WAS_TRIGGERED_DUE_TO_AN_UNMASKED_UNCORRECTABLE_ERROR 0x53 +#define DPC_WAS_TRIGGERED_DUE_TO_RECEIVING_AN_ERR_NONFATAL 0x54 +#define DPC_WAS_TRIGGERED_DUE_TO_RECEIVING_AN_ERR_FATAL 0x55 +#define DPC_WAS_TRIGGERED_DUE_TO_RP_PIO_ERROR 0x56 +#define DPC_WAS_TRIGGERED_DUE_TO_THE_DPC_SOFTWARE_TRIGGER_BIT 0x57 + +#define OUTBOUND_SWITCH_FIFO_DATA_PARITY_ERROR_DETECTED 0x80 +#define SENT_A_PCI_EXPRESS_COMPLETER_ABORT 0x81 +#define SENT_A_PCI_EXPRESS_UNSUPPORTED_REQUEST 0x82 +#define RECEIVED_COMPLETER_ABORT 0x83 +#define RECEIVED_UNSUPPORTED_REQUEST_COMPLETION_STATUS_FROM_DOWNSTREAM_DEVICE 0x84 +#define RECEIVED_MSI_WRITES_GREATER_THAN_A_DWORD 0x85 +#define OUTBOUND_POISONED_DATA 0x86 +#define PERR_NON_AER 0xA0 +#define SERR_NON_AER 0xA1 + enum cb_err ipmi_set_post_start(const int port); enum cb_err ipmi_set_cmos_clear(void); + +void ipmi_send_to_bmc(unsigned char *data, size_t size); +void ipmi_send_sel_pcie_dev_err(pci_devfn_t bdf, uint16_t prmry_cnt, uint8_t sec_id, + uint8_t prmry_id); +void ipmi_send_sel_pcie_dev_fail(uint16_t sts_reg, uint16_t src_id, enum fail_type code); +void ipmi_send_sel_iio_err(uint8_t iio_stack_num, uint8_t err_id); #endif diff --git a/src/drivers/ipmi/ocp/ipmi_sel.c b/src/drivers/ipmi/ocp/ipmi_sel.c new file mode 100644 index 0000000..e75df24 --- /dev/null +++ b/src/drivers/ipmi/ocp/ipmi_sel.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_kcs.h> +#include <string.h> + +#include "ipmi_ocp.h" + +static int ipmi_add_sel_entry(int port, unsigned char *data, int size) +{ + if (CONFIG(IPMI_KCS)) + return ipmi_kcs_message(port, IPMI_NETFN_STORAGE, 0, IPMI_ADD_SEL_ENTRY, data, + size, NULL, 0); + return 0; +} + +void ipmi_send_to_bmc(unsigned char *data, size_t size) +{ + if (CONFIG(IPMI_KCS)) { + if (CONFIG_BMC_KCS_BASE != 0) { + ipmi_add_sel_entry(CONFIG_BMC_KCS_BASE, data, size); + } else { + printk(BIOS_DEBUG, "\tBMC_ERROR: Unable to send record: Port #:%x\n", + CONFIG_BMC_KCS_BASE); + } + } +} + +void ipmi_send_sel_iio_err(uint8_t iio_stack_num, uint8_t err_id) +{ + struct ipmi_sel_iio_err ubslp; + memset(&ubslp, 0, sizeof(struct ipmi_sel_iio_err)); + ubslp.record_id = SEL_RECORD_ID; + ubslp.record_type = CONFIG_RAS_SEL_VENDOR_ID; + ubslp.general_info = SEL_PCIE_IIO_ERR; + /* ubslp.loc = 0; Only socket 0 support for now */ + ubslp.iio_stack_num = iio_stack_num; + ubslp.iio_err_id = err_id; + ipmi_send_to_bmc((unsigned char *)&ubslp, sizeof(ubslp)); + printk(BIOS_DEBUG, "\tsending PCIE IIO device error record to BMC\n"); + printk(BIOS_DEBUG, "\tstack # = %x\n", ubslp.iio_stack_num); +} + +void ipmi_send_sel_pcie_dev_err(pci_devfn_t bdf, uint16_t prmry_cnt, uint8_t sec_id, + uint8_t prmry_id) +{ + struct ipmi_sel_pcie_dev_err ubslp; + memset(&ubslp, 0, sizeof(struct ipmi_sel_pcie_dev_err)); + struct pci_dev_fn *inbdf = (struct pci_dev_fn *)&bdf; + ubslp.record_id = SEL_RECORD_ID; + ubslp.record_type = CONFIG_RAS_SEL_VENDOR_ID; + ubslp.general_info = SEL_PCIE_DEV_ERR; + ubslp.timestamp = 0; /* BMC will apply timestamp */ + ubslp.aux_loc = 0; + ubslp.bdf.bus = inbdf->bus; + ubslp.bdf.dev = inbdf->dev; + ubslp.bdf.func = inbdf->func >> 12; + ubslp.primary_err_count = prmry_cnt; + ubslp.secondary_id = sec_id; + ubslp.primary_id = prmry_id; + ipmi_send_to_bmc((unsigned char *)&ubslp, sizeof(ubslp)); + printk(BIOS_DEBUG, "\tsending PCIE device error record to BMC\n"); + printk(BIOS_DEBUG, "\tbdf = %x:%x:%x\n", ubslp.bdf.bus, ubslp.bdf.dev, ubslp.bdf.func); + printk(BIOS_DEBUG, "\tubslp.primary_id = %x\n", ubslp.primary_id); + printk(BIOS_DEBUG, "\tsecondary_id = %x\n", ubslp.secondary_id); +} + +void ipmi_send_sel_pcie_dev_fail(uint16_t sts_reg, uint16_t src_id, enum fail_type code) +{ + struct ipmi_sel_pcie_dev_fail ubslp; + memset(&ubslp, 0, sizeof(struct ipmi_sel_pcie_dev_fail)); + ubslp.record_id = SEL_RECORD_ID; + ubslp.record_type = CONFIG_RAS_SEL_VENDOR_ID; + ubslp.general_info = SEL_PCIE_DEV_FAIL_ID; + ubslp.timestamp = 0; /* BMC will apply timestamp */ + ubslp.type = code; + ubslp.failure_details1 = sts_reg; + ubslp.failure_details2 = src_id; + ipmi_send_to_bmc((unsigned char *)&ubslp, sizeof(ubslp)); + printk(BIOS_DEBUG, "\tsending PCI device FAILURE record to BMC\n"); + printk(BIOS_DEBUG, "\terror_code = %x, src_id = %x\n", ubslp.type, + ubslp.failure_details2); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65 Gerrit-Change-Number: 68758 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/ipmi/ipmi_ops.h: add __packed to sel_rec structs
by Jonathan Zhang (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: TangYiwei. Hello TangYiwei, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68757 to review the following change. Change subject: drivers/ipmi/ipmi_ops.h: add __packed to sel_rec structs ...................................................................... drivers/ipmi/ipmi_ops.h: add __packed to sel_rec structs Change-Id: Icfcef684caa253663503eadffc819ad2ab65550f Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> --- M src/drivers/ipmi/ipmi_ops.h 1 file changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/68757/1 diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index 7a92a28..788ae85 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -57,17 +57,17 @@ uint8_t sensor_num; uint8_t event_dir_type; uint8_t event_data[3]; -}; +} __packed; struct oem_ts_spec_sel_rec { uint32_t timestamp; uint8_t manf_id[3]; uint8_t oem_defined[6]; -}; +} __packed; struct oem_nots_spec_sel_rec { uint8_t oem_defined[13]; -}; +} __packed; /* SEL Event Record */ struct sel_event_record { -- To view, visit https://review.coreboot.org/c/coreboot/+/68757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfcef684caa253663503eadffc819ad2ab65550f Gerrit-Change-Number: 68757 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: TangYiwei Gerrit-Attention: TangYiwei Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/ipmi/ipmi_kcs_ops.c: accomodate BMC revision being 0
by Jonathan Zhang (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Johnny Lin, Angel Pons, Tim Chu. Hello build bot (Jenkins), Johnny Lin, Angel Pons, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68685 to look at the new patch set (#2). Change subject: drivers/ipmi/ipmi_kcs_ops.c: accomodate BMC revision being 0 ...................................................................... drivers/ipmi/ipmi_kcs_ops.c: accomodate BMC revision being 0 BMC major/minor revision may be 0. Get the value directly from BMC without checking to accomodate such situation. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Change-Id: I0e08c6d02de8f6efceb69b6d6cebad9d61cfd20e --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 17 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/68685/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e08c6d02de8f6efceb69b6d6cebad9d61cfd20e Gerrit-Change-Number: 68685 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/intelp2m/fields: Add unit tests
by Maxim Polyakov (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Maxim Polyakov. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68673 to look at the new patch set (#3). Change subject: util/intelp2m/fields: Add unit tests ...................................................................... util/intelp2m/fields: Add unit tests Change-Id: I6330855b1c7463a3093b38c54e6cc06c3409009a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/intelp2m/fields/cb/cb_test.go A util/intelp2m/fields/fsp/fsp_test.go A util/intelp2m/fields/raw/raw_test.go A util/intelp2m/fields/test/suite.go 4 files changed, 204 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/68673/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6330855b1c7463a3093b38c54e6cc06c3409009a Gerrit-Change-Number: 68673 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim: Implement touchscreen power sequencing
by Matt DeVillier (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, Martin Roth, Karthik Ramasubramanian. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67778 ) Change subject: mb/google/skyrim: Implement touchscreen power sequencing ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/67778/comment/8db59771_7df2937e PS3, Line 116: /* EN_PP3300_TCHSCR */ : PAD_GPO(GPIO_131, LOW), : /* TCHSCR_RESET_L */ : PAD_GPO(GPIO_136, LOW), > When all the touchscreen modules defined in devicetree could not be probed, we can put these GPIOs as NC? I've thought about that, but not come up with a good idea on how to determine at runtime (which would be necessary for older/existing boards for which we can't backport using FW_CONFIG). My least-worst idea is to create a new i2c touchscreen device driver which contains one or more generic i2c or i2c-hid devices, and could keep track if any present / turn off the GPIOs if none found. But still seems suboptimal to me -- To view, visit https://review.coreboot.org/c/coreboot/+/67778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4d7ac8f951bb94da2216a24dc85a96275c9d449 Gerrit-Change-Number: 67778 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 21:18:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/glados/var/lars: Set SKU ID based on VPD
by Paul Menzel (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Matt DeVillier, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68754 ) Change subject: mb/google/glados/var/lars: Set SKU ID based on VPD ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148462b6f86b25fa8db26ea6e1537d1a5e47984b Gerrit-Change-Number: 68754 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 21:12:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: intelp2m/parset: Add unit test
by Maxim Polyakov (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Maxim Polyakov. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67701 to look at the new patch set (#3). Change subject: intelp2m/parset: Add unit test ...................................................................... intelp2m/parset: Add unit test Also add an interface for printing macros to override this in the test and not create a new gpio file for comparison. Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/parser/parser_test.go A util/intelp2m/parser/test/inteltool_test.log 4 files changed, 286 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/67701/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/67701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461 Gerrit-Change-Number: 67701 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/kahlee: always detect ELAN touchpad
by 9elements QA (Code Review) 24 Oct '22

24 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68672 ) Change subject: mb/google/kahlee: always detect ELAN touchpad ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130541 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130540 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130539 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130538 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130537 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130536 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130535 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130534 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130533 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130532 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130531 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130530 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130529 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130528 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130527 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130526 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d14eedd5d95dd0990ae56775daed9284c03717 Gerrit-Change-Number: 68672 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 20:59:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Implement touchscreen power sequencing
by Karthik Ramasubramanian (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67778 ) Change subject: mb/google/skyrim: Implement touchscreen power sequencing ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/67778/comment/ced03567_af0cf4ec PS3, Line 116: /* EN_PP3300_TCHSCR */ : PAD_GPO(GPIO_131, LOW), : /* TCHSCR_RESET_L */ : PAD_GPO(GPIO_136, LOW), > Yeah, I think that sounds fine. I don't think on the AMD platforms we ever had a bit. I think this definitely makes a good reason to have a FW_CONFIG bit to indicate the presence of touch screen. An alternate is like Raul mentioned, we should assume that touch screen is present. When all the touchscreen modules defined in devicetree could not be probed, we can put these GPIOs as NC? -- To view, visit https://review.coreboot.org/c/coreboot/+/67778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4d7ac8f951bb94da2216a24dc85a96275c9d449 Gerrit-Change-Number: 67778 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 20:59:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/edk2: Set the correct serial settings for AMD SOCs
by Matt DeVillier (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Sean Rhodes, Martin L Roth, Stefan Reinauer, Arthur Heymans. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68596 ) Change subject: payloads/edk2: Set the correct serial settings for AMD SOCs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > because you don't get serial output on Picasso (and forward) without it […] I agree, but in the meantime this resolves the issue on Zen-based AMD platforms -- To view, visit https://review.coreboot.org/c/coreboot/+/68596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70630d21bbdb21f2aa8cbaeb3e842629b97af3ba Gerrit-Change-Number: 68596 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 24 Oct 2022 20:05:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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