coreboot-gerrit January 2022

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Change in coreboot[master]: nb/intel/sandybridge: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37200 ) Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/sandybridge: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..1745b98 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,6 +20,7 @@ select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..441844e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -19,6 +19,7 @@ #include <commonlib/region.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <arch/cpu.h> #include <device/mmio.h> @@ -422,6 +423,7 @@ report_memory_config(); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) save_timings(&ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 29c766a..9e70fc1 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -17,6 +17,7 @@ #include <console/usb.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <device/device.h> #include <device/pci_ops.h> @@ -451,6 +452,7 @@ hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); } + setup_romstage_wb_cbmem_cache(); cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/37200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Gerrit-Change-Number: 37200 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37197 ) Change subject: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed ...................................................................... drivers/amd/agesa/romstage: Only mark cbmem as UC if needed Now cbmem is flushed to dram before calling postcar stage. UNTESTED. Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/mtrr_fixme.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37197/1 diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index bbb9eb0..9e63425 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -51,6 +51,10 @@ if (s3resume) return; + /* We worry about cbmem hitting dram later */ + if (clflush_supported()) + return; + /* For normal path, INIT_POST has returned with all * memory set WB cacheable. But we need CBMEM as UC * to make CAR teardown with invalidation without -- To view, visit https://review.coreboot.org/c/coreboot/+/37197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3 Gerrit-Change-Number: 37197 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: nb/intel/nehalem: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37201 ) Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/nehalem: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841..bbea9e7 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index fe5d5c9..0fb9b8d 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4756,6 +4756,7 @@ udelay(1000); dump_timings(&info); + setup_romstage_wb_cbmem_cache(); cbmem_wasnot_inited = cbmem_recovery(s3resume); if (!s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: [WIP]soc/intel/apl: Cache CBMEM and compress postcar
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48207 ) Change subject: [WIP]soc/intel/apl: Cache CBMEM and compress postcar ...................................................................... [WIP]soc/intel/apl: Cache CBMEM and compress postcar Copying WP to WB seems to slow things down but OTOH reducing the size speeds things up. There seems to be no speedup, only a size reduction. Change-Id: I0f0b3f54a489a584c3e28fcc1650e6e1bbae2801 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mtrr/cbmem_cache.c M src/soc/intel/apollolake/Kconfig 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/48207/1 diff --git a/src/cpu/x86/mtrr/cbmem_cache.c b/src/cpu/x86/mtrr/cbmem_cache.c index de5ed8b..8e63315 100644 --- a/src/cpu/x86/mtrr/cbmem_cache.c +++ b/src/cpu/x86/mtrr/cbmem_cache.c @@ -21,7 +21,7 @@ while (1) { /* Do some sanity check before it gets absurdly big. */ - if (mtrr_size > 64 * MiB) { + if (mtrr_size > 256 * MiB) { printk(BIOS_WARNING, "Not caching cbmem, too large region requested!\n"); return -1; } diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4f762a9..0fdd708 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -109,6 +109,8 @@ select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI select HAVE_ASAN_IN_ROMSTAGE + select X86_CLFLUSH_CAR + select ROMSTAGE_CBMEM_CACHED config MAX_CPUS int -- To view, visit https://review.coreboot.org/c/coreboot/+/48207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f0b3f54a489a584c3e28fcc1650e6e1bbae2801 Gerrit-Change-Number: 48207 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: WIP: update blobs repo submodule
by Martin Kepplinger (Code Review) 06 Aug '23

06 Aug '23

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33197 Change subject: WIP: update blobs repo submodule ...................................................................... WIP: update blobs repo submodule Change-Id: I12fc447ee78d986f93f4c39bac282cb6a9a73814 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33197/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index ca6cfcd..8147d6b 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 +Subproject commit 8147d6b601050f6fac6f4c5ccfd8cdadbe3507de -- To view, visit https://review.coreboot.org/c/coreboot/+/33197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12fc447ee78d986f93f4c39bac282cb6a9a73814 Gerrit-Change-Number: 33197 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: [NOTFORMERGE]3rdparty/blobs: Update submodule pointer
by Arthur Heymans (Code Review) 06 Aug '23

06 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43902 ) Change subject: [NOTFORMERGE]3rdparty/blobs: Update submodule pointer ...................................................................... [NOTFORMERGE]3rdparty/blobs: Update submodule pointer Use microcode for Intel family 6, model 0x37, stepping 8 from 3rdparty/intel-microcode as this a more recent version. Change-Id: Id886c5d71cc8b8a4f2caa9bea847cf6cfba5660b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M 3rdparty/blobs M src/soc/intel/baytrail/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/43902/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index bbe5d99..2fbe86c 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit bbe5d99780d2d085e92d9bae2c0f7b6787419d72 +Subproject commit 2fbe86cf5e298ba189b418196ec1c522d6dbc49a diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 451f29e..25cd261 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -62,7 +62,7 @@ postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin \ - 3rdparty/intel-microcode/intel-ucode/06-37-09 + 3rdparty/intel-microcode/intel-ucode/06-37-* CPPFLAGS_common += -Isrc/soc/intel/baytrail/include -- To view, visit https://review.coreboot.org/c/coreboot/+/43902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id886c5d71cc8b8a4f2caa9bea847cf6cfba5660b Gerrit-Change-Number: 43902 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: [WIP] mb/hp: Add EliteBook 820 G2
by Iru Cai (vimacs) (Code Review) 05 Aug '23

05 Aug '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46630 to review the following change. Change subject: [WIP] mb/hp: Add EliteBook 820 G2 ...................................................................... [WIP] mb/hp: Add EliteBook 820 G2 Currently it boots to SeaBIOS. Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/mainboard/hp/820g2/Kconfig A src/mainboard/hp/820g2/Kconfig.name A src/mainboard/hp/820g2/Makefile.inc A src/mainboard/hp/820g2/acpi/ec.asl A src/mainboard/hp/820g2/acpi/superio.asl A src/mainboard/hp/820g2/acpi_tables.c A src/mainboard/hp/820g2/board_info.txt A src/mainboard/hp/820g2/devicetree.cb A src/mainboard/hp/820g2/dsdt.asl A src/mainboard/hp/820g2/gma-mainboard.ads A src/mainboard/hp/820g2/gpio.c A src/mainboard/hp/820g2/hda_verb.c A src/mainboard/hp/820g2/mainboard.c A src/mainboard/hp/820g2/pei_data.c A src/mainboard/hp/820g2/romstage.c 15 files changed, 444 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/1 diff --git a/src/mainboard/hp/820g2/Kconfig b/src/mainboard/hp/820g2/Kconfig new file mode 100644 index 0000000..f617551 --- /dev/null +++ b/src/mainboard/hp/820g2/Kconfig @@ -0,0 +1,34 @@ +if BOARD_HP_820_G2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select SOC_INTEL_BROADWELL + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/820g2" + +config MAINBOARD_PART_NUMBER + string + default "EliteBook 820 G2" + +config VGA_BIOS_FILE + string + default "pci8086,1616.rom" + +config VGA_BIOS_ID + string + default "8086,1616" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/hp/820g2/Kconfig.name b/src/mainboard/hp/820g2/Kconfig.name new file mode 100644 index 0000000..3fcf1a1 --- /dev/null +++ b/src/mainboard/hp/820g2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_820_G2 + bool "EliteBook 820 G2" diff --git a/src/mainboard/hp/820g2/Makefile.inc b/src/mainboard/hp/820g2/Makefile.inc new file mode 100644 index 0000000..2543ee7 --- /dev/null +++ b/src/mainboard/hp/820g2/Makefile.inc @@ -0,0 +1,4 @@ +romstage-y += gpio.c +romstage-y += pei_data.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += pei_data.c diff --git a/src/mainboard/hp/820g2/acpi/ec.asl b/src/mainboard/hp/820g2/acpi/ec.asl new file mode 100644 index 0000000..d39c59a --- /dev/null +++ b/src/mainboard/hp/820g2/acpi/ec.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 6) +/* FIXME: EC support */ +} diff --git a/src/mainboard/hp/820g2/acpi/superio.asl b/src/mainboard/hp/820g2/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/820g2/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/820g2/acpi_tables.c b/src/mainboard/hp/820g2/acpi_tables.c new file mode 100644 index 0000000..ca6f64b --- /dev/null +++ b/src/mainboard/hp/820g2/acpi_tables.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <arch/ioapic.h> +#include <soc/acpi.h> +#include <soc/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} diff --git a/src/mainboard/hp/820g2/board_info.txt b/src/mainboard/hp/820g2/board_info.txt new file mode 100644 index 0000000..db677c6 --- /dev/null +++ b/src/mainboard/hp/820g2/board_info.txt @@ -0,0 +1,2 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/hp/820g2/devicetree.cb b/src/mainboard/hp/820g2/devicetree.cb new file mode 100644 index 0000000..57cf333 --- /dev/null +++ b/src/mainboard/hp/820g2/devicetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/broadwell # FIXME: check these values + register "alt_gp_smi_en" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000402e9" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpe0_en_1" = "0" + register "gpe0_en_2" = "0" + register "gpe0_en_3" = "0" + register "gpe0_en_4" = "0" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "pcie_port_coalesce" = "1" + register "pcie_port_force_aspm" = "0" + register "sata_devslp_disable" = "0" + register "sata_devslp_mux" = "0" + register "sata_port0_gen3_dtle" = "0x0" + register "sata_port0_gen3_tx" = "0x0" + register "sata_port1_gen3_dtle" = "0x0" + register "sata_port1_gen3_tx" = "0x0" + register "sata_port2_gen3_dtle" = "0x0" + register "sata_port2_gen3_tx" = "0x0" + register "sata_port3_gen3_dtle" = "0x0" + register "sata_port3_gen3_tx" = "0x0" + register "sata_port_map" = "0xa" + register "sio_acpi_mode" = "0" + register "sio_i2c0_voltage" = "0" + register "sio_i2c1_voltage" = "0" + device cpu_cluster 0x0 on + device lapic 0x0 on + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge + subsystemid 0x103c 0x225a + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x225a + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x103c 0x225a + end + device pci 13.0 off # Smart Sound Audio DSP + end + device pci 14.0 on # xHCI Controller + subsystemid 0x103c 0x225a + end + device pci 15.0 off # Serial I/O DMA + end + device pci 15.1 off # I2C0 + end + device pci 15.2 off # I2C1 + end + device pci 15.3 off # GSPI0 + end + device pci 15.4 off # GSPI1 + end + device pci 15.5 off # UART0 + end + device pci 15.6 off # UART1 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x225a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 17.0 off # SDIO + end + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:15a2 + subsystemid 0x103c 0x225a + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x103c 0x225a + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x225a + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x225a + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x225a + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x225a + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge + subsystemid 0x103c 0x225a + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x103c 0x225a + end + device pci 1f.3 on # SMBus + subsystemid 0x103c 0x225a + end + device pci 1f.6 off # Thermal + end + end +end diff --git a/src/mainboard/hp/820g2/dsdt.asl b/src/mainboard/hp/820g2/dsdt.asl new file mode 100644 index 0000000..666115d --- /dev/null +++ b/src/mainboard/hp/820g2/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <soc/intel/broadwell/acpi/platform.asl> + #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/820g2/gma-mainboard.ads b/src/mainboard/hp/820g2/gma-mainboard.ads new file mode 100644 index 0000000..7b90060 --- /dev/null +++ b/src/mainboard/hp/820g2/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/820g2/gpio.c b/src/mainboard/hp/820g2/gpio.c new file mode 100644 index 0000000..b4ef103 --- /dev/null +++ b/src/mainboard/hp/820g2/gpio.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +const struct gpio_config mainboard_gpio_config[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = PCH_GPIO_OUT_LOW, + [3] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [4] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [5] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = PCH_GPIO_OUT_HIGH, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [12] = PCH_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = PCH_GPIO_OUT_HIGH, + [19] = PCH_GPIO_NATIVE, + [20] = PCH_GPIO_NATIVE, + [21] = PCH_GPIO_NATIVE, + [22] = PCH_GPIO_NATIVE, + [23] = PCH_GPIO_NATIVE, + [24] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .reset = GPIO_RESET_RSMRST }, + [25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = PCH_GPIO_OUT_HIGH, + [29] = PCH_GPIO_OUT_HIGH, + [30] = PCH_GPIO_NATIVE, + [31] = PCH_GPIO_NATIVE, + [32] = PCH_GPIO_NATIVE, + [33] = PCH_GPIO_NATIVE, + [34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [35] = PCH_GPIO_NATIVE, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [37] = PCH_GPIO_NATIVE, + [38] = PCH_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [48] = PCH_GPIO_OUT_HIGH, + [49] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [50] = PCH_GPIO_OUT_HIGH, + [51] = PCH_GPIO_OUT_HIGH, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [53] = PCH_GPIO_OUT_HIGH, + [54] = PCH_GPIO_OUT_HIGH, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .owner = GPIO_OWNER_GPIO, + .irqen = GPIO_IRQ_ENABLE, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = PCH_GPIO_OUT_HIGH, + [57] = PCH_GPIO_OUT_LOW, + [58] = PCH_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = PCH_GPIO_OUT_HIGH, + [61] = PCH_GPIO_OUT_LOW, + [62] = PCH_GPIO_NATIVE, + [63] = PCH_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = PCH_GPIO_OUT_LOW, + [66] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [70] = PCH_GPIO_OUT_LOW, + [71] = PCH_GPIO_NATIVE, + [72] = PCH_GPIO_NATIVE, + [73] = PCH_GPIO_NATIVE, + [74] = PCH_GPIO_NATIVE, + [75] = PCH_GPIO_NATIVE, + [76] = PCH_GPIO_NATIVE, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = PCH_GPIO_OUT_LOW, + [81] = PCH_GPIO_NATIVE, + [82] = PCH_GPIO_OUT_HIGH, + [83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [85] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [89] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + PCH_GPIO_END +}; diff --git a/src/mainboard/hp/820g2/hda_verb.c b/src/mainboard/hp/820g2/hda_verb.c new file mode 100644 index 0000000..ed96b9f --- /dev/null +++ b/src/mainboard/hp/820g2/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x00000000, /* Codec Vendor / Device ID: */ + 0x00000000, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0421101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40748605), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/820g2/mainboard.c b/src/mainboard/hp/820g2/mainboard.c new file mode 100644 index 0000000..98cc811 --- /dev/null +++ b/src/mainboard/hp/820g2/mainboard.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/820g2/pei_data.c b/src/mainboard/hp/820g2/pei_data.c new file mode 100644 index 0000000..90c45f6 --- /dev/null +++ b/src/mainboard/hp/820g2/pei_data.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 1; + + /* FIXME: check this */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[2] = 0xa4; + pei_data->dq_pins_interleaved = 0; + + /* FIXME: USB2 ports */ + pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_DOCK); + pei_data_usb2_port(pei_data, 1, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 2, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + pei_data_usb2_port(pei_data, 4, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + + /* FIXME: USB3 ports */ + pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); +} diff --git a/src/mainboard/hp/820g2/romstage.c b/src/mainboard/hp/820g2/romstage.c new file mode 100644 index 0000000..8fc2f9e --- /dev/null +++ b/src/mainboard/hp/820g2/romstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> + +void mainboard_pre_raminit(struct romstage_params *rp) +{ + /* Fill out PEI DATA */ + mainboard_fill_pei_data(&rp->pei_data); +} + +void mainboard_post_raminit(struct romstage_params *rp) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Gerrit-Change-Number: 46630 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 37

Change in coreboot[master]: payloads/external/Makefile.inc: Clean up targets
by Arthur Heymans (Code Review) 04 Aug '23

04 Aug '23

Hello Martin Roth, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36460 to review the following change. Change subject: payloads/external/Makefile.inc: Clean up targets ...................................................................... payloads/external/Makefile.inc: Clean up targets - Combine the short target name with the filename. - All targets depend on top level dotconfig. - Payload targets depend on their payload .config. - Add .PHONY target for the short target names. - Add additional short target names grub, uboot, and memtest. - Remove reversed dependencies of config files on the output. - Set SeaBIOS vgabios target at same level as main SeaBIOS target to prevent rebuilds because of the vbios being included. This fixes an issue with SeaBIOS and Filo rebuilding every time. Change-Id: I917c4cce46461ed15212a86dc01b703f818aba23 Signed-off-by: Martin Roth <martinroth(a)google.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/Makefile.inc 1 file changed, 18 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36460/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index f6417fd..cdc5552 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -17,14 +17,20 @@ ## ###################################################################### + +SEABIOS_DIR=payloads/external/SeaBIOS/seabios +SEABIOS_OUT=$(SEABIOS_DIR)/out +FILO_DIR=payloads/external/FILO/filo +FILO_OUT=$(FILO_DIR)/build + # set up payload config and version files for later inclusion ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) -PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config -PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/autoversion.h +PAYLOAD_CONFIG=$(SEABIOS_DIR)/.config +PAYLOAD_VERSION=$(SEABIOS_OUT)/autoversion.h endif ifeq ($(CONFIG_PAYLOAD_FILO),y) -PAYLOAD_CONFIG=payloads/external/FILO/filo/.config -PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h +PAYLOAD_CONFIG=$(FILO_DIR)/.config +PAYLOAD_VERSION=$(FILO_OUT)/version.h endif ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y) PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config @@ -75,10 +81,12 @@ etc/grub.cfg-type := raw etc/grub.cfg-required := the GRUB runtime configuration file ($(CONFIG_GRUB2_RUNTIME_CONFIG_FILE)) +.PHONY: seabios depthcharge grub2 grub tint memtest u-boot uboot ipxe + # SeaBIOS SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) -payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) +$(SEABIOS_OUT)/vgabios.bin $(SEABIOS_OUT)/bios.bin.elf seabios: $(DOTCONFIG) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/SeaBIOS \ HOSTCC="$(HOSTCC)" \ CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) \ @@ -104,10 +112,6 @@ CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \ CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) -payloads/external/SeaBIOS/seabios/out/vgabios.bin: seabios -payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf -payloads/external/SeaBIOS/seabios/out/autoversion.h: payloads/external/SeaBIOS/seabios/out/bios.bin.elf - # add a SeaBIOS bootorder file ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)),) cbfs-files-y += bootorder @@ -117,7 +121,7 @@ # Depthcharge -payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) +payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/depthcharge \ BOARD=$(BOARD) \ MFLAGS= MAKEFLAGS= \ @@ -153,7 +157,7 @@ # FILO -filo: +$(FILO_OUT)/filo.elf filo: $(DOTCONFIG) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/FILO \ HOSTCC="$(HOSTCC)" \ CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \ @@ -161,13 +165,9 @@ CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) -payloads/external/FILO/filo/build/filo.elf: filo -payloads/external/FILO/filo/.config: filo -payloads/external/FILO/filo/build/version.h: filo - # Grub -grub2: $(obj)/config.h +payloads/external/GRUB2/grub2/build/default_payload.elf grub2 grub: $(DOTCONFIG) $(MAKE) -C payloads/external/GRUB2 \ HOSTCC="$(HOSTCC)" \ CC="$(CC_x86_32)" LD="$(LD_x86_32)" \ @@ -179,11 +179,9 @@ CONFIG_GRUB2_REVISION_ID=$(CONFIG_GRUB2_REVISION_ID) \ CONFIG_GRUB2_EXTRA_MODULES=$(CONFIG_GRUB2_EXTRA_MODULES) -payloads/external/GRUB2/grub2/build/default_payload.elf: grub2 - # U-Boot -payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG) +payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot uboot: $(DOTCONFIG) $(MAKE) -C payloads/external/U-Boot \ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) @@ -211,7 +209,7 @@ SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD) endif -payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG) +payloads/external/Memtest86Plus/memtest86plus/memtest memtest: $(DOTCONFIG) $(MAKE) -C payloads/external/Memtest86Plus all \ CC="$(CC_x86_32)" \ LD="$(LD_x86_32)" \ -- To view, visit https://review.coreboot.org/c/coreboot/+/36460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c4cce46461ed15212a86dc01b703f818aba23 Gerrit-Change-Number: 36460 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable
by Name of user not set (Code Review) 03 Aug '23

03 Aug '23

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38495 ) Change subject: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable ...................................................................... vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable FinalRxEnCycle[ByteLane] does not get set in mtthrcSeedTrain.c if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && \ ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) evaluates FALSE. According to Coverity, this could result in cases where RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane] is used with an uninitialized value. Move the FinalRxEnCycle[ByteLane] initial assignment up a line so it gets initialized regardless. Tested on Lenovo G505s. Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1370599 --- M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38495/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c index 991667b..d21c246 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -504,8 +504,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c index 1446f3e..7ea7c56 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -505,8 +505,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); -- To view, visit https://review.coreboot.org/c/coreboot/+/38495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Gerrit-Change-Number: 38495 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/pcengines/apu2: describe serial ports in ACPI
by Michał Żygowski (Code Review) 03 Aug '23

03 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32989 Change subject: mb/pcengines/apu2: describe serial ports in ACPI ...................................................................... mb/pcengines/apu2: describe serial ports in ACPI FreeBSD users had to manually configure serial ports on their installations. Defining serial ports in ACPI save that effort. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 --- A src/mainboard/pcengines/apu2/acpi/superio.asl M src/mainboard/pcengines/apu2/dsdt.asl 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32989/1 diff --git a/src/mainboard/pcengines/apu2/acpi/superio.asl b/src/mainboard/pcengines/apu2/acpi/superio.asl new file mode 100644 index 0000000..c61e3d7 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/superio.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 PC Engines Gmbh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.LIBR) { + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } + + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + } + EndDependentFn () + }) + } +} \ No newline at end of file diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 3bf0ed6..409f03d 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -81,5 +81,8 @@ /* Define the System Indicators for the platform */ #include "acpi/si.asl" + + /* Super IO devices (COM ports) */ + #include "acpi/superio.asl" } /* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 Gerrit-Change-Number: 32989 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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