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Change subject: soc/amd/sabrina: drop PM_ESPI_CS_USE_DATA2 define and eSPI util code
......................................................................
Patch Set 5: Code-Review+1
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Change subject: soc/intel/adlrvp: Add PMC register base for ADL-N
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61148/comment/07aefe3d_e0050486
PS1, Line 9: Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N
> @Paul, can i mark this resolved ?
Can you just add that it was found from the FSP?
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61129 )
Change subject: soc/intel/alderlake: Enable eMMC based on dev enabled
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/61129/comment/9d33a34b_aa1f4ebd
PS7, Line 428: ScsEmmcHs400Enabled
nit: We do not have to use the same names as the FSP UPDs, and actually (although we have not been the most consistent on this, sorry), we prefer to use variable_names_like_this in coreboot. So perhaps a better name would be
`emmc_enable_hs400_mode`
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Change subject: soc/intel/alderlake: Enable eMMC based on dev enabled
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
current ADL FSP has no UPD defined for ScsEmmcEnabled nor ScsEmmcHs400Enabled
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Change subject: soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake N
......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/alderlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/61127/comment/10bb0267_3ec77fe7
PS2, Line 32: Method(_INI) {
: /* Clear register 0x1C20/0x4820 */
: SCSC (PID_EMMC)
: }
> This was initially added and reviewed in this patch, https://review.coreboot.org/c/coreboot/+/25290. […]
Gotcha, can we add comments to this file then explaining why this is done?
File src/soc/intel/alderlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/61127/comment/40b8fbb1_fb3222fc
PS3, Line 37: Method(_PS0, 0, Serialized) {
: Stall (50) // Sleep 50 us
:
: PGEN = 0 // Disable PG
:
: /* Clear register 0x1C20/0x4820 */
: SCSC (PID_EMMC)
:
: /* Set Power State to D0 */
: PMCR = PMCR & 0xFFFC
: TEMP = PMCR
: }
:
: Method(_PS3, 0, Serialized) {
: PGEN = 1 // Enable PG
:
: /* Set Power State to D3 */
: PMCR = PMCR | 0x0003
: TEMP = PMCR
: }
Curious why _PS0 and _PS3 methods are required for the eMMC device? Is the kernel driver not capable of configuring these PCI registers?
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Change subject: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/61126/comment/57e23a1c_e93d328c
PS3, Line 35:
: #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
: /* eMMC Port ID for Alder Lake N */
: #define PID_EMMC 0xa1
: #endif
nit: I don't know if we need the value guarded by an #if, we just have to make sure that only PCH-N code will use the PID
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Change subject: mb/google/brya/var/redrix: Enable MKBP wake
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Patch Set 3: Code-Review+2
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Change subject: soc/intel/xeon_sp/nb_acpi.c: Drop comparison to true
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/purism/librem_skl: disable HECI PCI device
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61408/comment/64065bfa_65c167df
PS2, Line 9: As all librem_skl devices ship with the ME disabled via
: HAP bit and ME firmware "neutralized" via me_cleaner,
: the HECI1 PCI device should be marked off/disabled to
: ensure that heci_init()/heci_reset() will not cause
: a 15s timeout delay when booting.
> Please reflow for 72 characters per line.
Done
https://review.coreboot.org/c/coreboot/+/61408/comment/6fa3d107_9450ccdb
PS2, Line 14:
> What commit introduced the regression?
Done
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Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61408
to look at the new patch set (#3).
Change subject: mb/purism/librem_skl: disable HECI PCI device
......................................................................
mb/purism/librem_skl: disable HECI PCI device
As all librem_skl devices ship with the ME disabled via HAP bit and ME
firmware "neutralized" via me_cleaner, the HECI1 PCI device should be
marked off/disabled to ensure that heci_reset() is not called at the end
of heci_init(), as this causes a 15s timeout delay when booting
(introduced in commit cb2fd20 [soc/intel/common: Add HECI Reset flow in
the CSE driver]).
Change-Id: Ib6bfcfd97e32bb9cf5be33535d77eea8227a8f9f
Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm>
---
M src/mainboard/purism/librem_skl/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/61408/3
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