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Change subject: mb/google/brya: Add GPIO table for nissa
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> Not yet CB:61106
You could rebase this on top of that so it will compile if you want
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Change subject: brya: Add custom PLD fields to device tree
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS7:
Do you (or someone) plan to do this for all of the brya variants?
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61431 )
Change subject: soc/intel/common/cse: Rework `heci_disable` function
......................................................................
soc/intel/common/cse: Rework `heci_disable` function
This patch provides the possible options for SoC users to choose the
applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for
disabling heci1 using non-posted sideband write (inside SMM) after
FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for
disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH
onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for
disabling heci1 using private configuration register (PCR) write.
Applicable for SoC platform prior to CNL PCH.
BUG=none
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
M src/soc/intel/common/block/cse/disable_heci.c
M src/soc/intel/common/block/include/intelblocks/cse.h
4 files changed, 63 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61431/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 23e08e6..cc1c93e 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -14,13 +14,34 @@
Mainboard users to select this config to make HECI1 `function disable`
prior to handing off to payload.
-config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM
+config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI
bool
default y if HECI_DISABLE_USING_SMM
select SOC_INTEL_COMMON_BLOCK_P2SB
help
- Use this config to include common CSE block to make HECI function
- disable in SMM mode
+ From CNL PCH onwards,`HECI1` disabling can only done using
+ non-posted sideband write after FSP-S sets the postboot_sai
+ attribute.
+ Use this config to include common CSE block to make
+ HECI function disable in SMM mode
+
+config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC
+ bool
+ default n
+ select SOC_INTEL_COMMON_BLOCK_PMC
+ help
+ From TGL PCH onwards, an alternative mechanism developed for
+ disabling `HECI1`device using PMC IPC command `0xA9`.
+ Allowing disabling heci1 device using PMC IPC doesn't required
+ to run the operation in SMM.
+
+config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR
+ bool
+ default n
+ select SOC_INTEL_COMMON_BLOCK_PCR
+ help
+ Prior to postboot_sai enforcement since CNL PCH, `HECI1` device were
+ disable using private configuration register (PCR) write.
config SOC_INTEL_CSE_LITE_SKU
bool
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc
index 0e5dcda..c94f8fab 100644
--- a/src/soc/intel/common/block/cse/Makefile.inc
+++ b/src/soc/intel/common/block/cse/Makefile.inc
@@ -1,8 +1,8 @@
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c disable_heci.c
romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
-smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c
ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c
diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c
index 1256fd1..14d5cd1 100644
--- a/src/soc/intel/common/block/cse/disable_heci.c
+++ b/src/soc/intel/common/block/cse/disable_heci.c
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#define __SIMPLE_DEVICE__
+
#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/pci.h>
@@ -15,8 +17,20 @@
#define CSME0_BAR 0x0
#define CSME0_FID 0xb0
+/* Disable HECI using PCR */
+static void heci_disable_using_pcr(void)
+{
+ soc_disable_heci_using_pcr();
+}
+
+/* Disable HECI using PMC IPC communication */
+static void heci_disable_using_pmc(void)
+{
+ cse_disable_mei_devices();
+}
+
/* Disable HECI using Sideband interface communication */
-void heci_disable(void)
+static void heci_disable_using_sbi(void)
{
struct pcr_sbi_msg msg = {
.pid = PID_CSME0,
@@ -46,3 +60,18 @@
/* hide p2sb device */
p2sb_hide();
}
+
+void heci_disable(void)
+{
+ if (!CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+ return;
+
+ if (ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI))
+ return heci_disable_using_sbi();
+ else if (CONFIG(SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC))
+ return heci_disable_using_pmc();
+ else if (CONFIG(SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR))
+ return heci_disable_using_pcr();
+ else
+ printk(BIOS_ERR, "%s Fail to make HECI function disable\n", __func__);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 9bf35da..3fa29d1 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -489,4 +489,11 @@
/* Function to make cse disable using PMC IPC */
bool cse_disable_mei_devices(void);
+/*
+ * SoC override API to make cse disable using PCR
+ * PSF port id for disabling cse is expected to be different between
+ * SoC generation hence, allow SoC to implement the override.
+ */
+void soc_disable_heci_using_pcr(void);
+
#endif // SOC_INTEL_COMMON_CSE_H
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Change subject: soc/intel/common/cse: Make cse_disable_mei_devices a public function
......................................................................
soc/intel/common/cse: Make cse_disable_mei_devices a public function
This patch export cse_disable_mei_devices() function instead of marking
it static. Other IA common code may need to get access to this function
for making `heci1` device disable.
BUG=none
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046
---
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/61430/1
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c
index 4e1c563..3fc4e2b 100644
--- a/src/soc/intel/common/block/cse/cse_eop.c
+++ b/src/soc/intel/common/block/cse/cse_eop.c
@@ -50,7 +50,7 @@
return true;
}
-static bool cse_disable_mei_devices(void)
+bool cse_disable_mei_devices(void)
{
struct pmc_ipc_buffer req = { 0 };
struct pmc_ipc_buffer rsp;
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index a558c32..9bf35da 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -486,4 +486,7 @@
*/
bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf);
+/* Function to make cse disable using PMC IPC */
+bool cse_disable_mei_devices(void);
+
#endif // SOC_INTEL_COMMON_CSE_H
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Change subject: soc/amd/sabrina: add additional UART controllers
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/sabrina/Kconfig:
https://review.coreboot.org/c/coreboot/+/61086/comment/b376b3b0_b259291f
PS5, Line 241: 0xfedd1000
> The PPR seems to have a typo on this address, i.e. it seems to repeat fedc_1xxx incorrectly.
oh, that's a bug in the address space mapping table in the current PPR version.
0xFEDD1000 should be the correct MMIO base address of UART4: the description of the UART registers results in that address when adding the base address to the offset to the UART4 function block and this is also what the reference code uses
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Change subject: soc/amd/sabrina: add additional UART controllers
......................................................................
Patch Set 5: Code-Review+1
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Change subject: soc/intel/common: Add the Primary to Sideband bridge library
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS5:
> Will wait for others to review as well
A bit update by exposing the generic p2sb_dev_sbi_read and p2sb_dev_sbi_write into p2sblib.
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Change subject: soc/amd/sabrina/chipset.cb: update USB ports
......................................................................
Patch Set 5: Code-Review+1
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Change subject: soc/amd/sabrina/include/southbridge: add new I2C_PAD_CTRL bits
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Patch Set 5: Code-Review+2
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