coreboot-gerrit August 2021

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Change in coreboot[master]: mb/supermicro/x10slm-f: Add new superio support to board's Kconfig
by Christoph Pomaska (Code Review) 07 Aug '23

07 Aug '23

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34905 ) Change subject: mb/supermicro/x10slm-f: Add new superio support to board's Kconfig ...................................................................... mb/supermicro/x10slm-f: Add new superio support to board's Kconfig Since the superio support code didnt exist when the board was ported, the Kconfig was not modified yet to add support for the BMC-chip. This commit fixes the missing Kconfig entry. Change-Id: I4f89c2ddcc00327e01d0a83fc13cfa862e6abd70 Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- M src/mainboard/supermicro/x10slm-f/Kconfig 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34905/1 diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 3945c09..6effff2 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -20,15 +20,16 @@ def_bool y select BOARD_ROMSIZE_KB_16384 select CPU_INTEL_HASWELL - select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. + select SOUTHBRIDGE_INTEL_LYNXPOINT select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_LYNXPOINT - select SUPERIO_NUVOTON_NCT6776 + select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. + select SUPERIO_ASPEED_AST2400 # The board's BMC + select SUPERIO_NUVOTON_NCT6776 # the board's superio select SUPERIO_NUVOTON_NCT6776_COM_A config CBFS_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/34905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f89c2ddcc00327e01d0a83fc13cfa862e6abd70 Gerrit-Change-Number: 34905 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

9 45

Change in coreboot[master]: mb/intel/jslrvp: Update pad termination for SD related GPIOs
by Maulik V Vaghela (Code Review) 07 Aug '23

07 Aug '23

Hello Ronak Kanabar, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49022 to review the following change. Change subject: mb/intel/jslrvp: Update pad termination for SD related GPIOs ...................................................................... mb/intel/jslrvp: Update pad termination for SD related GPIOs Change pad termination for SD related GPIO from NONE to NATIVE. This change aligns SoC gpio to be in line with dedede and also fixes the issue of sporadic detection of SD card. BUG=None BRANCH=dedede TEST=Check SD card detection works everytime Change-Id: I0c60cd3edf0ae561846115a0dd3c4fd5b3e26b9c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/49022/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 21e25ab..48ff97b 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -188,25 +188,25 @@ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* SD_SDIO_CMD */ - PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), /* SD_SDIO_D0 */ - PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), /* SD_SDIO_D1 */ - PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), /* SD_SDIO_D2 */ - PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), /* SD_SDIO_D3 */ - PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), /* SD_SDIO_CD_N */ PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), /* SD_SDIO_CLK */ - PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G6, NATIVE, DEEP, NF1), /* SD_SDIO_WP */ PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/49022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c60cd3edf0ae561846115a0dd3c4fd5b3e26b9c Gerrit-Change-Number: 49022 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: Documentation: added more payload links and descriptions
by Zoltan Baldaszti (Code Review) 07 Aug '23

07 Aug '23

Zoltan Baldaszti has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45829 ) Change subject: Documentation: added more payload links and descriptions ...................................................................... Documentation: added more payload links and descriptions Change-Id: I13c10edbc7fbb7017641ab025982c658cbeb3610 Signed-off-by: Zoltan Baldaszti <bztemail(a)gmail.com> --- M Documentation/payloads.md 1 file changed, 35 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45829/1 diff --git a/Documentation/payloads.md b/Documentation/payloads.md index eee841e..bee8393 100644 --- a/Documentation/payloads.md +++ b/Documentation/payloads.md @@ -23,17 +23,45 @@ coreboot payload, but these days this function is available directly in the CorebootPayloadPkg part of its source tree. +## iPXE + +[iPXE](https://ipxe.org) is the leading open source network boot firmware. +It provides a full PXE Implementation enchaced with additional features such +as booting from HTTP, iSCSI, FCoE, AoE, wireless, WAN, infiniband. + ## GRUB2 -GRUB2 was originally written as a bootloader and that's its most popular -purpose, but it can also be compiled as a coreboot payload. +[GRUB2](https://www.gnu.org/software/grub) was originally written as a +bootloader and that's its most popular purpose, but it can also be compiled +as a coreboot payload. + +## U-Boot + +[U-Boot](https://www.denx.de/wiki/U-Boot) is a boot loader for Embedded boards +based on PowerPC, ARM, MIPS and several other processors, which can be +installed in a boot ROM and used to initialize and test the hardware or to +download and run application code. + +## FILO + +[FILO](https://www.coreboot.org/FILO) loads boot images from local filesystem, +without help from legacy BIOS services. Expected usage is to flash it into +the BIOS ROM together with coreboot. + +## BOOTBOOT + +[BOOTBOOT](https://gitlab.com/bztsrc/bootboot) is a multi-platform, +architecture agnostic boot protocol. The protocol describes how to boot an +ELF64 or PE32+ executable inside an initial ram disk image into clean 64 bit +mode. This version uses libpayload to do that. Initrd can be in ROM or on +disk a GPT partition or a file on a FAT formatted ESP partition. ## Linux -There are several projects using Linux as a payload (which was the -configuration that gave coreboot its original name, LinuxBIOS). That kernel is -often rather small and serves to load a current kernel from somewhere, e.g. -disk or network, and run that through the kexec mechanism. +There are several projects using [Linux](https://kernel.org) as a payload +(which was the configuration that gave coreboot its original name, LinuxBIOS). +That kernel is often rather small and serves to load a current kernel from +somewhere, e.g. disk or network, and run that through the kexec mechanism. Two aspects emphasized by proponents of Linux-as-a-payload are the availability of well-tested, battle-hardened drivers (as compared to @@ -51,4 +79,4 @@ For more details have a look at [heads-wiki]. [Heads]: https://github.com/osresearch/heads -[heads-wiki]: http://osresearch.net/ \ No newline at end of file +[heads-wiki]: http://osresearch.net/ -- To view, visit https://review.coreboot.org/c/coreboot/+/45829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c10edbc7fbb7017641ab025982c658cbeb3610 Gerrit-Change-Number: 45829 Gerrit-PatchSet: 1 Gerrit-Owner: Zoltan Baldaszti <bztemail(a)gmail.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: [TEST] abuild: Default to !CHROMEOS
by Nico Huber (Code Review) 07 Aug '23

07 Aug '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49056 ) Change subject: [TEST] abuild: Default to !CHROMEOS ...................................................................... [TEST] abuild: Default to !CHROMEOS Change-Id: I9ae4bc22f70be5b8d8efa35f0cc8aa2d36a5531a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/49056/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 408de12..59da54c 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -655,7 +655,7 @@ clean_objs=false verboseopt='V=0' customizing="" -configoptions="" +configoptions="# CONFIG_CHROMEOS is not set\n" # testclass needs to be undefined if not used for variable expansion to work unset testclass while true ; do -- To view, visit https://review.coreboot.org/c/coreboot/+/49056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ae4bc22f70be5b8d8efa35f0cc8aa2d36a5531a Gerrit-Change-Number: 49056 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: soc/intel/common: Add romstage common stage file
by Bernardo Perez Priego (Code Review) 07 Aug '23

07 Aug '23

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37628 ) Change subject: soc/intel/common: Add romstage common stage file ...................................................................... soc/intel/common: Add romstage common stage file This patch will ensures all intel soc is using common stage files to make coreboot design flow align across all socs. CPU, SA, PCH, MCH programming sequence might be different between socs but the function call should route from same location across all soc. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c --- M src/cpu/intel/car/romstage.c A src/soc/intel/common/basecode/include/intelbasecode/romstage.h A src/soc/intel/common/basecode/romstage/Makefile.inc A src/soc/intel/common/basecode/romstage/romstage.c 4 files changed, 162 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37628/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..55d3c9d 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -52,9 +52,6 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; - if (CONFIG(VBOOT_EARLY_EC_SYNC)) - vboot_sync_ec(); - mainboard_romstage_entry(); /* Check the stack. */ @@ -64,9 +61,6 @@ printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - prepare_and_run_postcar(&early_mtrrs); /* We do not return here. */ } diff --git a/src/soc/intel/common/basecode/include/intelbasecode/romstage.h b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h new file mode 100644 index 0000000..0cebbbf --- /dev/null +++ b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H +#define SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +struct romstage_ops { + void (*soc_early_init)(void); + void (*soc_init)(void); + void (*pch_early_init)(void); + void (*pch_init)(void); + void (*cpu_early_init)(void); + void (*cpu_init)(void); + bool (*is_s3wake)(void); + void (*soc_mem_init_params)(FSP_M_CONFIG *mupd); +}; + +/* SoC Override function */ +struct romstage_ops *soc_get_ops(void); + +#endif diff --git a/src/soc/intel/common/basecode/romstage/Makefile.inc b/src/soc/intel/common/basecode/romstage/Makefile.inc new file mode 100644 index 0000000..29763fb --- /dev/null +++ b/src/soc/intel/common/basecode/romstage/Makefile.inc @@ -0,0 +1 @@ +romstage-y += romstage.c diff --git a/src/soc/intel/common/basecode/romstage/romstage.c b/src/soc/intel/common/basecode/romstage/romstage.c new file mode 100644 index 0000000..55c4ab5 --- /dev/null +++ b/src/soc/intel/common/basecode/romstage/romstage.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <romstage_common.h> +#include <cpu/x86/pae.h> +#include <intelbasecode/romstage.h> +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> + +static const struct romstage_ops s_romstage_ops; + +__weak struct romstage_ops *soc_get_ops(void) +{ + return (struct romstage_ops *)&s_romstage_ops; +} + +void romstage_early_init(void) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + rs_ops->soc_early_init(); + rs_ops->pch_early_init(); + rs_ops->cpu_early_init(); +} + +void romstage_init(void) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + rs_ops->soc_init(); + rs_ops->pch_init(); + rs_ops->cpu_init(); +} + +void romstage_cmn_soc_early_init(void) +{ + systemagent_early_init(); + heci_init(HECI1_BASE_ADDRESS); +} + +void romstage_cmn_soc_init(void) +{ +} + +void romstage_cmn_pch_early_init(void) +{ +} + +void romstage_cmn_cpu_early_init(void) +{ +} + +void romstage_cmn_pch_init(void) +{ +} + +void romstage_cmn_cpu_init(void) +{ +} + +bool romstage_cmn_is_s3wake(void) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + return pmc_fill_power_state(ps) == ACPI_S3; +} + +void romstage_cmn_soc_mem_init_param(FSP_M_CONFIG *m_cfg) +{ +} + +static const struct romstage_ops s_romstage_ops = { + &romstage_cmn_soc_early_init, + &romstage_cmn_soc_init, + &romstage_cmn_pch_early_init, + &romstage_cmn_pch_init, + &romstage_cmn_cpu_early_init, + &romstage_cmn_cpu_init, + &romstage_cmn_is_s3wake, + &romstage_cmn_mb_mem_init_param, + &romstage_cmn_soc_mem_init_param +}; + +/* + Main romstage function +*/ +asmlinkage void mainboard_romstage_entry(void) +{ + if (CONFIG(VBOOT_EARLY_EC_SYNC)) + vboot_sync_ec(rs_ops->fill_power_state()); + + romstage_early_init(); + romstage_init(); + fsp_memory_init(rs_ops->is_s3wake()); + + if (CONFIG(SMM_TSEG)) + smm_list_regions(); +} + +/* + Callback function for FSP memory initialization +*/ +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + FSP_M_CONFIG *m_cfg; + rs_ops->soc_mem_init_params(m_cfg); + mainboard_memory_init_params(m_cfg); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/37628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c Gerrit-Change-Number: 37628 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: soc/intel/common: Move reset request into intel_fw_update
by Sridhar Siricilla (Code Review) 07 Aug '23

07 Aug '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46819 ) Change subject: soc/intel/common: Move reset request into intel_fw_update ...................................................................... soc/intel/common: Move reset request into intel_fw_update The patch implements below functionalities: 1. Move reset request from CSE FW Update 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update and trigger global reset if one of the FW update requests reset. This patch prevents triggering global reset having separate reset request in UCODE update or CSE Lite FW Update. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004 --- A src/soc/intel/common/basecode/fw_update/fw_update.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 105 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/1 diff --git a/src/soc/intel/common/basecode/fw_update/fw_update.c b/src/soc/intel/common/basecode/fw_update/fw_update.c new file mode 100644 index 0000000..45d2d968 --- /dev/null +++ b/src/soc/intel/common/basecode/fw_update/fw_update.c @@ -0,0 +1,63 @@ +#include <bootstate.h> +#include <console/console.h> +#include <halt.h> +#include <intelbasecode/ucode_update.h> +#include <reset.h> +#include <security/vboot/misc.h> +#include <security/vboot/vboot_common.h> +#include <soc/intel/common/reset.h> +#include <vb2_api.h> +#include <intelblocks/cse.h> + +__weak void cse_board_reset(void) +{ + /* Default weak implementation, does nothing. */ +} + +void trigger_global_reset() { + + cse_board_reset(); + + /* If board does not perform the reset, then perform global_reset */ + do_global_reset(); + + die("cse_lite: Failed to reset the system\n"); +} + +static uint8_t update_ucode(void) +{ + if (CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE)) { + uint8_t reset_req = 0; + if (update_ucode_and_topswap_state(&reset_req)) { + /* Update failed */ + if (CONFIG(VBOOT)) { + printk(BIOS_DEBUG, "ucode: Failed to update microcode\n"); + struct vb2_context *ctx = vboot_get_context(); + if (ctx == NULL) + die("ucode: Failed to trigger recovery mode\n"); + vb2api_fail(ctx, 0x36, 0x0); + vboot_save_data(ctx); + vboot_reboot(); + } + } + return reset_req; + } +} + +static void intel_fw_update(void *unused) +{ + if (update_ucode() || cse_fw_sync()) + trigger_global_reset(); +} + + +#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) + +/* + * This needs to happen after the MRC cache write to avoid a 2nd + * memory training sequence. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, intel_fw_update, NULL); +#else +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, intel_fw_update, NULL); +#endif diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 77a8d5f..6006e13 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -414,43 +414,28 @@ return true; } -__weak void cse_board_reset(void) -{ - /* Default weak implementation, does nothing. */ -} - -/* Set the CSE's next boot partition and issues system reset */ -static bool cse_set_and_boot_from_next_bp(enum boot_partition_id bp) -{ - if (!cse_set_next_boot_partition(bp)) - return false; - - /* Allow the board to perform a reset for CSE RO<->RW jump */ - cse_board_reset(); - - /* If board does not perform the reset, then perform global_reset */ - do_global_reset(); - - die("cse_lite: Failed to reset the system\n"); - - /* Control never reaches here */ - return false; -} - -static bool cse_boot_to_rw(const struct cse_bp_info *cse_bp_info) +static bool cse_set_next_bp_to_rw(const struct cse_bp_info *cse_bp_info, uint8_t *reset_req) { if (cse_get_current_bp(cse_bp_info) == RW) return true; - return cse_set_and_boot_from_next_bp(RW); + if (!cse_set_next_boot_partition(RW)) + return false; + + *reset_req = 1; + return true; } -static bool cse_boot_to_ro(const struct cse_bp_info *cse_bp_info) +static bool cse_set_next_bp_to_ro(const struct cse_bp_info *cse_bp_info, uint8_t *reset_req) { if (cse_get_current_bp(cse_bp_info) == RO) return true; - return cse_set_and_boot_from_next_bp(RO); + if (!cse_set_next_boot_partition(RO)) + return false; + + *reset_req = 1; + return truel } static bool cse_get_rw_rdev(struct region_device *rdev) @@ -701,7 +686,7 @@ * It returns true if RW partition doesn't indicate BP_STATUS_DATA_FAILURE * otherwise false if any operation fails. */ -static bool cse_fix_data_failure_err(const struct cse_bp_info *cse_bp_info) +static bool cse_fix_data_failure_err(const struct cse_bp_info *cse_bp_info, uint8_t *reset_req) { /* * If RW partition status indicates BP_STATUS_DATA_FAILURE, @@ -715,7 +700,7 @@ if (!cse_data_clear_request(cse_bp_info)) return false; - return cse_boot_to_rw(cse_bp_info); + return cse_set_next_bp_to_rw(cse_bp_info, reset_req); } static bool cse_erase_rw_region(const struct region_device *target_rdev) @@ -798,16 +783,19 @@ } static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, - const struct cse_cbfs_rw_info *source_info) + const struct cse_cbfs_rw_info *source_info, uint8_t *reset_req) { /* * To set CSE's operation mode to HMRFPO mode: * 1. Ensure CSE to boot from RO(BP1) * 2. Send HMRFPO_ENABLE command to CSE */ - if (!cse_boot_to_ro(cse_bp_info)) + if (!cse_set_boot_to_ro(cse_bp_info, reset_req)) return false; + if (*reset_req) + return true; + if (cse_is_downgrade_instance(cse_bp_info, source_info) && !cse_data_clear_request(cse_bp_info)) { printk(BIOS_ERR, "cse_lite: CSE FW downgrade is aborted\n"); @@ -818,7 +806,8 @@ } static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, - const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) + const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev, + uint8_t *reset_req) { struct region_device source_rdev; @@ -836,7 +825,7 @@ } } - if (!cse_prep_for_rw_update(cse_bp_info, source_info)) { + if (!cse_prep_for_rw_update(cse_bp_info, source_info, reset_req)) { rv = CSE_LITE_SKU_COMMUNICATION_ERROR; goto error_exit; } @@ -850,7 +839,7 @@ } static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_info_rdev) + const struct region_device *source_info_rdev, uint8_t *reset_req) { struct region_device target_rdev; @@ -869,7 +858,7 @@ if (cse_is_update_required(cse_bp_info, &source_info, &target_rdev)) { printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); - return cse_trigger_fw_update(cse_bp_info, &source_info, &target_rdev); + return cse_trigger_fw_update(cse_bp_info, &source_info, &target_rdev, reset_req); } if (!cse_is_rw_bp_status_valid(cse_bp_info)) @@ -878,19 +867,19 @@ return 0; } -void cse_fw_sync(void *unused) +uint8_t cse_fw_sync(void) { static struct get_bp_info_rsp cse_bp_info; if (vboot_recovery_mode_enabled()) { printk(BIOS_DEBUG, "cse_lite: Skip switching to RW in the recovery path\n"); - return; + return 0; } /* If CSE SKU type is not Lite, skip enabling CSE Lite SKU */ if (!cse_is_hfs3_fw_sku_lite()) { printk(BIOS_ERR, "cse_lite: Not a CSE Lite SKU\n"); - return; + return 0; } if (!cse_get_bp_info(&cse_bp_info)) { @@ -898,9 +887,15 @@ cse_trigger_recovery(CSE_LITE_SKU_COMMUNICATION_ERROR); } - if (!cse_fix_data_failure_err(&cse_bp_info.bp_info)) + uint8_t reset_req = 0; + + if (!cse_fix_data_failure_err(&cse_bp_info.bp_info, &reset_req)) cse_trigger_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR); + if(reset_req) + return reset_req; + + /* * If CSE CBFS RW blob metadata is present in CBFS, then trigger CSE firmware update. * The driver triggers recovery if CSE CBFS RW metadata is present in the CBFS and CSE @@ -909,23 +904,17 @@ uint8_t rv; struct region_device source_info_rdev; if (cse_get_cbfs_rdev(&source_info_rdev)) { - rv = cse_fw_update(&cse_bp_info.bp_info, &source_info_rdev); + rv = cse_fw_update(&cse_bp_info.bp_info, &source_info_rdev, &reset_req); if (rv) cse_trigger_recovery(rv); } - if (!cse_boot_to_rw(&cse_bp_info.bp_info)) { + if(reset_req) + return reset_req; + + if (!cse_set_next_bp_to_rw(&cse_bp_info.bp_info, &reset_req)) { printk(BIOS_ERR, "cse_lite: Failed to switch to RW\n"); cse_trigger_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR); } + return reset_req; } - -#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) -/* - * This needs to happen after the MRC cache write to avoid a 2nd - * memory training sequence. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL); -#else -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); -#endif diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f554933..0ac5d74 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -216,8 +216,9 @@ * boot from RW and triggers recovery mode if CSE fails to jump to RW. * In software triggered recovery mode, the function allows CSE to boot from whatever is * currently selected partition. + * Returns 1 if reset is required otherwise 0. */ -void cse_fw_sync(void *unused); +uint8_t cse_fw_sync(void); /* Perform a board-specific reset sequence for CSE RO<->RW jump */ void cse_board_reset(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/46819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004 Gerrit-Change-Number: 46819 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: [TESTME]lenovo/x220: Attempt to fix broken DRAM init
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39043 ) Change subject: [TESTME]lenovo/x220: Attempt to fix broken DRAM init ...................................................................... [TESTME]lenovo/x220: Attempt to fix broken DRAM init Enable power on WWAN as it has SMBUS connected. Might resolv an issue where DRAM init fails as no EEPROM is found on the bus. Untested. Change-Id: Ia7a2ca370124ecf743b000998b56855d5ed8f573 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/ec/lenovo/h8/Makefile.inc M src/mainboard/lenovo/x220/early_init.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/39043/1 diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index 51c11be..9c8687a 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -18,6 +18,8 @@ ramstage-y += panic.c endif +romstage += wwan.c + ramstage-y += h8.c ramstage-y += bluetooth.c ramstage-y += wwan.c diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 3429c1b..ae16f0c 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -24,6 +24,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <cpu/x86/msr.h> +#include <ec/lenovo/h8/h8.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { @@ -74,6 +75,18 @@ *pei_data = pei_data_template; } +void mainboard_early_init(int s3_resume) +{ + /* + * The WWAN slot has SMBUS connected. Turn on power to make sure + * SMBUS is usable and DRAM init will succeed. + * ramstage will turn it off, in case it's not needed. + * TODO: Does GPIO42 (SMB_3B_EN) help here? + */ + if (h8_has_wwan()) + h8_wwan_enable(true); +} + void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd (&spd[0], 0x50, id_only); -- To view, visit https://review.coreboot.org/c/coreboot/+/39043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a2ca370124ecf743b000998b56855d5ed8f573 Gerrit-Change-Number: 39043 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: amdfwtool: Use *number in config file as NVRAM entry
by Bao Zheng (Code Review) 07 Aug '23

07 Aug '23

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49015 to review the following change. Change subject: amdfwtool: Use *number in config file as NVRAM entry ...................................................................... amdfwtool: Use *number in config file as NVRAM entry Add the entry like XXXX_FW_TYPE_STRING *0xXXXXX to config file. Then the required size of space will be allocated related to the firmware type. Change-Id: I98c94b4087f8a174f7d5753a30695a10f1b796ae Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 6 files changed, 35 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/49015/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index a0f3ec4..08d2817 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -213,7 +213,7 @@ # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_APCB_FILES_BK) \ diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 969f512..f7ef699 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -141,7 +141,7 @@ # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 215a5a1..3d96823 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -110,7 +110,7 @@ # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f167e5e..b6c9c8d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -775,6 +775,13 @@ ctx->current = ALIGN(ctx->current + bytes, BLOB_ALIGNMENT); count++; + } else if (fw_table[i].blank_size != 0) { + pspdir->entries[count].type = fw_table[i].type; + pspdir->entries[count].subprog = fw_table[i].subprog; + pspdir->entries[count].rsvd = 0; + pspdir->entries[count].size = (uint32_t)fw_table[i].blank_size; + pspdir->entries[count].addr = RUN_CURRENT(*ctx); + count++; } else { /* This APU doesn't have this firmware. */ } @@ -1018,11 +1025,15 @@ fw_table[i].type == AMD_BIOS_APCB_BK) ctx->current = ALIGN( ctx->current, ERASE_ALIGNMENT); - bytes = copy_blob(BUFF_CURRENT(*ctx), - fw_table[i].filename, BUFF_ROOM(*ctx)); - if (bytes <= 0) { - free(ctx->rom); - exit(1); + if (fw_table[i].filename != NULL) { + bytes = copy_blob(BUFF_CURRENT(*ctx), + fw_table[i].filename, BUFF_ROOM(*ctx)); + if (bytes <= 0) { + free(ctx->rom); + exit(1); + } + } else if (fw_table[i].blank_size != 0){ + bytes = fw_table[i].blank_size; } biosdir->entries[count].size = (uint32_t)bytes; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 6ae4675..beaa360 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -109,6 +109,7 @@ uint8_t subprog; int level; uint64_t other; + uint32_t blank_size; } amd_fw_entry; typedef struct _amd_cb_config { diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 017c689..de31242 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -254,7 +254,10 @@ while (psp_tableptr->type != AMD_FW_INVALID) { /* instance are not used in PSP table */ if (psp_tableptr->type == fw_type && psp_tableptr->subprog == subprog) { - psp_tableptr->filename = filename; + if (filename[0] == '*') + psp_tableptr->blank_size = strtoull(&filename[1], NULL, 16); + else + psp_tableptr->filename = filename; break; } psp_tableptr++; @@ -330,7 +333,10 @@ if (bhd_tableptr->type == fw_type && bhd_tableptr->subpr == subprog && bhd_tableptr->inst == instance) { - bhd_tableptr->filename = filename; + if (filename[0] == '*') + bhd_tableptr->blank_size = strtoull(&filename[1], NULL, 16); + else + bhd_tableptr->filename = filename; break; } bhd_tableptr++; @@ -440,9 +446,13 @@ continue; } else { path_filename = malloc(MAX_LINE_SIZE); - strcpy(path_filename, dir); - strcat(path_filename, "/"); - strcat(path_filename, &(oneline[match[2].rm_so])); + if (oneline[match[2].rm_so] == '*') { + strcpy(path_filename, &(oneline[match[2].rm_so])); + } else { + strcpy(path_filename, dir); + strcat(path_filename, "/"); + strcat(path_filename, &(oneline[match[2].rm_so])); + } if (find_register_fw_filename_psp_dir( &(oneline[match[1].rm_so]), -- To view, visit https://review.coreboot.org/c/coreboot/+/49015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98c94b4087f8a174f7d5753a30695a10f1b796ae Gerrit-Change-Number: 49015 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

5 53

Change in coreboot[master]: sb/intel/lynxpoint: Setup gpio in bootblock
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36712 ) Change subject: sb/intel/lynxpoint: Setup gpio in bootblock ...................................................................... sb/intel/lynxpoint: Setup gpio in bootblock GPIO setup is needed for verstage. verstage can also still happen after romstage so keep the GPIO init there too. Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/h81m-hds/Makefile.inc M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/slippy/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc M src/mainboard/supermicro/x10slm-f/Makefile.inc M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 10 files changed, 22 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36712/1 diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index de18bc5..3fc7ac7 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -16,4 +16,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 7535350..0ecb31d 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -23,5 +23,7 @@ romstage-y += variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index f80dcab..e35f93e 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -23,6 +23,8 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 91a7963..8f12999 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c smm-y += mainboard_smi.c diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm-f/Makefile.inc index 301070b..0b4f367 100644 --- a/src/mainboard/supermicro/x10slm-f/Makefile.inc +++ b/src/mainboard/supermicro/x10slm-f/Makefile.inc @@ -15,4 +15,5 @@ ## romstage-y += gpio.c +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 5ca7daf..433a310 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d..bacaf74 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -50,6 +50,7 @@ romstage-y += rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +bootblock-y += lp_gpio.c romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 39e6925..abcb35b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -16,6 +16,7 @@ #include <device/pci_ops.h> #include <cpu/intel/car/bootblock.h> #include "pch.h" +#include "lp_gpio.h" /* * Enable Prefetching and Caching. @@ -33,14 +34,6 @@ pci_write_config8(dev, 0xdc, reg8); } - -static void map_rcba(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -} - static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. The chipset does this by default, @@ -72,7 +65,7 @@ void bootblock_early_southbridge_init(void) { - map_rcba(); + pch_enable_bars(); enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); @@ -83,3 +76,12 @@ pch_enable_lpc(); mainboard_config_superio(); } + +void bootblock_southbridge_init(void) +{ +#if CONFIG(INTEL_LYNXPOINT_LP) + setup_pch_lp_gpios(mainboard_gpio_map); +#else + setup_pch_gpios(mainboard_gpio_map); +#endif +} diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index b49d3cf..9cf021e 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -45,7 +45,7 @@ return id == PCH_TYPE_LPT_LP; } -static void pch_enable_bars(void) +void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8802be1..561c5b7 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -184,6 +184,7 @@ int early_pch_init(const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); +void pch_enable_bars(void); #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Gerrit-Change-Number: 36712 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mainboard/lenovo: Add Thinkpad Edge S220 (a.k.a E220s)
by Bill XIE (Code Review) 07 Aug '23

07 Aug '23

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48771 ) Change subject: mainboard/lenovo: Add Thinkpad Edge S220 (a.k.a E220s) ...................................................................... mainboard/lenovo: Add Thinkpad Edge S220 (a.k.a E220s) The code is based on autoport and that for s230u Tested: - CPU i3-2357M - Slotted DIMM 2GiB - Camera - pci-e and usb2 on Mini PCI-E slot for wlan - sata and usb2 on Mini PCI-E slot for wwan - On board SDHCI connected to pci-e - libgfxinit-based graphic init - Sound - S3 - EHCI debug - Seabios Payload Change-Id: I746798b13e83d1971bb7be93751a15875d16c337 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/s220.md A Documentation/mainboard/lenovo/s220_ready_to_flash.jpg M src/mainboard/hp/snb_ivb_laptops/cmos.default A src/mainboard/lenovo/s220/Kconfig A src/mainboard/lenovo/s220/Kconfig.name A src/mainboard/lenovo/s220/Makefile.inc A src/mainboard/lenovo/s220/acpi/ec.asl A src/mainboard/lenovo/s220/acpi/gpe.asl A src/mainboard/lenovo/s220/acpi/platform.asl A src/mainboard/lenovo/s220/acpi/superio.asl A src/mainboard/lenovo/s220/acpi_tables.c A src/mainboard/lenovo/s220/board_info.txt A src/mainboard/lenovo/s220/data.vbt A src/mainboard/lenovo/s220/devicetree.cb A src/mainboard/lenovo/s220/dsdt.asl A src/mainboard/lenovo/s220/early_init.c A src/mainboard/lenovo/s220/ec.c A src/mainboard/lenovo/s220/ec.h A src/mainboard/lenovo/s220/gma-mainboard.ads A src/mainboard/lenovo/s220/gpio.c A src/mainboard/lenovo/s220/hda_verb.c A src/mainboard/lenovo/s220/mainboard.c A src/mainboard/lenovo/s220/smihandler.c 24 files changed, 1,269 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48771/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 95efe55..c0976e0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -103,6 +103,7 @@ - [T420](lenovo/t420.md) - [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md) - [X1](lenovo/x1.md) +- [S220](lenovo/s220.md) ### Ivy Bridge series diff --git a/Documentation/mainboard/lenovo/s220.md b/Documentation/mainboard/lenovo/s220.md new file mode 100644 index 0000000..2bbc22d --- /dev/null +++ b/Documentation/mainboard/lenovo/s220.md @@ -0,0 +1,36 @@ +# Lenovo Edge S220 (a.k.a E220s) + +## Disassembly Instructions + +You must remove the following parts to access the SPI flash: + +![S220 ready to flash](s220_ready_to_flash.jpg) + +* Keyboard +* Hard Drive Cover +* Palmrest + +Its [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/e220s_s220_hmm_en_0a60672… can be used as a guidance of disassembly. + +The vendor IFD VSCC list contains: +- MACRONIX_MX25L6405 (0xc2, 0x2017) +- WINBOND_NEX_W25X64 (0xef, 0x3017) +- ATMEL_AT25DF641 (0x1f, 0x4800) + +The general [flashing tutorial] has more details. + +Tested: +- CPU i3-2357M +- Slotted DIMM 2GiB +- Camera +- pci-e and usb2 on Mini PCI-E slot for wlan +- sata and usb2 on Mini PCI-E slot for wwan +- On board SDHCI connected to pci-e +- libgfxinit-based graphic init +- Sound +- S3 +- EHCI debug +- Seabios Payload + +[flashing tutorial]: ../../flash_tutorial/ext_power.md + diff --git a/Documentation/mainboard/lenovo/s220_ready_to_flash.jpg b/Documentation/mainboard/lenovo/s220_ready_to_flash.jpg new file mode 100644 index 0000000..3fbafce --- /dev/null +++ b/Documentation/mainboard/lenovo/s220_ready_to_flash.jpg Binary files differ diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default index ba33ddf..ad822d5 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.default +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default @@ -2,5 +2,4 @@ debug_level=Debug power_on_after_fail=Disable nmi=Enable -volume=0x3 sata_mode=AHCI diff --git a/src/mainboard/lenovo/s220/Kconfig b/src/mainboard/lenovo/s220/Kconfig new file mode 100644 index 0000000..e909399 --- /dev/null +++ b/src/mainboard/lenovo/s220/Kconfig @@ -0,0 +1,59 @@ +if BOARD_LENOVO_THINKPAD_EDGE_S220 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_C216 + select EC_COMPAL_ENE932 + select EC_ACPI + select NO_UART_ON_SUPERIO + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_PANEL_1_ON_LVDS + select SERIRQ_CONTINUOUS_MODE + select INTEL_GMA_HAVE_VBT + +config MAINBOARD_DIR + string + default lenovo/s220 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad Edge S220/E220s" + +config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + +config VGA_BIOS_ID + string + default "8086,0116" + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config EC_BASE_ADDRESS + hex + default 0xff000000 + +config PS2K_EISAID + default "PTL0001" + +config PS2M_EISAID + default "LEN0031" + +endif diff --git a/src/mainboard/lenovo/s220/Kconfig.name b/src/mainboard/lenovo/s220/Kconfig.name new file mode 100644 index 0000000..78a5af3 --- /dev/null +++ b/src/mainboard/lenovo/s220/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_EDGE_S220 + bool "ThinkPad Edge S220/E220s" diff --git a/src/mainboard/lenovo/s220/Makefile.inc b/src/mainboard/lenovo/s220/Makefile.inc new file mode 100644 index 0000000..a0a3aa1 --- /dev/null +++ b/src/mainboard/lenovo/s220/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += ec.c +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/s220/acpi/ec.asl b/src/mainboard/lenovo/s220/acpi/ec.asl new file mode 100644 index 0000000..20a9096 --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/ec.asl @@ -0,0 +1,347 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, THINKPAD_EC_GPE) + Mutex (ECLK, 0x07) + + /* EmbeddedControl should work as well, but memory mapped is faster. */ + OperationRegion (ERAM, SystemMemory, (CONFIG_EC_BASE_ADDRESS + 0x100), 0x100) + Field (ERAM, ByteAcc, Lock, Preserve) + { + , 1, + , 1, + HKFA, 1, // FN lock (Hotkey / FN row toggle) + , 1, + , 1, + , 1, + , 1, + + Offset(0x0c), + HLCL, 8, // LED control + + Offset(0x46), + , 4, + ONAC, 1, + , 3, + + Offset(0x81), + PAGE, 8, + } + + /* Battery info page 0 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0xA0), + SBRC, 16, /* Remaining capacity */ + SBFC, 16, /* Full-charge capacity */ + SBAE, 16, + SBRS, 16, + SBAC, 16, /* Present rate */ + SBVO, 16, /* Present voltage */ + SBAF, 16, + SBBS, 16, + } + + /* Battery info page 1 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + , 15, + SBCM, 1, /* Power unit (0 == mA/mAh, 1 == mW/mWh) */ + SBMD, 16, + SBCC, 16, + } + + /* Battery info page 2 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBDC, 16, /* Design Capacity */ + SBDV, 16, /* Design Voltage */ + SBOM, 16, + SBSI, 16, + SBDT, 16, + SBSN, 16, /* Serial number */ + } + + /* Battery info page 4 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBCH, 32, /* Type (LiON) */ + } + + /* Battery info page 5 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBMN, 128, /* Manufacturer */ + } + + /* Battery info page 6 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBDN, 128, /* Model */ + } + + Method (_CRS, 0, Serialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + IO (Decode16, 0x700, 0x700, 0, 8) + Memory32Fixed(ReadOnly, CONFIG_EC_BASE_ADDRESS, 0x1000, FF00) + }) + Return (ECMD) + } + + /* Increase brightness hotkey */ + Method (_Q14, 0, NotSerialized) { + BRIGHTNESS_UP() + ^HKEY.MHKQ (0x1010) + } + + /* Decrease brightness hotkey */ + Method (_Q15, 0, NotSerialized) { + BRIGHTNESS_DOWN() + ^HKEY.MHKQ (0x1011) + } + + /* Video output switch hotkey */ + Method (_Q16, 0, NotSerialized) { + Notify (\_SB.PCI0.GFX0, 0x82) + ^HKEY.MHKQ (0x1007) + } + + Method (_Q19, 0, NotSerialized) + { + ^HKEY.MHKQ (0x1018) + } + + /* Switched to AC power */ + Method (_Q26, 0, NotSerialized) + { + Store (One, PWRS) + Notify (^AC, 0x80) + Notify (^BAT0, 0x80) + \PNOT () + ^HKEY.MHKQ (0x6040) + } + + /* Switched to battery power */ + Method (_Q27, 0, NotSerialized) + { + Store (Zero, PWRS) + Notify (^AC, 0x80) + Notify (^BAT0, 0x80) + \PNOT () + ^HKEY.MHKQ (0x6040) + } + + /* Lid openend */ + Method (_Q2A, 0, NotSerialized) + { + Store (One, LIDS) + Notify(^LID, 0x80) + ^HKEY.MHKQ (0x5002) + } + + /* Lid closed */ + Method (_Q2B, 0, NotSerialized) + { + Store (Zero, LIDS) + Notify(^LID, 0x80) + ^HKEY.MHKQ (0x5001) + } + + /* Tablet swivel down */ + Method (_Q35, 0, NotSerialized) + { + ^HKEY.MHKQ (0x60c0) + ^HKEY.MHKQ (0x500a) + } + + /* Tablet swivel up */ + Method (_Q36, 0, NotSerialized) + { + ^HKEY.MHKQ (0x60c0) + ^HKEY.MHKQ (0x5009) + } + + /* Tablet rotate lock button */ + Method (_Q37, 0, NotSerialized) + { + ^HKEY.MHKQ (0x6020) + } + + /* Numlock pressed */ + Method (_Q3F, 0, NotSerialized) + { + ^HKEY.MHKQ (0x6000) + } + + /* RFKill status changed */ + Method (_Q41, 0, NotSerialized) { + ^HKEY.MHKQ (0x7000) + } + + /* Mute hotkey */ + Method (_Q43, 0, NotSerialized) { + ^HKEY.MHKQ (0x1017) + } + + /* Settings hotkey */ + Method (_Q5A, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101D) + } + + /* Search hotkey */ + Method (_Q5B, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101E) + } + + /* Scale hotkey */ + Method (_Q5C, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101F) + } + + /* File hotkey */ + Method (_Q5D, 0, NotSerialized) + { + ^HKEY.MHKQ (0x1020) + } + + /* RFkill hotkey */ + Method (_Q64, 0, NotSerialized) { + ^HKEY.MHKQ (0x1005) + } + + /* Mic mute hotkey */ + Method (_Q6A, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101B) + } + + /* FN key pressed */ + Method (_Q70, 0, NotSerialized) { } + + /* FN+Esc pressed / FN row mode switch */ + Method (_Q74, 0, NotSerialized) { + XOr(One, HKFA, HKFA) + ^HKEY.MHKQ (0x6060) + } + + /* Implements enough of the Lenovo hotkey device for + * thinkpad-acpi to work, no real support for hotkey masking */ + Device (HKEY) + { + Name (_HID, EisaId ("LEN0068")) + + Name (DHKC, Zero) + Name (DHKV, Zero) + Name (DHKN, 0xFC018070) // Hotkey mask + Mutex (XDHK, 0x07) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (MHKV, 0, NotSerialized) + { + Return (0x0100) // Interface version 1.0 + } + + Method (MHKA, 0, NotSerialized) // Hotkey all mask + { + Return (0xFFFFFFFF) + } + + Method (MHKM, 2, NotSerialized) // Set hotkey mask + { + Acquire (XDHK, 0xFFFF) + + ShiftLeft (One, Decrement (Arg0), Local0) + If (Arg1) { + Or (Local0, DHKN, DHKN) + } Else { + And (Not(Local0), DHKN, DHKN) + } + + Release (XDHK) + } + + Method (MHKC, 1, NotSerialized) // Hotkey disable? + { + Acquire (XDHK, 0xFFFF) + + Store (Arg0, DHKC) + + Release (XDHK) + } + + Method (MHKP, 0, NotSerialized) // Hotkey poll + { + Acquire (XDHK, 0xFFFF) + + Store (Zero, Local0) + + if (DHKV) { + Store (DHKV, Local0) + Store (Zero, DHKV) + } + + Release (XDHK) + + Return (Local0) + } + + Method (MHKQ, 1, NotSerialized) // Send hotkey event + { + Acquire (XDHK, 0xFFFF) + + Store (Arg0, DHKV) + + Release (XDHK) + + Notify (HKEY, 0x80) // Status Change + } + } + + /* LED support for thinkpad-acpi */ + Method (LED, 2, NotSerialized) + { + Or (Arg0, Arg1, HLCL) + } + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package (1) { \_SB }) + + Method (_PSR, 0, NotSerialized) + { + Return (ONAC) + } + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + /* Battery is H8 compatible, but requires an explicit delay */ + #define BATTERY_PAGE_DELAY_MS 20 + #include <ec/lenovo/h8/acpi/battery.asl> + + /* LID is H8 compatible */ + #include <ec/lenovo/h8/acpi/lid.asl> +} diff --git a/src/mainboard/lenovo/s220/acpi/gpe.asl b/src/mainboard/lenovo/s220/acpi/gpe.asl new file mode 100644 index 0000000..8124ec7 --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/gpe.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_GPE) +{ + Name (PDET, Zero) + Method (PNOT, 2, Serialized) { + ShiftLeft (Arg0, Arg1, Local0) + Not( ShiftLeft (One, Arg1), Local1) + Or (Local0, And (Local1, PDET), PDET) + If (LEqual (PDET, Zero)) { + // Palm removed + \_SB.PCI0.LPCB.EC0.HKEY.MHKQ (0x60B1) + } Else { + // Palm detected + \_SB.PCI0.LPCB.EC0.HKEY.MHKQ (0x60B0) + } + } + + Method (TINV, 2, Serialized) { + ShiftLeft (One, Arg1, Local0) + If (LEqual (Arg0, Zero)) { + Not (Local0, Local0) + And (GIV0, Local0, GIV0) + } Else { + Or (GIV0, Local0, GIV0) + } + } + + /* Palm detect sensor 1 */ + Method (_L12, 0, NotSerialized) { + // Invert trigger + TINV (GP02, 2) + + PNOT (GP02, 0) + } + + /* Palm detect sensor 2 */ + Method (_L14, 0, NotSerialized) { + // Invert trigger + TINV (GP04, 4) + + PNOT (GP04, 1) + } +} diff --git a/src/mainboard/lenovo/s220/acpi/platform.asl b/src/mainboard/lenovo/s220/acpi/platform.asl new file mode 100644 index 0000000..149fb3a --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/platform.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + /* Turn on radios */ + Store (One, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + Store (One, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + /* There also is RF_OFF# on pin 20, controlled by the EC */ + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* Turn off radios */ + Store (Zero, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + Store (Zero, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + /* There also is RF_OFF# on pin 20, controlled by the EC */ +} + +Scope(\_SI) +{ + Method(_SST, 1, NotSerialized) + { + If (LLess(Arg0, 2)) + { + /* Thinkpad LED on */ + \_SB.PCI0.LPCB.EC0.LED (Zero, 0x80) + } + Else + { + /* Thinkpad LED blinking */ + \_SB.PCI0.LPCB.EC0.LED (Zero, 0xC0) + } + } +} diff --git a/src/mainboard/lenovo/s220/acpi/superio.asl b/src/mainboard/lenovo/s220/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/s220/acpi_tables.c b/src/mainboard/lenovo/s220/acpi_tables.c new file mode 100644 index 0000000..c85058d --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi_tables.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/s220/board_info.txt b/src/mainboard/lenovo/s220/board_info.txt new file mode 100644 index 0000000..cdbf8b8 --- /dev/null +++ b/src/mainboard/lenovo/s220/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year diff --git a/src/mainboard/lenovo/s220/data.vbt b/src/mainboard/lenovo/s220/data.vbt new file mode 100644 index 0000000..f7882f9 --- /dev/null +++ b/src/mainboard/lenovo/s220/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/s220/devicetree.cb b/src/mainboard/lenovo/s220/devicetree.cb new file mode 100644 index 0000000..22429c9 --- /dev/null +++ b/src/mainboard/lenovo/s220/devicetree.cb @@ -0,0 +1,84 @@ +chip northbridge/intel/sandybridge + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_cpu_backlight" = "0x00000f55" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" + register "gpu_panel_power_backlight_off_delay" = "2700" + register "gpu_panel_power_backlight_on_delay" = "3800" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "95" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x17aa 0x21e4 inherit + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00000000" + register "gen2_dec" = "0x000c0701" + register "gen3_dec" = "0x000c0069" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi7_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x19" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x21e4 + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/s220/dsdt.asl b/src/mainboard/lenovo/s220/dsdt.asl new file mode 100644 index 0000000..6d67b91 --- /dev/null +++ b/src/mainboard/lenovo/s220/dsdt.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 23 + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/gpe.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/s220/early_init.c b/src/mainboard/lenovo/s220/early_init.c new file mode 100644 index 0000000..e04b4df --- /dev/null +++ b/src/mainboard/lenovo/s220/early_init.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include "ec.h" + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 0, 1, 1 }, + { 0, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 0, 0, 5 }, + { 0, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + /* Memory map KB9012 EC registers */ + pci_write_config32(PCH_LPC_DEV, LGMR, + CONFIG_EC_BASE_ADDRESS | 1); + pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); + + /* Enable external USB port power. */ + if (CONFIG(USBDEBUG)) + ec_mm_set_bit(0x3b, 4); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/lenovo/s220/ec.c b/src/mainboard/lenovo/s220/ec.c new file mode 100644 index 0000000..285a8d5 --- /dev/null +++ b/src/mainboard/lenovo/s220/ec.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ec.h" +#include <ec/compal/ene932/ec.h> + +/* The keyboard matrix tells the EC how the keyboard is wired internally */ +static void set_keyboard_matrix_us(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE5); +} + +/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */ +static void enter_apm_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE9); +} + +void lenovo_s230u_ec_init(void) +{ + set_keyboard_matrix_us(); + + /* + * The EC has a special "blinking Caps Lock LED" mode which it normally + * enters when it believes the OS is not responding. It occasionally + * disables battery charging when in this mode, although other + * functionality is unaffected. Although the EC starts in APM mode by + * default, it only leaves the "blinking Caps Lock LED" mode after + * receiving the following command. + */ + enter_apm_mode(); + + /* Enable external USB port power. */ + ec_mm_set_bit(0x3b, 4); +} diff --git a/src/mainboard/lenovo/s220/ec.h b/src/mainboard/lenovo/s220/ec.h new file mode 100644 index 0000000..273f58b --- /dev/null +++ b/src/mainboard/lenovo/s220/ec.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _MAINBOARD_LENOVO_S230U_EC_H +#define _MAINBOARD_LENOVO_S230U_EC_H + +void lenovo_s230u_ec_init(void); + +#define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x))) +#define ec_mm_read(addr) (ECMM(0x100 + addr)) +#define ec_mm_write(addr, data) (ECMM(0x100 + addr) = data) +#define ec_mm_set_bit(addr, bit) (ECMM(0x100 + addr) |= 1 << bit) +#define ec_mm_clr_bit(addr, bit) (ECMM(0x100 + addr) &= ~(1 << bit)) + +#endif /* _MAINBOARD_LENOVO_S230U_EC_H */ diff --git a/src/mainboard/lenovo/s220/gma-mainboard.ads b/src/mainboard/lenovo/s220/gma-mainboard.ads new file mode 100644 index 0000000..03e6a55 --- /dev/null +++ b/src/mainboard/lenovo/s220/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/s220/gpio.c b/src/mainboard/lenovo/s220/gpio.c new file mode 100644 index 0000000..ea8a906 --- /dev/null +++ b/src/mainboard/lenovo/s220/gpio.c @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/s220/hda_verb.c b/src/mainboard/lenovo/s220/hda_verb.c new file mode 100644 index 0000000..0bb7e02 --- /dev/null +++ b/src/mainboard/lenovo/s220/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec Vendor / Device ID: Conexant */ + 0x17aa21e4, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21e4), + AZALIA_PIN_CFG(0, 0x19, 0x04211040), + AZALIA_PIN_CFG(0, 0x1a, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1b, 0x04a11060), + AZALIA_PIN_CFG(0, 0x1c, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1f, 0x90170110), + AZALIA_PIN_CFG(0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x23, 0x90a60170), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x17aa21e4, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x17aa21e4), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/s220/mainboard.c b/src/mainboard/lenovo/s220/mainboard.c new file mode 100644 index 0000000..7f2c7fd --- /dev/null +++ b/src/mainboard/lenovo/s220/mainboard.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <southbridge/intel/common/gpio.h> +#include <string.h> +#include <smbios.h> +#include "ec.h" + +#include <acpi/acpi.h> + +static u8 mainboard_fill_ec_version(char *buf, u8 buf_len) +{ + u8 i, c; + char str[16 + 1]; /* 16 ASCII chars + \0 */ + + /* Build ID */ + for (i = 0; i < 8; i++) { + c = ec_mm_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) { + i = snprintf(str, sizeof(str), "*INVALID"); + break; + } + str[i] = c; + } + + i = MIN(buf_len, i); + memcpy(buf, str, i); + + return i; +} + +static void mainboard_smbios_strings( + struct device *dev, struct smbios_type11 *t) +{ + char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; + u16 fwvh, fwvl; + + mainboard_fill_ec_version(tpec + 35, 17); + t->count = smbios_add_string(t->eos, tpec); + + /* Apparently byteswapped compared to H8 */ + fwvh = ec_mm_read(0xe8); + fwvl = ec_mm_read(0xe9); + + printk(BIOS_INFO, "EC Firmware ID %.54s, Version %d.%d%d%c\n", tpec, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = mainboard_smbios_strings, + + install_intel_vga_int15_handler( + GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); + + if (!acpi_is_wakeup_s3()) + lenovo_s230u_ec_init(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/s220/smihandler.c b/src/mainboard/lenovo/s220/smihandler.c new file mode 100644 index 0000000..62bba44 --- /dev/null +++ b/src/mainboard/lenovo/s220/smihandler.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/compal/ene932/ec.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmutil.h> + +#include "ec.h" + +#define GPE_PALMDET1 2 +#define GPE_PALMDET2 4 +#define GPE_EC_SCI 7 +#define GPE_EC_SMI 8 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +enum sleep_states { + S0 = 0, + S1 = 1, + S3 = 3, + S4 = 4, + S5 = 5, +}; + +enum ec_smi_event { + EC_SMI_EVENT_IDLE = 0x80, + EC_SMI_BATTERY_LOW = 0xb3, +}; + +/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs. */ +static void ec_enter_apm_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE9); +} +/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs. */ +static void ec_enter_acpi_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE8); +} + +static uint8_t ec_get_smi_event(void) +{ + ec_kbc_write_cmd(0x56); + return ec_kbc_read_ob(); +} + +static void ec_process_smi(uint8_t src) +{ + /* + * Reading the SMI source satisfies the EC in terms of responding to + * the event, regardless of whether we take an action or not. + */ + + printk(BIOS_DEBUG, "Unhandled EC_SMI event 0x%x\n", src); +} + +static void handle_ec_smi(void) +{ + uint8_t src; + + while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE) + ec_process_smi(src); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SMI)) + handle_ec_smi(); +} + +int mainboard_smi_apmc(u8 data) +{ + printk(BIOS_INFO, "mainboard_smi_apmc(%02x)\n", data); + + switch (data) { + case APM_CNT_ACPI_ENABLE: + printk(BIOS_DEBUG, "Enable ACPI mode\n"); + ec_enter_acpi_mode(); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + gpi_route_interrupt(GPE_PALMDET1, GPI_IS_SCI); + gpi_route_interrupt(GPE_PALMDET2, GPI_IS_SCI); + break; + case APM_CNT_ACPI_DISABLE: + printk(BIOS_DEBUG, "Disable ACPI mode\n"); + ec_enter_apm_mode(); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + break; + default: + printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data); + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == S3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I746798b13e83d1971bb7be93751a15875d16c337 Gerrit-Change-Number: 48771 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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coreboot-gerrit August 2021