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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57071 )
Change subject: mb/google/brya/var/brya0: Align comments in overridetree
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Thank you.
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Change subject: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/emulation/qemu-power9/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126503):
https://review.coreboot.org/c/coreboot/+/57079/comment/51f1853f_ab017b8e
PS1, Line 10: if (!dev) {
braces {} are not necessary for single statement blocks
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Change subject: src/cpu/power9/*: Add file structure for power9, implement SCOM access
......................................................................
Patch Set 1:
(22 comments)
File src/arch/ppc64/include/arch/byteorder.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/76ca4c5a_cdff1784
PS1, Line 9: #define PPC_BITMASK(bs,be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
space required after that ',' (ctx:VxV)
File src/cpu/power9/scom.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/06fd1acd_71701bda
PS1, Line 9: #define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35)
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/e518c09d_95c448bf
PS1, Line 10: #define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63)
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/b959b745_ed1e420f
PS1, Line 11: #define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12,63)
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/2a7ef02d_077b2480
PS1, Line 30: if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) {
space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/54be4cdf_b34fddd4
PS1, Line 33: else if(data & XSCOM_DATA_IND_COMPLETE) {
space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/4365d06b_6da95a6b
PS1, Line 33: else if(data & XSCOM_DATA_IND_COMPLETE) {
else should follow close brace '}'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/2fd03ef8_333ce4b4
PS1, Line 52: if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) {
space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/55ee24c8_86bacf01
PS1, Line 55: else if(data & XSCOM_DATA_IND_COMPLETE) {
space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/a993cd8b_77fb2d83
PS1, Line 55: else if(data & XSCOM_DATA_IND_COMPLETE) {
else should follow close brace '}'
File src/include/cpu/power/scom.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/00b80450_87025d6d
PS1, Line 8: // 8 7 6 5 4 3 2 1
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/f5f63c7e_55a0291d
PS1, Line 10: // |0 1 2 3| |4 5 6 7| |8 9 10 11| |12 13 14 15| |16 17 18 19| |20 21 22 23| |24 25 26 27| |28 29 30 31|
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/8d14abbe_5b7e17ed
PS1, Line 11: // {A}{ B } { C } { D }{ E }{ F }
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/06222f7c_5e9a1104
PS1, Line 30: #define XSCOM_ADDR_IND_ADDR PPC_BITMASK(11,31)
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/ff6f6a1b_9a6e35b2
PS1, Line 31: #define XSCOM_ADDR_IND_DATA PPC_BITMASK(48,63)
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/a320a0da_0c40ecb1
PS1, Line 40: {
open brace '{' following enum go on the same line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/495168a0_2d8c4106
PS1, Line 107: "ldcix %0, %1, %2":
spaces required around that ':' (ctx:VxE)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/01488a74_e2e6e96c
PS1, Line 108: "=r"(val):
spaces required around that ':' (ctx:VxE)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/982fd92e_aeccc0d8
PS1, Line 186: addr &= ~PPC_BITMASK(34,39);
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/f58b851c_d8393da3
PS1, Line 193: addr &= ~PPC_BITMASK(34,39);
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/10670a67_c92e4061
PS1, Line 198: static inline void scom_and_or_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t and, uint64_t or)
line over 96 characters
File src/include/cpu/power/spr.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126502):
https://review.coreboot.org/c/coreboot/+/57078/comment/20deddb6_3989638d
PS1, Line 29: #define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23)
space required after that ',' (ctx:VxV)
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Change subject: ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment
......................................................................
Patch Set 1:
(1 comment)
File src/arch/ppc64/bootblock_crt0.S:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126500):
https://review.coreboot.org/c/coreboot/+/57076/comment/3186bd46_0b2e5521
PS1, Line 46: /* Curently not needed, .bss is zeroed in the file. If it were to be
'Curently' may be misspelled - perhaps 'Currently'?
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Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56438 )
Change subject: [WIP]amdfwtool: Use relative address for EFS gen2
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56438/comment/512b4732_73361e05
PS2, Line 9: The second generation EFS (offset 0x24[0]=0) uses
: "binary relative" offsets and not "x86 physical
: MMIO address" like gen1.
:
: Chips like Cezanne can run in both cases, so no problem
: comes up so far.
:
: TODO: Need to fix the problem in psp_verstage.
> if this breaks psp_verstage, why are you putting it up for review?
Cause it is going to be merged after the psp_verstage doesnt break.
Kangheui Won is doing this now.
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