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Change subject: thread: Add thread_handle
......................................................................
Patch Set 4:
(1 comment)
File src/include/thread.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123992):
https://review.coreboot.org/c/coreboot/+/56229/comment/9752eda8_b44eeeed
PS4, Line 29: enum cb_err (*entry)(void *);
function definition argument 'void *' should also have an identifier name
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Hello build bot (Jenkins), Julius Werner, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: thread: Add thread_handle
......................................................................
thread: Add thread_handle
The thread_handle can be used to wait for a thread to exit. I also added
a return value to the thread function that will be stored on the handle
after it completes. This makes it easy for the callers to check if the
thread completed successfully or had an error. The wait_for_thread
method uses the handle to block until the thread completes.
BUG=b:179699789
TEST=See thread_handle state update and see error code set correctly.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff
---
M src/include/thread.h
M src/lib/thread.c
2 files changed, 87 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/56229/4
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Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
......................................................................
soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.
There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.
BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/common/block/lpc/spi_dma.c
2 files changed, 171 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56228/4
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Change subject: soc/amd/cezanne: Move APOB update into ramstage
......................................................................
soc/amd/cezanne: Move APOB update into ramstage
There is no technical reason this needs to be done in romstage. Moving
it into ramstage allow us (in future CLs) to use threads to pre-load
the apob from SPI.
BUG=b:179699789
TEST=Boot and Ezkinil and Guybrush and verify APOB update still work
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e
---
M src/soc/amd/cezanne/romstage.c
M src/soc/amd/common/block/apob/Makefile.inc
M src/soc/amd/common/block/apob/apob_cache.c
M src/soc/amd/common/block/include/amdblocks/apob_cache.h
M src/soc/amd/picasso/romstage.c
5 files changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/56227/4
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Change subject: thread: Add missing static inline
......................................................................
thread: Add missing static inline
BUG=b:179699789
TEST=Able to compile with the rest of the patch train.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I9e3cfb55e48737c378bde53ae0e5d7cbf5e41bc3
---
M src/include/thread.h
1 file changed, 5 insertions(+), 0 deletions(-)
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Change subject: soc/amd/cezanne: Start loading APOB asynchronously
......................................................................
soc/amd/cezanne: Start loading APOB asynchronously
This enables COOP_MULTITASKING (i.e., multiple stacks single CPU). This
will allow the APOB to start loading while ramstage progresses
through the state machine.
BUG=b:179699789
TEST=Boot guybrush and verify APOB read timestamp has dropped from 10ms
to a few uS.
Starting APOB preload
APOB thread running
spi_dma_readat_dma: start: dest: 0xcb7aa640, offset: 0x0, size: 65536
took 0 us to acquire mutex
start_spi_dma_transaction: dest: 0xcb7aa640, offset: 0x0, remaining: 65536
<ramstage doing work>
spi_dma_readat_dma: end: dest: 0xcb7aa640, offset: 0x0, size: 65536, remaining: 0
<more work..>
waiting for thread
took 0 us
APOB valid copy is already in flash
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1bea
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/fsp_s_params.c
2 files changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/56234/4
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Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB_NV
......................................................................
soc/amd/common/apob: Add support for asynchronously reading APOB_NV
This CL adds a method that can start the processes of reading the APOB
from SPI. It does require more RAM in ramstage since we no longer mmap
the buffer in the happy path. This will allow us to reduce our
boot time by ~10ms. The SoC code will need to be updated to call
start_apob_cache_read at a point where it makes sense.
BUG=b:179699789
TEST=With this and the patches above I can see a 10 ms reduction in
boot time on guybrush.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5
---
M src/soc/amd/common/block/apob/apob_cache.c
M src/soc/amd/common/block/include/amdblocks/apob_cache.h
2 files changed, 65 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/56232/4
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Change subject: thread: Add missing static inline
......................................................................
thread: Add missing static inline
BUG=b:179699789
TEST=Able to compile with the rest of the patch train.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I9e3cfb55e48737c378bde53ae0e5d7cbf5e41bc3
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Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56232 )
Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56232/comment/7171ee6a_584027a3
PS3, Line 7: APOB
APOB_NV please
https://review.coreboot.org/c/coreboot/+/56232/comment/586c44e0_ac9ae3f4
PS3, Line 11: happy path
😄
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