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Change subject: sc7280: Add PCIe RC driver in Coreboot
......................................................................
sc7280: Add PCIe RC driver in Coreboot
In coreboot ram stage, PCIe root complex driver initialize
the PCIe core, QMP PHY and does the bus enumeration.
Upon successful detection of EP(NVMe), PCIe RC driver
allocates the resources and set the configuration parameters.
Below are the changes added.
(a) PCIe Core reset, init, link training.
(b) Bus enumeration and resource allocation
(c) QMP PHY 3x2 initialization
To enable NVMe LDO's, need to set gpio19 pin in SKU1
and gpio51 in SKU2.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631
Signed-off-by: Prasad Malisetty <pmaliset(a)codeaurora.org>
---
M src/mainboard/google/herobrine/mainboard.c
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/include/soc/addressmap.h
A src/soc/qualcomm/sc7280/include/soc/pcie.h
A src/soc/qualcomm/sc7280/include/soc/qcom_qmp_phy.h
A src/soc/qualcomm/sc7280/pcie_host.c
6 files changed, 1,718 insertions(+), 3 deletions(-)
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Change subject: herobrine: sc7280: Load GSI FW in ramstage
......................................................................
herobrine: sc7280: Load GSI FW in ramstage
Load GSI FW in ramstage and make it part of RW
As part of the code clean up, update the header files of the
QUP drivers with the correct path.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org>
Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30
---
M src/mainboard/google/herobrine/bootblock.c
M src/mainboard/google/herobrine/mainboard.c
2 files changed, 22 insertions(+), 0 deletions(-)
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Change subject: sc7180: Refactor QUP driver
......................................................................
sc7180: Refactor QUP driver
Refactor QUP driver by separating
common and SoC specific driver code.
Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org>
Change-Id: I18581af0e209c409edf7b6613757e651dbe32eee
---
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M src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h
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Change subject: sc7180: Refactor QSPI driver
......................................................................
sc7180: Refactor QSPI driver
Refactor Qcom QSPI driver by seperating
common and SoC specific driver code.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org>
Change-Id: I840279de264f7c740e439a64fe64ee0cf556dc01
---
M src/soc/qualcomm/sc7180/bootblock.c
M src/soc/qualcomm/sc7180/include/soc/addressmap.h
D src/soc/qualcomm/sc7180/include/soc/qspi.h
D src/soc/qualcomm/sc7180/spi.c
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Change subject: soc/qualcomm/common/qspi: Add support for common QSPI driver
......................................................................
soc/qualcomm/common/qspi: Add support for common QSPI driver
Add common QSPI functionalities for qualcomm SoC targets.
This common QSPI driver works in master mode and provides read/write
operation for the slave devices like flash.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board
Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org>
Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9
---
A src/soc/qualcomm/common/include/soc/qspi_common.h
A src/soc/qualcomm/common/qspi.c
A src/soc/qualcomm/common/spi.c
3 files changed, 440 insertions(+), 0 deletions(-)
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Change subject: mainboard/google/herobrine: Configure SDCC clock
......................................................................
mainboard/google/herobrine: Configure SDCC clock
Configure 384MHz for eMMC clock and 50MHz for SD card clock.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I8acbce58614add0228adc39289762da10937cbe2
Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org>
---
M src/mainboard/google/herobrine/mainboard.c
1 file changed, 10 insertions(+), 1 deletion(-)
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Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme
......................................................................
qualcomm/sc7280: gpio: Support eGPIO scheme
eGPIO is a scheme which allows special power island domain IOs to be
reused as regular chip GPIOs by muxing regular TLMM functions with
Island Domain functions. With this scheme, an IO can be controlled
both by APPS and Island processor.
egpio_configure_pins() API to configure the eGPIO's for a given range
specified from start to end.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board by configuring the
the existing supported GPIO's to function as eGPIO's
Signed-off-by: Taniya Das <tdas(a)codeaurora.org>
Change-Id: I2c54a14c50fb7b5921d1961d2de83098ed2d4358
---
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/include/soc/gpio.h
A src/soc/qualcomm/sc7280/sc7280_egpio.c
3 files changed, 39 insertions(+), 0 deletions(-)
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55950 )
Change subject: herobrine: get boardid from GPIO configuration
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/herobrine/boardid.c:
https://review.coreboot.org/c/coreboot/+/55950/comment/1a08116a_fb3f4bfb
PS5, Line 25: CB_ERR
> hi shelly, […]
Yes, you are correct actually. But, I just realized that if we don't match one of the boards, it is actually not an error, but we just don't recognize it. So, I believe that the correct action is to return the retrieved boardid anyway and perhaps print out that it was not recognized.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 )
Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
......................................................................
Patch Set 3:
(1 comment)
File src/drivers/intel/fsp2_0/util.c:
https://review.coreboot.org/c/coreboot/+/56190/comment/9f43e928_f4179511
PS3, Line 14: looks_like_fsp_header
> can we change this code like below? […]
Why? I think this needs to be fixed in EDK2. If there is a reason why EDK2 must not be updated to match the spec, then this check in coreboot can be completely dropped as the version<->length consistency is not being followed. But, I would like to understand why EDK2 is not being updated.
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