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Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD
......................................................................
soc/amd/cezanne: add ACPI CPPC support for AMD
This leverages the existing Collaborative Processor Performance Control
(CPPC) support and adds CPPC init for AMD/Cezanne.
Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com>
Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb
---
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/cezanne/acpi.c
A src/soc/amd/cezanne/cppc.c
A src/soc/amd/cezanne/include/soc/cppc.h
M src/soc/amd/cezanne/include/soc/msr.h
5 files changed, 216 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56188/5
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Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
......................................................................
mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is
enableda on the system.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon
if not updated.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I2a1f60fda7575212bb694fc423bd229452515903
---
M src/mainboard/intel/adlrvp/bootblock.c
1 file changed, 85 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56073/5
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Change subject: drivers/intel/gma: Support IGD Opregion 2.1
......................................................................
Patch Set 24:
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/52758/comment/72fdc02d_4e2a9f72
PS14, Line 290: CONFIG(INTEL_GMA_OPREGION_2_1)
> May be worth a helper function? […]
Woops. Sorry, had missed this comment. Yes, my original suggestion wouldn't work for Opregion 3.0 { .major = 3, .minor = 0 }.
Either !CONFIG(INTEL_GMA_OPREGION_2_0) or Tim's helper function suggestion looks fine. I am slightly inclined towards the latter (i.e. actual version check using `header->opver`) because we don't have to worry about Kconfig changing and having to re-evaluate the file to see how it impacts the code.
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Change subject: tests: Add lib/libgcc-test test case
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/brya: Program Unused Cnvi BT related GPIOs to NC
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/55317/comment/983b3bea_9f393677
PS6, Line 368: Put unused Cnvi BT UART lines in NC mode since we use USB mode
> Yes Furquan...default state of these vGPIO lines are set to NF1.
Interesting. Do we need to configure all other vGPIOs as NC as well? What is the impact of leaving these at NF1? Power hit? S0ix failures? Functionality issues?
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Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
......................................................................
Patch Set 3:
(1 comment)
File src/drivers/intel/fsp2_0/util.c:
https://review.coreboot.org/c/coreboot/+/56190/comment/e9d43806_501c132e
PS3, Line 14: looks_like_fsp_header
> We don't really need any change in coreboot. […]
I have initiated an internal email thread to understand why we didn't updated the EDK2 version since we have introduced the FSP2.1 and its still pointing to FSP2.0
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Change subject: soc/amd/picasso: check length of mca_bank_name array
......................................................................
Patch Set 1: Code-Review+2
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