coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/picasso: add missing banks to mca_bank_name array
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56273 ) Change subject: soc/amd/picasso: add missing banks to mca_bank_name array ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb Gerrit-Change-Number: 56273 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 19:18:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Furquan Shaikh (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Martin Roth, Michał Żygowski, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/b7c7f22c_b9d9daff PS3, Line 14: looks_like_fsp_header > i agree that ideally this might need EDK2 fix but suggesting this instead of https://review. […] We don't really need any change in coreboot. As a workaround, I think AMD FSP package needs to override the PCD for header version and you/Nate will have to follow up to get EDK2 fixed to set the header version field correctly. -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 19:17:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: check length of mca_bank_name array
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56274 ) Change subject: soc/amd/picasso: check length of mca_bank_name array ...................................................................... soc/amd/picasso: check length of mca_bank_name array The length of mca_bank_name should match the return value of mca_get_bank_count which gets the number of MCA banks from an MSR. TEST=No error message on serial console on amd/mandolin Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/56274/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 69864a5..2b1e1b2 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -184,6 +184,9 @@ struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); + if (ARRAY_SIZE(mca_bank_name) != num_banks) + printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); + for (unsigned int i = 0 ; i < num_banks ; i++) { mci.bank = i; mci.sts = rdmsr(MCAX_STATUS_MSR(i)); -- To view, visit https://review.coreboot.org/c/coreboot/+/56274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342 Gerrit-Change-Number: 56274 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: add missing banks to mca_bank_name array
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56273 ) Change subject: soc/amd/picasso: add missing banks to mca_bank_name array ...................................................................... soc/amd/picasso: add missing banks to mca_bank_name array Also use array indices for the initialization. TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16 Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c 1 file changed, 23 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56273/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 23d7b61..69864a5 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -135,14 +135,29 @@ } static const char *const mca_bank_name[] = { - "Load-store unit", - "Instruction fetch unit", - "L2 cache unit", - "Decode unit", - "", - "Execution unit", - "Floating point unit", - "L3 cache unit" + [ 0] = "Load-store unit", + [ 1] = "Instruction fetch unit", + [ 2] = "L2 cache unit", + [ 3] = "Decode unit", + [ 4] = "", + [ 5] = "Execution unit", + [ 6] = "Floating point unit", + [ 7] = "L3 cache unit", + [ 8] = "L3 cache unit", + [ 9] = "L3 cache unit", + [10] = "L3 cache unit", + [11] = "L3 cache unit", + [12] = "L3 cache unit", + [13] = "L3 cache unit", + [14] = "L3 cache unit", + [15] = "UMC", + [16] = "UMC", + [17] = "SMU", + [18] = "PSP", + [19] = "PB", + [20] = "CS", + [21] = "CS", + [22] = "PIE", }; static void mca_print_error(unsigned int bank) -- To view, visit https://review.coreboot.org/c/coreboot/+/56273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb Gerrit-Change-Number: 56273 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: use index for mca_bank_name initialization
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56272 ) Change subject: soc/amd/stoneyridge: use index for mca_bank_name initialization ...................................................................... soc/amd/stoneyridge: use index for mca_bank_name initialization Change-Id: Id640fd8006c47ce1db8a8729407c1c9a9c1e79c3 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/mca.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/56272/1 diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index d444003..50e7fdd 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -136,13 +136,13 @@ } static const char *const mca_bank_name[] = { - "Load-store unit", - "Instruction fetch unit", - "Combined unit", - "Reserved", - "Northbridge", - "Execution unit", - "Floating point unit" + [0] = "Load-store unit", + [1] = "Instruction fetch unit", + [2] = "Combined unit", + [3] = "Reserved", + [4] = "Northbridge", + [5] = "Execution unit", + [6] = "Floating point unit" }; static void mca_print_error(unsigned int bank) -- To view, visit https://review.coreboot.org/c/coreboot/+/56272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id640fd8006c47ce1db8a8729407c1c9a9c1e79c3 Gerrit-Change-Number: 56272 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge/mca: add missing types.h include
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56271 ) Change subject: soc/amd/stoneyridge/mca: add missing types.h include ...................................................................... soc/amd/stoneyridge/mca: add missing types.h include Change-Id: Ifbcad4d81fb9f6c359a870be73b05ed86441e7f0 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/mca.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/56271/1 diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index d9aac91..d444003 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -9,6 +9,7 @@ #include <console/console.h> #include <arch/bert_storage.h> #include <cper.h> +#include <types.h> struct mca_bank_status { unsigned int bank; -- To view, visit https://review.coreboot.org/c/coreboot/+/56271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcad4d81fb9f6c359a870be73b05ed86441e7f0 Gerrit-Change-Number: 56271 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56228 ) Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality ...................................................................... Patch Set 4: (3 comments) File src/soc/amd/common/block/include/amdblocks/lpc.h: https://review.coreboot.org/c/coreboot/+/56228/comment/40650366_25a58a5a PS3, Line 121: LPC_ROM_DMA_EC_HOST_CONTROL 0xb8 > PPR 55570 has this register definition. […] I mostly used the stoney BKDG, but the registers I used were apart of the picasso PPR. I had Felix verify the registers on Cezanne and they were present. File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/56228/comment/56be0795_d3b62520 PS3, Line 103: ctrl |= LPC_ROM_DMA_CTRL_ERROR; /* Clear error */ I was using the stoney BKDG since it provides more details: > DmaErrorStatus. Read; Write-1-to-clear. Reset: 0. 1=Previous transfer has error. 0=Previous transfer has completed successfully. I've never actually encountered an error so I haven't validated the behavior. I would prefer to set it since it won't cause any problems if it is read only, but it will clear the error if it isn't. Thoughts? https://review.coreboot.org/c/coreboot/+/56228/comment/4c8ed17a_1ab752aa PS3, Line 209: val |= BIT(6); > Is this the magic bit that needs to be set? A macro for that bit? What does this bit do to make the […] Yeah this is the magic bit: b/179699789#comment11 has the explanation. I didn't add a macro since it's an internal only register. I also didn't link the bug here since this is public code. -- To view, visit https://review.coreboot.org/c/coreboot/+/56228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Gerrit-Change-Number: 56228 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 19:15:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add dependencies as part common QSPI cleanup code changes
by Ravi kumar (Code Review) 13 Jul '21

13 Jul '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56270 ) Change subject: sc7180: Add dependencies as part common QSPI cleanup code changes ...................................................................... sc7180: Add dependencies as part common QSPI cleanup code changes Added references as part of common QSPI driver changes to avoid compilation errors. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org> Change-Id: Idffe9ab4c790bc63b2840d9b29504a4c998002fe --- M src/mainboard/google/trogdor/mainboard.c M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/include/soc/addressmap.h M src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h M src/soc/qualcomm/sc7180/qcom_qup_se.c 5 files changed, 24 insertions(+), 603 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/56270/1 diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 3561a5a..7be74a1 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -9,8 +9,10 @@ #include <framebuffer_info.h> #include <soc/display/mipi_dsi.h> #include <soc/display/mdssreg.h> -#include <soc/qupv3_config.h> -#include <soc/qupv3_i2c.h> +#include <soc/qupv3_config_common.h> +#include <soc/qupv3_i2c_common.h> +#include <soc/qup_se_handlers_common.h> +#include <soc/qcom_qup_se.h> #include <soc/usb.h> #include "board.h" diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 11ece9a..8bee67e 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -5,14 +5,15 @@ decompressor-y += mmu.c decompressor-y += ../common/timer.c all-y += ../common/timer.c -all-y += spi.c +all-y += ../common/spi.c all-y += ../common/gpio.c -all-y += qupv3_i2c.c -all-y += qupv3_spi.c all-y += clock.c -all-$(CONFIG_SC7180_QSPI) += qspi.c +all-$(CONFIG_SC7180_QSPI) += ../common/qspi.c all-y += qcom_qup_se.c -all-y += qupv3_config.c +all-$(CONFIG_SC7180_QSPI) += ../common/qupv3_spi.c +all-$(CONFIG_SC7180_QSPI) += ../common/qup_se_handler.c +all-y += ../common/qupv3_config.c +all-y += ../common/qupv3_i2c.c ################################################################################ bootblock-y += bootblock.c @@ -20,7 +21,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart_bitbang.c ################################################################################ -verstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c +verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ romstage-y += cbmem.c @@ -30,14 +31,14 @@ romstage-y += mmu.c romstage-y += usb.c romstage-y += carve_out.c -romstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c +romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ ramstage-y += soc.c ramstage-y += carve_out.c ramstage-y += aop_load_reset.c ramstage-y += usb.c -ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c +ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 832ef42..c9f2e80 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -46,4 +46,14 @@ #define QMP_PHY_PCS_REG_BASE 0x088e9c00 #define USB_HOST_DWC3_BASE 0x0a60c100 +/* SC7180 QSPI GPIO PINS */ +#define QSPI_CLK GPIO(63) +#define QSPI_DATA_0 GPIO(64) +#define QSPI_DATA_1 GPIO(65) +#define QSPI_CS GPIO(68) + +#define GPIO_FUNC_QSPI_DATA_0 GPIO64_FUNC_QSPI_DATA_0 +#define GPIO_FUNC_QSPI_DATA_1 GPIO65_FUNC_QSPI_DATA_1 +#define GPIO_FUNC_QSPI_CLK GPIO63_FUNC_QSPI_CLK + #endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h index d2f171f..6829028 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h +++ b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h @@ -9,180 +9,6 @@ #include <timer.h> #include <types.h> -#define GENMASK(h, l) (BIT(h + 1) - BIT(l)) - -/* GENI_OUTPUT_CTRL fields */ -#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) - -/* GENI_FORCE_DEFAULT_REG fields */ -#define FORCE_DEFAULT BIT(0) - -#define GENI_FW_REVISION_RO_PROTOCOL_MASK 0x0000FF00 -#define GENI_FW_REVISION_RO_PROTOCOL_SHIFT 0x00000008 - -/* GENI_CGC_CTRL fields */ -#define CFG_AHB_CLK_CGC_ON BIT(0) -#define CFG_AHB_WR_ACLK_CGC_ON BIT(1) -#define DATA_AHB_CLK_CGC_ON BIT(2) -#define SCLK_CGC_ON BIT(3) -#define TX_CLK_CGC_ON BIT(4) -#define RX_CLK_CGC_ON BIT(5) -#define EXT_CLK_CGC_ON BIT(6) -#define PROG_RAM_HCLK_OFF BIT(8) -#define PROG_RAM_SCLK_OFF BIT(9) -#define DEFAULT_CGC_EN (CFG_AHB_CLK_CGC_ON | CFG_AHB_WR_ACLK_CGC_ON \ - | DATA_AHB_CLK_CGC_ON | SCLK_CGC_ON \ - | TX_CLK_CGC_ON | RX_CLK_CGC_ON | EXT_CLK_CGC_ON) - -/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ -#define SER_CLK_EN BIT(0) -#define CLK_DIV_SHFT 4 -#define CLK_DIV_MSK (0xFFF << CLK_DIV_SHFT) - -/* FIFO_IF_DISABLE_RO fields */ -#define FIFO_IF_DISABLE BIT(0) - -/* FW_REVISION_RO fields */ -#define FW_REV_PROTOCOL_MSK GENMASK(15, 8) -#define FW_REV_PROTOCOL_SHFT 8 -#define FW_REV_VERSION_SHFT 0 - -/* GENI_CLK_SEL fields */ -#define CLK_SEL_MSK GENMASK(2, 0) - -/* SE_GENI_DMA_MODE_EN */ -#define GENI_DMA_MODE_EN BIT(0) - -/* GENI_M_CMD0 fields */ -#define M_OPCODE_MSK GENMASK(31, 27) -#define M_OPCODE_SHFT 27 -#define M_PARAMS_MSK GENMASK(26, 0) - -/* GENI_M_CMD_CTRL_REG */ -#define M_GENI_CMD_CANCEL BIT(2) -#define M_GENI_CMD_ABORT BIT(1) -#define M_GENI_DISABLE BIT(0) - -/* GENI_S_CMD0 fields */ -#define S_OPCODE_MSK GENMASK(31, 27) -#define S_OPCODE_SHFT 27 -#define S_PARAMS_MSK GENMASK(26, 0) - -/* GENI_S_CMD_CTRL_REG */ -#define S_GENI_CMD_CANCEL BIT(2) -#define S_GENI_CMD_ABORT BIT(1) -#define S_GENI_DISABLE BIT(0) - -/* GENI_M_IRQ_EN fields */ -#define M_CMD_DONE_EN BIT(0) -#define M_CMD_OVERRUN_EN BIT(1) -#define M_ILLEGAL_CMD_EN BIT(2) -#define M_CMD_FAILURE_EN BIT(3) -#define M_CMD_CANCEL_EN BIT(4) -#define M_CMD_ABORT_EN BIT(5) -#define M_TIMESTAMP_EN BIT(6) -#define M_RX_IRQ_EN BIT(7) -#define M_GP_SYNC_IRQ_0_EN BIT(8) -#define M_GP_IRQ_0_EN BIT(9) -#define M_GP_IRQ_1_EN BIT(10) -#define M_GP_IRQ_2_EN BIT(11) -#define M_GP_IRQ_3_EN BIT(12) -#define M_GP_IRQ_4_EN BIT(13) -#define M_GP_IRQ_5_EN BIT(14) -#define M_IO_DATA_DEASSERT_EN BIT(22) -#define M_IO_DATA_ASSERT_EN BIT(23) -#define M_RX_FIFO_RD_ERR_EN BIT(24) -#define M_RX_FIFO_WR_ERR_EN BIT(25) -#define M_RX_FIFO_WATERMARK_EN BIT(26) -#define M_RX_FIFO_LAST_EN BIT(27) -#define M_TX_FIFO_RD_ERR_EN BIT(28) -#define M_TX_FIFO_WR_ERR_EN BIT(29) -#define M_TX_FIFO_WATERMARK_EN BIT(30) -#define M_SEC_IRQ_EN BIT(31) -#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ - M_IO_DATA_DEASSERT_EN | \ - M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ - M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ - M_TX_FIFO_WR_ERR_EN) - -/* GENI_S_IRQ_EN fields */ -#define S_CMD_DONE_EN BIT(0) -#define S_CMD_OVERRUN_EN BIT(1) -#define S_ILLEGAL_CMD_EN BIT(2) -#define S_CMD_FAILURE_EN BIT(3) -#define S_CMD_CANCEL_EN BIT(4) -#define S_CMD_ABORT_EN BIT(5) -#define S_GP_SYNC_IRQ_0_EN BIT(8) -#define S_GP_IRQ_0_EN BIT(9) -#define S_GP_IRQ_1_EN BIT(10) -#define S_GP_IRQ_2_EN BIT(11) -#define S_GP_IRQ_3_EN BIT(12) -#define S_GP_IRQ_4_EN BIT(13) -#define S_GP_IRQ_5_EN BIT(14) -#define S_IO_DATA_DEASSERT_EN BIT(22) -#define S_IO_DATA_ASSERT_EN BIT(23) -#define S_RX_FIFO_RD_ERR_EN BIT(24) -#define S_RX_FIFO_WR_ERR_EN BIT(25) -#define S_RX_FIFO_WATERMARK_EN BIT(26) -#define S_RX_FIFO_LAST_EN BIT(27) -#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ - S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) - -/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ -#define WATERMARK_MSK GENMASK(5, 0) - -/* GENI_TX_FIFO_STATUS fields */ -#define TX_FIFO_WC GENMASK(27, 0) - -/* GENI_RX_FIFO_STATUS fields */ -#define RX_LAST BIT(31) -#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) -#define RX_LAST_BYTE_VALID_SHFT 28 -#define RX_FIFO_WC_MSK GENMASK(24, 0) - -/* SE_IRQ_EN fields */ -#define DMA_RX_IRQ_EN BIT(0) -#define DMA_TX_IRQ_EN BIT(1) -#define GENI_M_IRQ_EN BIT(2) -#define GENI_S_IRQ_EN BIT(3) - -/* SE_DMA_GENERAL_CFG */ -#define DMA_RX_CLK_CGC_ON BIT(0) -#define DMA_TX_CLK_CGC_ON BIT(1) -#define DMA_AHB_SLV_CFG_ON BIT(2) -#define AHB_SEC_SLV_CLK_CGC_ON BIT(3) -#define DUMMY_RX_NON_BUFFERABLE BIT(4) -#define RX_DMA_ZERO_PADDING_EN BIT(5) -#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) -#define RX_DMA_IRQ_DELAY_SHFT 6 - -#define DEFAULT_SE_CLK (19200 * KHz) -#define GENI_DFS_IF_CFG_DFS_IF_EN_BMSK BIT(0) - -/* FIFO BUFFER PARAMETERS */ -#define BYTES_PER_FIFO_WORD 4 -#define FIFO_WIDTH 32 -#define FIFO_DEPTH 16 -#define BITS_PER_WORD 8 -#define TX_WATERMARK 1 - -/* PACKING CONFIGURATION VECTOR */ - -/* start_idx:x: Bit position to move - * direction:1: MSB to LSB - * len:7: Represents bits-per-word = 8 - * stop:0: Till it's 1, FIFO bit shift continues - */ - -/* Start_idx:7, direction:1, len:7, stop:0 */ -#define PACK_VECTOR0 0x0FE -/* Start_idx:15, direction:1, len:7, stop:0 */ -#define PACK_VECTOR1 0x1FE -/* Start_idx:23, direction:1, len:7, stop:0 */ -#define PACK_VECTOR2 0x2FE -/* Start_idx:31, direction:1, len:7, stop:1 */ -#define PACK_VECTOR3 0x3FF - enum qup_se { QUPV3_0_SE0, QUPV3_0_SE1, @@ -199,242 +25,6 @@ QUPV3_SE_MAX, }; -enum se_protocol { - SE_PROTOCOL_SPI = 1, - SE_PROTOCOL_UART = 2, - SE_PROTOCOL_I2C = 3, - SE_PROTOCOL_I3C = 4, - SE_PROTOCOL_MAX = 5 -}; - -enum se_mode { - NONE, - GSI, - FIFO, - CPU_DMA, - MIXED -}; - -struct qup_regs { - u32 geni_init_cfg_revision; - u32 geni_s_init_cfg_revision; - u8 _reserved1[0x10 - 0x08]; - u32 geni_general_cfg; - u32 geni_rx_fifo_ctrl; - u8 _reserved2[0x20 - 0x18]; - u32 geni_force_default_reg; - u32 geni_output_ctrl; - u32 geni_cgc_ctrl; - u32 geni_char_cfg; - u32 geni_char_data_n; - u8 _reserved3[0x40 - 0x34]; - u32 geni_status; - u32 geni_test_bus_ctrl; - u32 geni_ser_m_clk_cfg; - u32 geni_ser_s_clk_cfg; - u32 geni_prog_rom_ctrl_reg; - u8 _reserved4[0x60 - 0x54]; - u32 geni_clk_ctrl_ro; - u32 fifo_if_disable_ro; - u32 geni_fw_revision_ro; - u32 geni_s_fw_revision_ro; - u32 geni_fw_multilock_protns_ro; - u32 geni_fw_multilock_msa_ro; - u32 geni_fw_multilock_sp_ro; - u32 geni_clk_sel; - u32 geni_dfs_if_cfg; - u8 _reserved5[0x100 - 0x084]; - u32 geni_cfg_reg0; - u32 geni_cfg_reg1; - u32 geni_cfg_reg2; - u32 geni_cfg_reg3; - u32 geni_cfg_reg4; - u32 geni_cfg_reg5; - u32 geni_cfg_reg6; - u32 geni_cfg_reg7; - u32 geni_cfg_reg8; - u32 geni_cfg_reg9; - u32 geni_cfg_reg10; - u32 geni_cfg_reg11; - u32 geni_cfg_reg12; - u32 geni_cfg_reg13; - u32 geni_cfg_reg14; - u32 geni_cfg_reg15; - u32 geni_cfg_reg16; - u32 geni_cfg_reg17; - u32 geni_cfg_reg18; - u8 _reserved6[0x200 - 0x14C]; - u32 geni_cfg_reg64; - u32 geni_cfg_reg65; - u32 geni_cfg_reg66; - u32 geni_cfg_reg67; - u32 geni_cfg_reg68; - u32 geni_cfg_reg69; - u32 geni_cfg_reg70; - u32 geni_cfg_reg71; - u32 geni_cfg_reg72; - u32 spi_cpha; - u32 geni_cfg_reg74; - u32 proto_loopback_cfg; - u32 spi_cpol; - u32 i2c_noise_cancellation_ctl; - u32 i2c_monitor_ctl; - u32 geni_cfg_reg79; - u32 geni_cfg_reg80; - u32 geni_cfg_reg81; - u32 geni_cfg_reg82; - u32 spi_demux_output_inv; - u32 spi_demux_sel; - u32 geni_byte_granularity; - u32 geni_dma_mode_en; - u32 uart_tx_trans_cfg_reg; - u32 geni_tx_packing_cfg0; - u32 geni_tx_packing_cfg1; - union { - u32 uart_tx_word_len; - u32 spi_word_len; - }; - union { - u32 uart_tx_stop_bit_len; - u32 i2c_tx_trans_len; - u32 spi_tx_trans_len; - }; - union { - u32 uart_tx_trans_len; - u32 i2c_rx_trans_len; - u32 spi_rx_trans_len; - }; - u32 spi_pre_post_cmd_dly; - u32 i2c_scl_counters; - u32 geni_cfg_reg95; - u32 uart_rx_trans_cfg; - u32 geni_rx_packing_cfg0; - u32 geni_rx_packing_cfg1; - u32 uart_rx_word_len; - u32 geni_cfg_reg100; - u32 uart_rx_stale_cnt; - u32 geni_cfg_reg102; - u32 geni_cfg_reg103; - u32 geni_cfg_reg104; - u32 uart_tx_parity_cfg; - u32 uart_rx_parity_cfg; - u32 uart_manual_rfr; - u32 geni_cfg_reg108; - u32 geni_cfg_reg109; - u32 geni_cfg_reg110; - u8 _reserved7[0x600 - 0x2BC]; - u32 geni_m_cmd0; - u32 geni_m_cmd_ctrl_reg; - u8 _reserved8[0x10 - 0x08]; - u32 geni_m_irq_status; - u32 geni_m_irq_enable; - u32 geni_m_irq_clear; - u32 geni_m_irq_en_set; - u32 geni_m_irq_en_clear; - u32 geni_m_cmd_err_status; - u32 geni_m_fw_err_status; - u8 _reserved9[0x30 - 0x2C]; - u32 geni_s_cmd0; - u32 geni_s_cmd_ctrl_reg; - u8 _reserved10[0x40 - 0x38]; - u32 geni_s_irq_status; - u32 geni_s_irq_enable; - u32 geni_s_irq_clear; - u32 geni_s_irq_en_set; - u32 geni_s_irq_en_clear; - u8 _reserved11[0x700 - 0x654]; - u32 geni_tx_fifon; - u8 _reserved12[0x780 - 0x704]; - u32 geni_rx_fifon; - u8 _reserved13[0x800 - 0x784]; - u32 geni_tx_fifo_status; - u32 geni_rx_fifo_status; - u32 geni_tx_fifo_threshold; - u32 geni_tx_watermark_reg; - u32 geni_rx_watermark_reg; - u32 geni_rx_rfr_watermark_reg; - u8 _reserved14[0x900 - 0x818]; - u32 geni_gp_output_reg; - u8 _reserved15[0x908 - 0x904]; - u32 geni_ios; - u32 geni_timestamp; - u32 geni_m_gp_length; - u32 geni_s_gp_length; - u8 _reserved16[0x920 - 0x918]; - u32 geni_hw_irq_en; - u32 geni_hw_irq_ignore_on_active; - u8 _reserved17[0x930 - 0x928]; - u32 geni_hw_irq_cmd_param_0; - u8 _reserved18[0xA00 - 0x934]; - u32 geni_i3c_ibi_cfg_tablen; - u8 _reserved19[0xA80 - 0xA04]; - u32 geni_i3c_ibi_status; - u32 geni_i3c_ibi_rd_data; - u32 geni_i3c_ibi_search_pattern; - u32 geni_i3c_ibi_search_data; - u32 geni_i3c_sw_ibi_en; - u32 geni_i3c_sw_ibi_en_recover; - u8 _reserved20[0xC30 - 0xA98]; - u32 dma_tx_ptr_l; - u32 dma_tx_ptr_h; - u32 dma_tx_attr; - u32 dma_tx_length; - u32 dma_tx_irq_stat; - u32 dma_tx_irq_clr; - u32 dma_tx_irq_en; - u32 dma_tx_irq_en_set; - u32 dma_tx_irq_en_clr; - u32 dma_tx_length_in; - u32 dma_tx_fsm_rst; - u32 dma_tx_max_burst_size; - u8 _reserved21[0xD30 - 0xC60]; - u32 dma_rx_ptr_l; - u32 dma_rx_ptr_h; - u32 dma_rx_attr; - u32 dma_rx_length; - u32 dma_rx_irq_stat; - u32 dma_rx_irq_clr; - u32 dma_rx_irq_en; - u32 dma_rx_irq_en_set; - u32 dma_rx_irq_en_clr; - u32 dma_rx_length_in; - u32 dma_rx_fsm_rst; - u32 dma_rx_max_burst_size; - u32 dma_rx_flush; - u8 _reserved22[0xE14 - 0xD64]; - u32 se_irq_high_priority; - u32 se_gsi_event_en; - u32 se_irq_en; - u32 dma_if_en_ro; - u32 se_hw_param_0; - u32 se_hw_param_1; - u32 se_hw_param_2; - u32 dma_general_cfg; - u8 _reserved23[0x40 - 0x34]; - u32 dma_debug_reg0; - u32 dma_test_bus_ctrl; - u32 se_top_test_bus_ctrl; - u8 _reserved24[0x1000 - 0x0E4C]; - u32 se_geni_fw_revision; - u32 se_s_fw_revision; - u8 _reserved25[0x10-0x08]; - u32 se_geni_cfg_ramn; - u8 _reserved26[0x2000 - 0x1014]; - u32 se_geni_clk_ctrl; - u32 se_dma_if_en; - u32 se_fifo_if_disable; - u32 se_geni_fw_multilock_protns; - u32 se_geni_fw_multilock_msa; - u32 se_geni_fw_multilock_sp; -}; -check_member(qup_regs, geni_clk_sel, 0x7C); -check_member(qup_regs, geni_cfg_reg108, 0x2B0); -check_member(qup_regs, geni_dma_mode_en, 0x258); -check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84); -check_member(qup_regs, dma_test_bus_ctrl, 0xE44); -check_member(qup_regs, se_geni_cfg_ramn, 0x1010); -check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014); - struct qup { struct qup_regs *regs; gpio_t pin[6]; @@ -443,11 +33,6 @@ extern struct qup qup[12]; -u32 qup_wait_for_m_irq(unsigned int bus); -u32 qup_wait_for_s_irq(unsigned int bus); -void qup_m_cancel_and_abort(unsigned int bus); -void qup_s_cancel_and_abort(unsigned int bus); -int qup_handle_transfer(unsigned int bus, const void *dout, void *din, - int size); +#define MAX_OFFSET_CFG_REG 0x000001c0 #endif /* __SOC_QCOM_QUP_SE_H__ */ diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index 6750c3e..ce23a35 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -67,180 +67,3 @@ GPIO55_FUNC_QUP1_L2, GPIO56_FUNC_QUP1_L3 } }, }; - -u32 qup_wait_for_m_irq(unsigned int bus) -{ - struct stopwatch sw; - unsigned int m_irq = 0; - struct qup_regs *regs = qup[bus].regs; - - stopwatch_init_usecs_expire(&sw, 25); - while (!stopwatch_expired(&sw)) { - m_irq = read32(&regs->geni_m_irq_status); - if (m_irq) - break; - } - return m_irq; -} - -u32 qup_wait_for_s_irq(unsigned int bus) -{ - struct stopwatch sw; - unsigned int s_irq = 0; - struct qup_regs *regs = qup[bus].regs; - - stopwatch_init_usecs_expire(&sw, 25); - while (!stopwatch_expired(&sw)) { - s_irq = read32(&regs->geni_s_irq_status); - if (s_irq) - break; - } - return s_irq; -} - -static int handle_tx(unsigned int bus, const u8 *dout, - unsigned int tx_rem_bytes) -{ - int max_bytes = 0; - struct qup_regs *regs = qup[bus].regs; - - max_bytes = (FIFO_DEPTH - TX_WATERMARK) * BYTES_PER_FIFO_WORD; - max_bytes = MIN(tx_rem_bytes, max_bytes); - - buffer_to_fifo32((void *)dout, max_bytes, &regs->geni_tx_fifon, - 0, BYTES_PER_FIFO_WORD); - - if (tx_rem_bytes == max_bytes) - write32(&regs->geni_tx_watermark_reg, 0); - return max_bytes; -} - -static int handle_rx(unsigned int bus, u8 *din, unsigned int rx_rem_bytes) -{ - struct qup_regs *regs = qup[bus].regs; - u32 rx_fifo_status = read32(&regs->geni_rx_fifo_status); - int rx_bytes = 0; - - rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * BYTES_PER_FIFO_WORD; - rx_bytes = MIN(rx_rem_bytes, rx_bytes); - - buffer_from_fifo32(din, rx_bytes, &regs->geni_rx_fifon, - 0, BYTES_PER_FIFO_WORD); - return rx_bytes; -} - -void qup_m_cancel_and_abort(unsigned int bus) -{ - struct qup_regs *regs = qup[bus].regs; - struct stopwatch sw; - unsigned int m_irq; - - write32(&regs->geni_tx_watermark_reg, 0); - write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_CANCEL); - - stopwatch_init_msecs_expire(&sw, 100); - do { - m_irq = qup_wait_for_m_irq(bus); - if (m_irq & M_CMD_CANCEL_EN) { - write32(&regs->geni_m_irq_clear, m_irq); - break; - } - write32(&regs->geni_m_irq_clear, m_irq); - } while (!stopwatch_expired(&sw)); - - if (!(m_irq & M_CMD_CANCEL_EN)) { - printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n", - __func__); - - write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_ABORT); - stopwatch_init_msecs_expire(&sw, 100); - do { - m_irq = qup_wait_for_m_irq(bus); - if (m_irq & M_CMD_ABORT_EN) { - write32(&regs->geni_m_irq_clear, m_irq); - break; - } - write32(&regs->geni_m_irq_clear, m_irq); - } while (!stopwatch_expired(&sw)); - - if (!(m_irq & M_CMD_ABORT_EN)) - printk(BIOS_INFO, "%s:Abort failed\n", __func__); - } -} - -void qup_s_cancel_and_abort(unsigned int bus) -{ - struct qup_regs *regs = qup[bus].regs; - struct stopwatch sw; - unsigned int s_irq; - u32 rx_fifo_status; - u8 buf[64]; /* FIFO size */ - - write32(&regs->geni_tx_watermark_reg, 0); - write32(&regs->geni_s_cmd_ctrl_reg, S_GENI_CMD_CANCEL); - - stopwatch_init_msecs_expire(&sw, 100); - do { - s_irq = qup_wait_for_s_irq(bus); - rx_fifo_status = read32(&regs->geni_rx_fifo_status); - if (rx_fifo_status & RX_LAST) - handle_rx(bus, buf, 64); /* Read whatever data available in FIFO */ - if (s_irq & S_CMD_CANCEL_EN) { - write32(&regs->geni_s_irq_clear, s_irq); - break; - } - write32(&regs->geni_s_irq_clear, s_irq); - } while (!stopwatch_expired(&sw)); - - if (!(s_irq & S_CMD_CANCEL_EN)) { - printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n", - __func__); - - write32(&regs->geni_s_cmd_ctrl_reg, S_GENI_CMD_ABORT); - stopwatch_init_msecs_expire(&sw, 100); - do { - s_irq = qup_wait_for_s_irq(bus); - if (s_irq & S_CMD_ABORT_EN) { - write32(&regs->geni_s_irq_clear, s_irq); - break; - } - write32(&regs->geni_s_irq_clear, s_irq); - } while (!stopwatch_expired(&sw)); - - if (!(s_irq & S_CMD_ABORT_EN)) - printk(BIOS_INFO, "%s:Abort failed\n", __func__); - } -} - -int qup_handle_transfer(unsigned int bus, const void *dout, void *din, int size) -{ - unsigned int m_irq; - struct stopwatch sw; - unsigned int rx_rem_bytes = din ? size : 0; - unsigned int tx_rem_bytes = dout ? size : 0; - struct qup_regs *regs = qup[bus].regs; - - stopwatch_init_msecs_expire(&sw, 1000); - do { - m_irq = qup_wait_for_m_irq(bus); - if ((m_irq & M_RX_FIFO_WATERMARK_EN) || - (m_irq & M_RX_FIFO_LAST_EN)) - rx_rem_bytes -= handle_rx(bus, din + size - - rx_rem_bytes, rx_rem_bytes); - if (m_irq & M_TX_FIFO_WATERMARK_EN) - tx_rem_bytes -= handle_tx(bus, dout + size - - tx_rem_bytes, tx_rem_bytes); - if (m_irq & M_CMD_DONE_EN) { - write32(&regs->geni_m_irq_clear, m_irq); - break; - } - write32(&regs->geni_m_irq_clear, m_irq); - } while (!stopwatch_expired(&sw)); - - if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) { - printk(BIOS_INFO, "%s:Error: Transfer failed\n", __func__); - qup_m_cancel_and_abort(bus); - return -1; - } - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/56270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idffe9ab4c790bc63b2840d9b29504a4c998002fe Gerrit-Change-Number: 56270 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/qualcomm/common/usb: Add support for common USB driver
by Ravi kumar (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Ravi kumar, Shelley Chen, Sandeep Maheswaram, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56091 to look at the new patch set (#3). Change subject: soc/qualcomm/common/usb: Add support for common USB driver ...................................................................... soc/qualcomm/common/usb: Add support for common USB driver Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 --- M src/soc/qualcomm/common/Kconfig A src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/qusb_phy.h A src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/usb_common.h A src/soc/qualcomm/common/usb/qmp_usb_phy.c A src/soc/qualcomm/common/usb/qusb_phy.c A src/soc/qualcomm/common/usb/snps_usb_phy.c A src/soc/qualcomm/common/usb/usb.c 9 files changed, 1,403 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56091/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Gerrit-Change-Number: 56091 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Add MMIO support in PCI lib
by Ravi kumar (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, Julius Werner, Prasad Malisetty, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Furquan Shaikh, Ravi Kumar Bokka, Julius Werner, Arthur Heymans, Prasad Malisetty, mturney mturney, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53903 to look at the new patch set (#23). Change subject: libpayload: Add MMIO support in PCI lib ...................................................................... libpayload: Add MMIO support in PCI lib Added MMIO Support in libpayload pci driver to allow ep config space access using payload PCI functions. endpoint config space address passed from coreboot to payload through coreboot tables if MMIO supports. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I7cfb95e31b7ee984ee0c2e7586e6caeecd7deadd Signed-off-by: Prasad Malisetty <pmaliset(a)codeaurora.org> --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pci_ops.c M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/soc/qualcomm/sc7280/Kconfig 11 files changed, 199 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/53903/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/53903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cfb95e31b7ee984ee0c2e7586e6caeecd7deadd Gerrit-Change-Number: 53903 Gerrit-PatchSet: 23 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021