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Change subject: soc/intel/alderlake: Fix booting issue with MultiPhaseSiInit API skip
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56382/comment/d4213f80_0434de91
PS2, Line 7: Fix booting issue with MultiPhaseSiInit API skip
Nit: *Fix* implies issues (at least for me). Shorter:
> Fix boot with MiltiPhaseSiInit API skip
Maybe even *hang* instead of *boot*.
https://review.coreboot.org/c/coreboot/+/56382/comment/559cab64_9931569d
PS2, Line 12: FSP would results into a hang while calling FSP-Notify Phase if
: EnableMultiPhaseSiliconInit UPD remains enable but bootloader don't
: make call into MultiPhaseSiInit as
: soc_fsp_multi_phase_init_is_enable() returns 0.
Which FSP version? I would put the problem description at the beginning.
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Change subject: mb/google/kahlee/Kconfig: add board-specific MAINBOARD_PART_NUMBER
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Patch Set 2: Code-Review+2
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Change subject: mb/google/brya: Create taeko variant
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56385/comment/485a7578_7a76a337
PS1, Line 12: ).
Please put the dot/period before the ).
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Change subject: mb/google/trogdor: Add new variant Womdingler
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Patch Set 3: Code-Review+1
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Change subject: mb/google/kahlee/Kconfig: add board-specific MAINBOARD_PART_NUMBER
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Change subject: mb/google/brya: move the common config to the baseboard
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56387/comment/2bb0f227_672facfa
PS1, Line 10: remove
removes
https://review.coreboot.org/c/coreboot/+/56387/comment/8023485c_5634b0fd
PS1, Line 9: This patch moves the common config to the Kconfig
: under BOARD_GOOGLE_BASEBOARD_BRYA and remove the
: redundant config.
Please reflow for 75 characters per line.
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Change subject: Add console deinit API, use in SMM handler
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56386/comment/e95ff3e0_50e45a38
PS6, Line 11: When CONFIG_DEBUG_SMI is enabled SMM handler performs console
No need to break the line after a sentence.
https://review.coreboot.org/c/coreboot/+/56386/comment/ea2fb39b_be47d145
PS6, Line 15: Linux
: kernel
Please add the version.
https://review.coreboot.org/c/coreboot/+/56386/comment/12f6a4c0_d0fdee2c
PS6, Line 19: For 8250, we save all the registers we touch in init and restore them in deinit.
Please wrap lines after 75 characters.
https://review.coreboot.org/c/coreboot/+/56386/comment/62adfedf_b2b312c9
PS6, Line 22:
Please mention the hardware you reproduced this with.
File src/cpu/x86/smm/smm_module_handler.c:
https://review.coreboot.org/c/coreboot/+/56386/comment/07bfc9d7_35ccdf9f
PS6, Line 184: * but the OS may be using interrupt mode. */
Please use one of the recommended multiline comment styles [1].
[1]: https://doc.coreboot.org/contributing/coding_style.html#commenting
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Change subject: intel/common/*timer/Kconfig : Add default for TIANOCORE
......................................................................
Patch Set 1:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56367/comment/9a66f97a_e6432a41
PS1, Line 7: intel/common/*timer/Kconfig :
Please remove the space before the colon.
https://review.coreboot.org/c/coreboot/+/56367/comment/bb9db50c_9b4f025c
PS1, Line 7: TIANOCORE
TianoCore
https://review.coreboot.org/c/coreboot/+/56367/comment/3c9b185d_0308a1cb
PS1, Line 7: intel/common/*timer/Kconfig
Maybe:
> soc/intel/common: timer: Select legacy 8254 timer for TianoCore
https://review.coreboot.org/c/coreboot/+/56367/comment/05c5306c_022b216d
PS1, Line 10: Tianocore payload
Please describe the TianoCore error you get.
File src/soc/intel/common/block/timer/Kconfig:
https://review.coreboot.org/c/coreboot/+/56367/comment/b317402c_1b86d861
PS1, Line 8: default y if PAYLOAD_SEABIOS || VGA_ROM_RUN || PAYLOAD_TIANOCORE
Why wasn’t it needed in the past for TianoCore?
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Change subject: soc/amd/cezanne: enable crypto in PSP
......................................................................
Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55833/comment/b7567ade_157c1a18
PS2, Line 9: Enable crypto functions
Please elaborate in the commit message, which ones.
https://review.coreboot.org/c/coreboot/+/55833/comment/adea3ee0_d31b90b6
PS2, Line 9: cezanne
You also change Picasso.
https://review.coreboot.org/c/coreboot/+/55833/comment/f0ba20ba_21ad0a8e
PS2, Line 9: since support has been added
Please reference the commit.
https://review.coreboot.org/c/coreboot/+/55833/comment/9189a33a_8c6e9f2c
PS2, Line 10:
Tested how?
File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h:
https://review.coreboot.org/c/coreboot/+/55833/comment/3c6a55f3_f882c8a5
PS2, Line 293: /* Calculate ModEx
For consistency, please add a blank comment line at the top.
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Change subject: mb/google/kahlee/Kconfig: add board-specific MAINBOARD_PART_NUMBER
......................................................................
Patch Set 2: Code-Review+1
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