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Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB_NV
......................................................................
Patch Set 8:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/apob_cache.h:
https://review.coreboot.org/c/coreboot/+/56232/comment/a2c379ed_ddbbc23d
PS8, Line 7: start_apob_cache_read
> Any reason not to do this as part of one of the earliest boot states?
We need to time it so we don't introduce any contention on the SPI bus. My goal right now is to run it after FSP-S loads so we don't slow down loading FSP-S. Once I get all the pieces in place I will reevaluate adding these preload calls into common code.
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Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB_NV
......................................................................
Patch Set 8:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/apob_cache.h:
https://review.coreboot.org/c/coreboot/+/56232/comment/ba01cb66_5c787dfe
PS8, Line 7: start_apob_cache_read
Any reason not to do this as part of one of the earliest boot states?
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Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
......................................................................
Patch Set 7:
(1 comment)
File src/soc/amd/common/block/lpc/spi_dma.c:
https://review.coreboot.org/c/coreboot/+/56228/comment/de6d74cd_4be87d9a
PS7, Line 101: We should have complete control over the DMA controller, so there shouldn't
: * be any outstanding transactions.
> This was more me being paranoid to verify that the PSP in fact was not using the SPI DMA. […]
Ack.
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Change subject: lib/thread: Add mutex
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56230/comment/0af7f3a8_10758cb8
PS7, Line 14:
: If a task (A) wishes to yield control to the next task (B) that is
: holding onto the mutex, without encountering a delay of its own
: (i.e., udelay(0)), then we need to ensure the next task (B) is at the
: head of the queue. We do this by using a `0 us` delay in mutex_lock. If
: we were to use anything larger than a `0 us` delay, a `udelay(0)` by the
: task (A) that just unlocked the mutex will most likely not schedule the
: next task (B) that was holding onto the mutex.
> Maybe its just me. But I find this example really confusing. […]
I can remove this paragraph now. The mutex just uses `thread_yield()` so we don't need an elaborate explanation.
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Change subject: lib/thread: Clean up initialization sequence
......................................................................
Patch Set 1:
(1 comment)
File src/lib/thread.c:
https://review.coreboot.org/c/coreboot/+/56356/comment/20094b96_65115c11
PS1, Line 261: t->can_yield = 1;
> Why do we need to set this explicitly at this point? `prepare_thread()` always marks new threads as […]
We never call `prepare_thread()` for the BSP thread.
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Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
......................................................................
Patch Set 7:
(1 comment)
File src/soc/amd/common/block/lpc/spi_dma.c:
https://review.coreboot.org/c/coreboot/+/56228/comment/175eb934_e492a6d3
PS7, Line 101: We should have complete control over the DMA controller, so there shouldn't
: * be any outstanding transactions.
> Based on the comment you added on line 230, can there ever be a scenario that PSP decides to use the […]
This was more me being paranoid to verify that the PSP in fact was not using the SPI DMA. I don't think the PSP currently uses it since the DMA controller can only write to x86 memory.
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Change subject: soc/amd/cezanne: Add support for Modern Standby event logging
......................................................................
Patch Set 1: Code-Review+2
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