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Hello build bot (Jenkins), Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: arch/x86: Add missing SPD memory type 72b-SO-UDIMM and Non-DIMM
......................................................................
arch/x86: Add missing SPD memory type 72b-SO-UDIMM and Non-DIMM
This patch fixes the form factor type `unknown` issue on ADLRVP and Brya
with `row of chips` as applicable for `Non-DIMM` Memory Type.
Refer to datasheet SPD4.1.2.M-1 for LPDDR4 and SPD4.1.2.L-3 for DDR4.
BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Unknown
....
With this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Row Of Chips
....
Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/arch/x86/smbios.c
M src/include/spd.h
2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56628/7
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Change subject: mb/google/dedede/var/cappy2: Add I2C devices
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56513/comment/d2fcb4fa_0c4ae228
PS7, Line 9: Add I2C devices support in devicetree.
> Please mention the devices you are adding in the commit message.
Done
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Hello build bot (Jenkins), Henry Sun, Werner Zeh, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: mb/google/dedede/var/cappy2: Add I2C devices
......................................................................
mb/google/dedede/var/cappy2: Add I2C devices
Add tp and audio devices support in devicetree.
BUG=None
BRANCH=dedede
TEST=i2c devices function is OK
Signed-off-by: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com>
Change-Id: I995e93b5a4c4294d6f6b97c48d14fabf48004d92
---
M src/mainboard/google/dedede/variants/cappy2/overridetree.cb
1 file changed, 56 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/56513/8
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Change subject: arch/x86: Add missing SPD memory type 72b-SO-UDIMM and Non-DIMM
......................................................................
Patch Set 6: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56628/comment/c4f85b9f_48e642a1
PS6, Line 9: This patch fixes the form factor type `unknown` issue on ADLRVP and Brya.
Maybe mention the new form factor *row of chips*?
https://review.coreboot.org/c/coreboot/+/56628/comment/4f82298c_c9e68da9
PS6, Line 10:
The datasheet name and revision would be nice to have.
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Change subject: soc/intel/alderlake: Disable Crashlog by default
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya: Disable crashlog on brya
......................................................................
mb/google/brya: Disable crashlog on brya
Crashlog is a debug feature and not used in normal mode of operation.
Disabling this feature will allow us to disable unused IPs and also
provide boot time savings of ~5-7 ms.
BUG=b:188577893
BRANCH=None
TEST=Platform boots and no function impact
Change-Id: I1f7def4ea41ff7a566aada080be1e791c11766e6
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/56654/1
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 03a14e4..5755a09 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -5,7 +5,6 @@
select DRIVERS_GENESYSLOGIC_GL9755
select DRIVERS_INTEL_MIPI_CAMERA
select SOC_INTEL_COMMON_BLOCK_IPU
- select SOC_INTEL_CRASHLOG
config BOARD_GOOGLE_PRIMUS
bool "-> Primus"
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Change subject: soc/intel/alderlake: Disable Crashlog by default
......................................................................
soc/intel/alderlake: Disable Crashlog by default
Disabling crashlog by default since it is a debug feature.
Since we don't use debug features in normal mode, disabling crashlog
feature by default. It'll also give us boot time savings of around
5-7 ms.
BUG=b:188577893
BRANCH=None
TEST=platform boots and no function impact observed
Change-Id: I4e420a2b84a60af3ec9c646a649d9bb765758b23
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/alderlake/chipset.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/56653/1
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 532ec38..427e3c9 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -55,7 +55,7 @@
end
device pci 08.0 alias gna off end
device pci 09.0 alias north_tracehub off end
- device pci 0a.0 alias crashlog on end
+ device pci 0a.0 alias crashlog off end
device pci 0d.0 alias tcss_xhci off
chip drivers/usb/acpi
register "type" = "UPC_TYPE_HUB"
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