coreboot-gerrit July 2021

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Set the xHCI LFPS period sampling off...
by Patrick Georgi (Code Review) 28 Jul '21

28 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56518 ) Change subject: mb/google/dedede/var/sasukette: Set the xHCI LFPS period sampling off time to 0ms ...................................................................... mb/google/dedede/var/sasukette: Set the xHCI LFPS period sampling off time to 0ms LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:191426542 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: I3be7adad49f87956a6764ad91fec6e76681b393f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56518 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Chiasheng Lee <chiasheng.lee(a)intel.com> --- M src/mainboard/google/dedede/variants/sasukette/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Chiasheng Lee: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 776ba8a..0624a0e 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -81,6 +81,8 @@ register "tcc_offset" = "10" # TCC of 95C + register "xhci_lfps_sampling_offtime_ms" = "0" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/56518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be7adad49f87956a6764ad91fec6e76681b393f Gerrit-Change-Number: 56518 Gerrit-PatchSet: 4 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Chiasheng Lee <chiasheng.lee(a)intel.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jessie Xu <xuyanan(a)huaqin.corp-partner.google.com> Gerrit-CC: Rui Huang <huangrui(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/collis: Update DPTF parameters for DVT build
by Patrick Georgi (Code Review) 28 Jul '21

28 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56512 ) Change subject: mb/google/volteer/var/collis: Update DPTF parameters for DVT build ...................................................................... mb/google/volteer/var/collis: Update DPTF parameters for DVT build Update Passive Policy and TCHG parameters. BUG=b:188936764 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Id75bfa74ba353f2342c95bcf8d73cd83c957deb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56512 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/collis/overridetree.cb 1 file changed, 6 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/collis/overridetree.cb b/src/mainboard/google/volteer/variants/collis/overridetree.cb index 5ae6b51..86a36b0 100644 --- a/src/mainboard/google/volteer/variants/collis/overridetree.cb +++ b/src/mainboard/google/volteer/variants/collis/overridetree.cb @@ -56,7 +56,8 @@ ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 52, 10000), - [1] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 53, 30000)}" + [1] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 58, 30000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 53, 10000)}" ## Power Limits Control # 7-9W PL1 in 200mW increments, avg over 28-32s interval @@ -75,10 +76,10 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 2500 }, - [1] = { 24, 1900 }, - [2] = { 16, 1500 }, - [3] = { 8, 1000 }}" + [0] = { 40, 2500 }, + [1] = { 30, 1900 }, + [2] = { 24, 1500 }, + [3] = { 16, 1000 }}" ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf" = "{[0] = {0}}" -- To view, visit https://review.coreboot.org/c/coreboot/+/56512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id75bfa74ba353f2342c95bcf8d73cd83c957deb5 Gerrit-Change-Number: 56512 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [DoNotMerge]Revert "mb/google/brya0: Enable MIPI UFC"
by Varshit B Pandya (Code Review) 28 Jul '21

28 Jul '21

Varshit B Pandya has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/56129 ) Change subject: [DoNotMerge]Revert "mb/google/brya0: Enable MIPI UFC" ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/56129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I369cca6998295e26b585b3448214e4739a896e9f Gerrit-Change-Number: 56129 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scan
by Werner Zeh (Code Review) 28 Jul '21

28 Jul '21

Attention is currently required from: Paul Menzel, Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56631 ) Change subject: mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scan ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56631/comment/a49c73f7_91697f3b PS1, Line 10: takes > Will do. Done File src/mainboard/siemens/mc_ehl/mainboard.c: https://review.coreboot.org/c/coreboot/+/56631/comment/52f572d3_d9224b0f PS1, Line 91: uint32_t > You mean long instead of uint32_t? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd Gerrit-Change-Number: 56631 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 28 Jul 2021 11:23:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed
by Werner Zeh (Code Review) 28 Jul '21

28 Jul '21

Attention is currently required from: Paul Menzel, Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56632 ) Change subject: mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56632/comment/cacf0919_6151c35f PS1, Line 10: old drivers > These are proprietary non-public drivers embedded in an proprietary OS, I doubt that these versions […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1 Gerrit-Change-Number: 56632 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 28 Jul 2021 11:23:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Configure H21 as GPO
by Varshit B Pandya (Code Review) 28 Jul '21

28 Jul '21

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56655 ) Change subject: mb/google/brya: Configure H21 as GPO ...................................................................... mb/google/brya: Configure H21 as GPO As per the schematics, UFC has on card oscillator so we donot need H21 in NF1 that is IMGCLKOUT H21 is used to enable this oscialltor so configuring it as 1 Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d --- M src/mainboard/google/brya/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/56655/1 diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index bb74526..fd58cd7 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -299,7 +299,7 @@ /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H20, 1, DEEP), /* H21 : IMGCLKOUT2 ==> UCAM_MCLK */ - PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_H21, 1, DEEP), /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d Gerrit-Change-Number: 56655 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: create dynamic power limits mechanism for thermal
by Zhuohao Lee (Code Review) 28 Jul '21

28 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Sumeet R Pawnikar, Aaron Durbin, Karthik Ramasubramanian. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56515 ) Change subject: mb/google/brya: create dynamic power limits mechanism for thermal ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/56515/comment/97f0149a_84c23051 PS1, Line 30: field THERMAL 15 17 : option POWER_LIMITS_282 0 : option POWER_LIMITS_482 1 : option POWER_LIMITS_682 2 : end > Thanks for this suggestion. […] Sorry, let me reopen this thread for the discussion. I think using the CPU sku to switch the DPTF may not meet the expectation. For example, if there are two projects which use the same MB and the same firmware build target but using the different chassis, the DTPF setting should be different. However, If we use the CPU SKU to distinguish the setting, then we can't distinguish the firmware is running on which device at runtime and we need to set the lower DPTF config for both projects. -- To view, visit https://review.coreboot.org/c/coreboot/+/56515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86619516adeec13642f02ba7faf9fc4945ad774e Gerrit-Change-Number: 56515 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 28 Jul 2021 11:14:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Don't suppress SPD Module Type value
by Subrata Banik (Code Review) 28 Jul '21

28 Jul '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56650 ) Change subject: soc/intel/common: Don't suppress SPD Module Type value ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56650/comment/ba3d96c0_3ae9906a PS2, Line 13: > Tested how? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3f38c24efa6a8685639bb607926e2fd9c702ff6 Gerrit-Change-Number: 56650 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 28 Jul 2021 10:57:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Don't suppress SPD Module Type value
by Subrata Banik (Code Review) 28 Jul '21

28 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56650 to look at the new patch set (#3). Change subject: soc/intel/common: Don't suppress SPD Module Type value ...................................................................... soc/intel/common: Don't suppress SPD Module Type value This patch fixes an issue where SPD original module type is getting suppressed due to DDR2 module type conversion. Make use of default case to pass the original SPD module type without overriding to `undefined` SPD memory type as part of DDR2 module type conversion. BUG=b:194659789 TEST=Verified this code changes with CB:56628 and Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia3f38c24efa6a8685639bb607926e2fd9c702ff6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/smbios.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/56650/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3f38c24efa6a8685639bb607926e2fd9c702ff6 Gerrit-Change-Number: 56650 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Add missing SPD memory type 72b-SO-UDIMM and Non-DIMM
by Subrata Banik (Code Review) 28 Jul '21

28 Jul '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56628 ) Change subject: arch/x86: Add missing SPD memory type 72b-SO-UDIMM and Non-DIMM ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56628/comment/167215e8_94a30c25 PS6, Line 9: This patch fixes the form factor type `unknown` issue on ADLRVP and Brya. > Maybe mention the new form factor *row of chips*? Ack https://review.coreboot.org/c/coreboot/+/56628/comment/205d0479_c219ba4f PS6, Line 10: > The datasheet name and revision would be nice to have. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Jul 2021 10:55:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit July 2021