coreboot-gerrit July 2021

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSP
by EricR Lai (Code Review) 29 Jul '21

29 Jul '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56682 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSP ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSP Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08 --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h 1 file changed, 17 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/56682/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h index 3fad944..3722749 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h @@ -132,27 +132,21 @@ // // Matches MrcDdrType enum in MRC // -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 #endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 #endif #ifndef MRC_DDR_TYPE_LPDDR4 #define MRC_DDR_TYPE_LPDDR4 3 #endif -#ifndef MRC_DDR_TYPE_WIO2 -#define MRC_DDR_TYPE_WIO2 4 -#endif #ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 5 +#define MRC_DDR_TYPE_UNKNOWN 4 #endif -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported #define MAX_TRACE_REGION 5 #define MAX_TRACE_CACHE_TYPE 2 @@ -262,9 +256,18 @@ SiMrcVersion Version; BOOLEAN EccSupport; UINT8 MemoryProfile; + UINT8 IsDMBRunning; ///< Memory Trained with Dynamic Memory Boost (DMB) UINT32 TotalPhysicalMemorySize; UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + /// + /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported. + /// Bit 0: XMP Profile 1 capability status + /// Bit 1: XMP Profile 2 capability status + /// Bit 2: XMP Profile 3 capability status + /// Bit 3: User Profile 4 capability status + /// Bit 4: User Profile 5 capability status + /// + UINT8 XmpProfileEnable; UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 UINT8 RefClk; -- To view, visit https://review.coreboot.org/c/coreboot/+/56682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08 Gerrit-Change-Number: 56682 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Use HDA TMODE 8T to match spec for ADL P RVP
by Sathya Prakash M R (Code Review) 29 Jul '21

29 Jul '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Sugnan Prabhu S. Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56208 ) Change subject: mb/intel/adlrvp: Use HDA TMODE 8T to match spec for ADL P RVP ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: @subrata - can we merge ? -- To view, visit https://review.coreboot.org/c/coreboot/+/56208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33 Gerrit-Change-Number: 56208 Gerrit-PatchSet: 3 Gerrit-Owner: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Comment-Date: Thu, 29 Jul 2021 03:49:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: create dynamic power limits mechanism for thermal
by Zhuohao Lee (Code Review) 29 Jul '21

29 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Sumeet R Pawnikar, Aaron Durbin, Karthik Ramasubramanian. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56515 ) Change subject: mb/google/brya: create dynamic power limits mechanism for thermal ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/56515/comment/02943fa8_d538ab77 PS1, Line 30: field THERMAL 15 17 : option POWER_LIMITS_282 0 : option POWER_LIMITS_482 1 : option POWER_LIMITS_682 2 : end > This is just for Brya0, each mainboard can set their own individual policies. So, by taking the previous example, we can add the THERMAL bits to FW_CONFIG for the different chassis, right? From the current patchset 5, we can overwrite variant_update_power_limits per board, do we need to add THERMAL bits in the variant_update_power_limits or in the overridetree.cb? -- To view, visit https://review.coreboot.org/c/coreboot/+/56515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86619516adeec13642f02ba7faf9fc4945ad774e Gerrit-Change-Number: 56515 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 29 Jul 2021 03:29:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update descriptor region for board ID 2
by Furquan Shaikh (Code Review) 29 Jul '21

29 Jul '21

Attention is currently required from: Tim Wawrzynczak, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56681 ) Change subject: mb/google/brya: Update descriptor region for board ID 2 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > We can do this in FIT as well right? I thought we already change that... […] Yeah, can we set the frequency to 50MHz by default in FIT strap? I think boards with SPI on DB should work fine as confirmed by Will. -- To view, visit https://review.coreboot.org/c/coreboot/+/56681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc4cca72f72eceededf2790f28124e46a02d12dc Gerrit-Change-Number: 56681 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 29 Jul 2021 02:54:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update descriptor region for board ID 2
by EricR Lai (Code Review) 29 Jul '21

29 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56681 ) Change subject: mb/google/brya: Update descriptor region for board ID 2 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: We can do this in FIT as well right? I thought we already change that...woops -- To view, visit https://review.coreboot.org/c/coreboot/+/56681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc4cca72f72eceededf2790f28124e46a02d12dc Gerrit-Change-Number: 56681 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Jul 2021 02:02:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: helpers: Add GENMASK macro
by Yu-Ping Wu (Code Review) 29 Jul '21

29 Jul '21

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56543 ) Change subject: helpers: Add GENMASK macro ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56543/comment/7014c074_2eb95b8c PS5, Line 12: helpers.h, for unsigned long and unsigned long long types, respectively. > Do we really need two helpers? What happens if you just make it ULL to begin with, does it throw war […] I was worried that this would accidentally change the existing behavior that we might not be aware of. In most cases the macro is used for read32/write32, so I guess we'll be fine. File src/commonlib/bsd/include/commonlib/bsd/helpers.h: https://review.coreboot.org/c/coreboot/+/56543/comment/04c91151_08cee17c PS5, Line 65: #define GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) > This file is BSD-licensed, so please don't copy Linux code wholesale (including the comment) in here […] Done. Changed back to my own comment. File src/soc/mediatek/common/pll.c: https://review.coreboot.org/c/coreboot/+/56543/comment/7a59900c_a2598d9a PS5, Line 3: #include <commonlib/bsd/helpers.h> > Prefer to just #include <types.h> instead of including this directly. Done. Could you explain more on that? Is it because types.h is the place where we group all common headers together? /* types.h is supposed to provide the standard headers defined in here: */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Gerrit-Change-Number: 56543 Gerrit-PatchSet: 6 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Jul 2021 00:54:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: helpers: Add GENMASK macro
by Yu-Ping Wu (Code Review) 29 Jul '21

29 Jul '21

Attention is currently required from: Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Jakub Czapiga, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56543 to look at the new patch set (#6). Change subject: helpers: Add GENMASK macro ...................................................................... helpers: Add GENMASK macro The GENMASK is defined in multiple files (with various names such as MASKBIT), which sets certain consecutive bits to 1 and leaves the others to 0. To avoid duplicate macros, add GENMASK macro to helpers.h. GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000. Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in mmio.h. BUG=none TEST=make tests/commonlib/bsd/helpers-test TEST=emerge-cherry coreboot BRANCH=none Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/commonlib/bsd/include/commonlib/bsd/helpers.h M src/include/device/mmio.h M src/soc/mediatek/common/pll.c M src/soc/mediatek/mt8195/dptx_hal.c M src/soc/mediatek/mt8195/include/soc/dptx_hal.h M src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h M tests/commonlib/bsd/helpers-test.c 7 files changed, 33 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/56543/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Gerrit-Change-Number: 56543 Gerrit-PatchSet: 6 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/spd_tools/lp4x: Add new memory parts and generate SPDs
by 9elements QA (Code Review) 29 Jul '21

29 Jul '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56597 ) Change subject: util/spd_tools/lp4x: Add new memory parts and generate SPDs ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 1 / 13 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/70910 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/70909 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/70908 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/70907 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/70906 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/70905 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/70904 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/70903 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/70902 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/70901 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/70900 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/70899 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/70898 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/56597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970 Gerrit-Change-Number: 56597 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 28 Jul 2021 23:55:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/elogtool: add tool to print elog events
by Jack Rosenthal (Code Review) 29 Jul '21

29 Jul '21

Attention is currently required from: Ricardo Quesada, Paul Menzel. Jack Rosenthal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56406 ) Change subject: util/elogtool: add tool to print elog events ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: Really cool to see this, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/56406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1fe1c9ed3c4c6bda846055d4b10943b54463935 Gerrit-Change-Number: 56406 Gerrit-PatchSet: 4 Gerrit-Owner: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 28 Jul 2021 23:09:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Move ELOG defines/struct to commonib/bsd/elog.h
by Jack Rosenthal (Code Review) 29 Jul '21

29 Jul '21

Attention is currently required from: Ricardo Quesada. Jack Rosenthal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56405 ) Change subject: Move ELOG defines/struct to commonib/bsd/elog.h ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f307f599a311810df2367b7c888f650cff1214a Gerrit-Change-Number: 56405 Gerrit-PatchSet: 3 Gerrit-Owner: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Comment-Date: Wed, 28 Jul 2021 23:08:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2021