June 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: [DO NOT MERGE] q1900m
by Angel Pons (Code Review) Sept. 8, 2023

Sept. 8, 2023

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39658 ) Change subject: [DO NOT MERGE] q1900m ...................................................................... [DO NOT MERGE] q1900m Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asrock/q1900m/Kconfig A src/mainboard/asrock/q1900m/Kconfig.name A src/mainboard/asrock/q1900m/Makefile.inc A src/mainboard/asrock/q1900m/acpi/dptf.asl A src/mainboard/asrock/q1900m/acpi/ec.asl A src/mainboard/asrock/q1900m/acpi/superio.asl A src/mainboard/asrock/q1900m/acpi_tables.c A src/mainboard/asrock/q1900m/board_info.txt A src/mainboard/asrock/q1900m/devicetree.cb A src/mainboard/asrock/q1900m/dsdt.asl A src/mainboard/asrock/q1900m/fadt.c A src/mainboard/asrock/q1900m/gpio.c A src/mainboard/asrock/q1900m/irqroute.c A src/mainboard/asrock/q1900m/irqroute.h A src/mainboard/asrock/q1900m/mainboard.c A src/mainboard/asrock/q1900m/romstage.c A src/mainboard/asrock/q1900m/spd/spd0.spd.hex A src/mainboard/asrock/q1900m/spd/spd1.spd.hex 18 files changed, 841 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39658/1 diff --git a/src/mainboard/asrock/q1900m/Kconfig b/src/mainboard/asrock/q1900m/Kconfig new file mode 100644 index 0000000..79db93c --- /dev/null +++ b/src/mainboard/asrock/q1900m/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +if BOARD_ASROCK_Q1900M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select MAINBOARD_HAS_CHROMEOS + +config MAINBOARD_DIR + string + default "asrock/q1900m" + +config MAINBOARD_PART_NUMBER + string + default "Q1900M" + +config VGA_BIOS_FILE + string + default "pci8086,0f31.rom" + +endif diff --git a/src/mainboard/asrock/q1900m/Kconfig.name b/src/mainboard/asrock/q1900m/Kconfig.name new file mode 100644 index 0000000..1056ef9 --- /dev/null +++ b/src/mainboard/asrock/q1900m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_Q1900M + bool "Q1900M" diff --git a/src/mainboard/asrock/q1900m/Makefile.inc b/src/mainboard/asrock/q1900m/Makefile.inc new file mode 100644 index 0000000..8947e78 --- /dev/null +++ b/src/mainboard/asrock/q1900m/Makefile.inc @@ -0,0 +1,24 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = spd0 +SPD_SOURCES += spd1 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd + +ramstage-y += irqroute.c +ramstage-y += gpio.c diff --git a/src/mainboard/asrock/q1900m/acpi/dptf.asl b/src/mainboard/asrock/q1900m/acpi/dptf.asl new file mode 100644 index 0000000..bdc396b --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi/dptf.asl @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 80 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 80 + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, // Revision + Package () { // Power Limit 1 + 0, // PowerLimitIndex, 0 for Power Limit 1 + 1600, // PowerLimitMinimum + 6200, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 200 // StepSize + }, + Package () { // Power Limit 2 + 1, // PowerLimitIndex, 1 for Power Limit 2 + 8000, // PowerLimitMinimum + 8000, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 1000 // StepSize + } +}) + +/* Include SoC DPTF */ +#include <soc/intel/baytrail/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asrock/q1900m/acpi/ec.asl b/src/mainboard/asrock/q1900m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi/ec.asl diff --git a/src/mainboard/asrock/q1900m/acpi/superio.asl b/src/mainboard/asrock/q1900m/acpi/superio.asl new file mode 100644 index 0000000..e224349 --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi/superio.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/q1900m/acpi_tables.c b/src/mainboard/asrock/q1900m/acpi_tables.c new file mode 100644 index 0000000..c8a95c6 --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi_tables.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <types.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include <soc/iomap.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/asrock/q1900m/board_info.txt b/src/mainboard/asrock/q1900m/board_info.txt new file mode 100644 index 0000000..d3e1fc2 --- /dev/null +++ b/src/mainboard/asrock/q1900m/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Q1900M/ +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: possible +Flashrom support: y diff --git a/src/mainboard/asrock/q1900m/devicetree.cb b/src/mainboard/asrock/q1900m/devicetree.cb new file mode 100644 index 0000000..3085696 --- /dev/null +++ b/src/mainboard/asrock/q1900m/devicetree.cb @@ -0,0 +1,118 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "1" + register "ide_legacy_combined" = "0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0" + register "usb3_port_disable_mask" = "0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuning for Q1900M board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + #register "gpu_pipea_port_select" = "2" # DP_C + #register "gpu_pipea_power_cycle_delay" = "6" # 600ms + #register "gpu_pipea_power_on_delay" = "5000" # 500ms + #register "gpu_pipea_light_on_delay" = "70" # 7ms + #register "gpu_pipea_power_off_delay" = "500" # 50ms + #register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 off end # LPE + device pci 17.0 off end # MMC + device pci 18.0 off end # SIO_DMA1 + device pci 18.1 off end # I2C1 + device pci 18.2 off end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.3 on end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 off end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on # LPC Bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 off # Keyboard + #io 0x60 = 0x60 + #io 0x62 = 0x64 + #irq 0x70 = 1 + #irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0xe3 = 0x14 + irq 0xe6 = 0x4c + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + end + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-Pull or Open-drain + device pnp 2e.14 off end # SVID + device pnp 2e.16 on end # Deep Sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/asrock/q1900m/dsdt.asl b/src/mainboard/asrock/q1900m/dsdt.asl new file mode 100644 index 0000000..2e9de53 --- /dev/null +++ b/src/mainboard/asrock/q1900m/dsdt.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/baytrail/acpi/platform.asl> + #include <soc/intel/baytrail/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + } + + /* Dynamic Platform Thermal Framework */ + //#include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asrock/q1900m/fadt.c b/src/mainboard/asrock/q1900m/fadt.c new file mode 100644 index 0000000..d07d157 --- /dev/null +++ b/src/mainboard/asrock/q1900m/fadt.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <string.h> +#include <soc/acpi.h> +#include <version.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = get_acpi_table_revision(FADT); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->reserved = 0; + fadt->preferred_pm_profile = PM_DESKTOP; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/asrock/q1900m/gpio.c b/src/mainboard/asrock/q1900m/gpio.c new file mode 100644 index 0000000..c1dfef9 --- /dev/null +++ b/src/mainboard/asrock/q1900m/gpio.c @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * Note that Pad Number differs from GPIO Number. The pads list is in the BWG Vol2 Rev1p0. + * Chapter 35: GPIO Handling + * Table 35-2: Pad Number Mapping According to Pad Name + */ + + #define GPIO_INNC GPIO_INPUT_NOPU + #define GPIO_FS GPIO_INPUT_NOPU + +/* DDI0 = HDMI; DDI1 = DVI; no backlight used on either pipe */ + +/* NCORE GPIOs */ /* Map [15..26] to MCSI_GPIO[00..11] */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* [00] - HDMI DDC Detect */ // DDI0_HPD + GPIO_FUNC2, /* [01] - HDMI DDC Data */ // DDI0_DDCDATA + GPIO_FUNC2, /* [02] - HDMI DDC Clock */ // DDI0_DDCCLK + GPIO_INNC, /* [03] - No Connect */ // DDI0_VDDEN + GPIO_INNC, /* [04] - No Connect */ // DDI0_BKLTEN + GPIO_INNC, /* [05] - No Connect */ // DDI0_BKLTCTL + GPIO_FUNC2, /* [06] - DVI DDC Detect */ // DDI1_HPD + GPIO_FUNC2, /* [07] - DVI DDC Data */ // DDI1_DDCDATA + GPIO_FUNC2, /* [08] - DVI DDC Clock */ // DDI1_DDCCLK + GPIO_INNC, /* [09] - No Connect */ // DDI1_VDDEN + GPIO_INNC, /* [10] - No Connect */ // DDI1_BKLTEN + GPIO_INNC, /* [11] - No Connect */ // DDI1_BKLTCTL + GPIO_INNC, /* [12] - No Connect */ // RESERVED + GPIO_FS, /* [13] - No Connect */ // RESERVED (removed in EDS_Rev1p5) + GPIO_INNC, /* [14] - No Connect */ // RESERVED + GPIO_INNC, /* [15] - No Connect */ // OBSFN_C0 (XDP stuff) + GPIO_INNC, /* [16] - No Connect */ // XDP stuff + GPIO_INNC, /* [17] - No Connect */ // XDP stuff + GPIO_INNC, /* [18] - No Connect */ // XDP stuff + GPIO_INNC, /* [19] - No Connect */ // XDP stuff + GPIO_INNC, /* [20] - No Connect */ // XDP stuff + GPIO_INNC, /* [21] - No Connect */ // XDP stuff + GPIO_INNC, /* [22] - No Connect */ // XDP stuff + GPIO_INNC, /* [23] - No Connect */ // XDP stuff + GPIO_INNC, /* [24] - No Connect */ // Still camera 0 reset + GPIO_INNC, /* [25] - No Connect */ // Still camera 1 reset + GPIO_INNC, /* [26] - No Connect */ // Video camera reset + GPIO_END +}; + +/* SCORE GPIOs (_XX) */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FS, /* [000] - SATA_GP0 */ // SHOULD BE A PULL-UP, BUT READS LOW! + GPIO_FS, /* [001] - SATA_GP1 */ // EXTERNAL PULL UP + GPIO_FUNC1, /* [002] - SATA_LED_B */ // HDD LED + GPIO_FUNC1, /* [003] - PCIE_CLKREQ_0 */ // CLKREQ# FOR TOP PCIE X1 + GPIO_FUNC1, /* [004] - PCIE_CLKREQ_1 */ // CLKREQ# FOR PCIE X4 + GPIO_FUNC1, /* [005] - PCIE_CLKREQ_2 */ // CLKREQ# FOR BOTTOM PCIE X1 + GPIO_FUNC1, /* [006] - PCIE_CLKREQ_3 */ // CLKREQ# FOR LAN + GPIO_INNC, /* [007] - SD3_WP */ // NO CONNECT + GPIO_FUNC2, /* [008] - No Connect */ // HDA RESET + GPIO_FUNC2, /* [009] - No Connect */ // HDA SYNC + GPIO_FUNC2, /* [010] - No Connect */ // HDA CLK + GPIO_FUNC2, /* [011] - No Connect */ // HDA SDO + GPIO_FUNC2, /* [012] - No Connect */ // HDA SDI0 + GPIO_INNC, /* [013] - No Connect */ // NO CONNECT + GPIO_FS, /* [014] - No Connect */ // OTE_GATE1 !!! + GPIO_FS, /* [015] - No Connect */ // OTE_GATE2 !!! + GPIO_INNC, /* [016] - No Connect */ // NO CONNECT + GPIO_INNC, /* [017] - No Connect */ // NO CONNECT + GPIO_INNC, /* [018] - No Connect */ // NO CONNECT + GPIO_INNC, /* [019] - No Connect */ // NO CONNECT + GPIO_INNC, /* [020] - No Connect */ // NO CONNECT + GPIO_INNC, /* [021] - No Connect */ // NO CONNECT + GPIO_INNC, /* [022] - No Connect */ // NO CONNECT + GPIO_INNC, /* [023] - No Connect */ // NO CONNECT + GPIO_INNC, /* [024] - No Connect */ // NO CONNECT + GPIO_INNC, /* [025] - No Connect */ // NO CONNECT + GPIO_INNC, /* [026] - No Connect */ // NO CONNECT + GPIO_INNC, /* [027] - No Connect */ // NO CONNECT + GPIO_INNC, /* [028] - No Connect */ // NO CONNECT + GPIO_INNC, /* [029] - No Connect */ // NO CONNECT + GPIO_INNC, /* [030] - No Connect */ // NO CONNECT + GPIO_INNC, /* [031] - No Connect */ // NO CONNECT + GPIO_INNC, /* [032] - No Connect */ // NO CONNECT + GPIO_INNC, /* [033] - SD3_CLK */ // NO CONNECT + GPIO_INNC, /* [034] - SD3_D0 */ // NO CONNECT + GPIO_INNC, /* [035] - SD3_D1 */ // NO CONNECT + GPIO_INNC, /* [036] - SD3_D2 */ // NO CONNECT + GPIO_INNC, /* [037] - SD3_D3 */ // NO CONNECT + GPIO_INNC, /* [038] - SD3_CD# */ // NO CONNECT + GPIO_INNC, /* [039] - SD3_CMD */ // NO CONNECT + GPIO_INNC, /* [040] - No Connect */ // NO CONNECT + GPIO_INNC, /* [041] - SD3_PWREN */ // NO CONNECT + GPIO_FUNC1, /* [042] - No Connect */ // LAD0 + GPIO_FUNC1, /* [043] - No Connect */ // LAD1 + GPIO_FUNC1, /* [044] - No Connect */ // LAD2 + GPIO_FUNC1, /* [045] - No Connect */ // LAD3 + GPIO_FUNC1, /* [046] - No Connect */ // LFRAME# + GPIO_FUNC1, /* [047] - No Connect */ // LPC CLOCK (TPM) + GPIO_FUNC1, /* [048] - No Connect */ // LPC CLOCK (SIO) + GPIO_FUNC1, /* [049] - No Connect */ // LPC CLKRUN# + GPIO_FUNC1, /* [050] - No Connect */ // SERIRQ# + GPIO_FUNC1, /* [051] - PCU_SMB_DATA */ // SMBUS DATA + GPIO_FUNC1, /* [052] - PCU_SMB_CLK */ // SMBUS CLK + GPIO_FUNC1, /* [053] - PCU_SMB_ALERT */ // SMBUS ALERT# (UNUSED? STRAP?) + GPIO_FUNC1, /* [054] - ILB_8254_SPKR */ // SPEAKER + GPIO_FS, /* [055] - No Connect */ // FRONT PANEL PRESENCE (PIN 4) + GPIO_FS, /* [056] - _56 */ // TOP SWAP (DEFEATURE) + GPIO_INNC, /* [057] - PCU_UART3_TXD */ // NO CONNECT + GPIO_INNC, /* [058] - No Connect */ // NO CONNECT + GPIO_INNC, /* [059] - No Connect */ // NO CONNECT + GPIO_INNC, /* [060] - No Connect */ // NO CONNECT + GPIO_FS, /* [061] - PCU_UART3_RXD */ // PCIE3_SEL !!! + GPIO_INNC, /* [062] - LPE_I2S_CLK */ // NO CONNECT + GPIO_FS, /* [063] - LPE_I2S_FRM */ // BOOT SEL STRAP + GPIO_INNC, /* [064] - LPE_I2S_DATIN */ // NO CONNECT + GPIO_FS, /* [065] - LPE_I2S_DATOUT */ // IFD OVERRIDE STRAP + GPIO_INNC, /* [066] - SOC_SIO_SPI_CS1 */ // NO CONNECT + GPIO_INNC, /* [067] - SOC_SIO_SPI_MISO */ // NO CONNECT + GPIO_INNC, /* [068] - SOC_SIO_SPI_MOSI */ // NO CONNECT + GPIO_INNC, /* [069] - SOC_SIO_SPI_CLK */ // NO CONNECT + GPIO_INNC, /* [070] - SIO_UART1_RXD */ // NO CONNECT + GPIO_INNC, /* [071] - SIO_UART1_TXD */ // NO CONNECT + GPIO_INNC, /* [072] - No Connect */ // NO CONNECT + GPIO_INNC, /* [073] - No Connect */ // NO CONNECT + GPIO_INNC, /* [074] - No Connect */ // NO CONNECT + GPIO_INNC, /* [075] - No Connect */ // NO CONNECT + GPIO_INNC, /* [076] - No Connect */ // NO CONNECT + GPIO_INNC, /* [077] - No Connect */ // NO CONNECT + GPIO_INNC, /* [078] - No Connect */ // NO CONNECT + GPIO_INNC, /* [079] - No Connect */ // NO CONNECT + GPIO_INNC, /* [080] - No Connect */ // NO CONNECT + GPIO_INNC, /* [081] - No Connect */ // NO CONNECT + GPIO_INNC, /* [082] - No Connect */ // NO CONNECT + GPIO_INNC, /* [083] - No Connect */ // NO CONNECT + GPIO_INNC, /* [084] - No Connect */ // NO CONNECT + GPIO_INNC, /* [085] - No Connect */ // NO CONNECT + GPIO_INNC, /* [086] - No Connect */ // NO CONNECT + GPIO_INNC, /* [087] - No Connect */ // NO CONNECT + GPIO_INNC, /* [088] - No Connect */ // NO CONNECT + GPIO_INNC, /* [089] - No Connect */ // NO CONNECT + GPIO_INNC, /* [090] - EXP_I2C_SDA */ // NO CONNECT + GPIO_INNC, /* [091] - EXP_I2C_SCL */ // NO CONNECT + GPIO_FS, /* [092] - 0R GND? */ // PCIE1_SEL !!! + GPIO_FS, /* [093] - 0R GND? */ // PCIE2_SEL !!! + GPIO_INNC, /* [094] - SOC_PWM0 */ // NO CONNECT + GPIO_INNC, /* [095] - SOC_PWM1 */ // NO CONNECT + GPIO_FUNC1, /* [096] - No Connect */ // PMC PLT CLK0 + GPIO_FUNC1, /* [097] - No Connect */ // PMC PLT CLK1 + GPIO_INNC, /* [098] - No Connect */ // NO CONNECT + GPIO_INNC, /* [099] - No Connect */ // NO CONNECT + GPIO_INNC, /* [100] - No Connect */ // NO CONNECT + GPIO_INNC, /* [101] - No Connect */ // NO CONNECT + GPIO_END +}; + +/* SSUS GPIOs () */ +static const struct soc_gpio_map gp_ssus_gpio_map[] = { + GPIO_FS, /* [00] - No Connect */ // RINGIN# !!! + GPIO_INNC, /* [01] - PMC_WAKE_PCIE[1] */ // NO CONNECT + GPIO_INNC, /* [02] - PMC_WAKE_PCIE[2] */ // PME# (SIO) + GPIO_INNC, /* [03] - PMC_WAKE_PCIE[3] */ // SMI# (SIO) + GPIO_INNC, /* [04] - No Connect */ // NO CONNECT + GPIO_INNC, /* [05] - No Connect */ // NO CONNECT + GPIO_INNC, /* [06] - No Connect */ // NO CONNECT + GPIO_INNC, /* [07] - No Connect */ // NO CONNECT + GPIO_INNC, /* [08] - No Connect */ // NO CONNECT + GPIO_INNC, /* [09] - No Connect */ // NO CONNECT + GPIO_INNC, /* [10] - _10_UNLOCK */ // NO CONNECT + GPIO_FUNC0, /* [11] - SUSPWRDNACK */ // SUSPWRDNACK + GPIO_FS, /* [12] - No Connect */ // NO CONNECT ??? + GPIO_INNC, /* [13] - No Connect */ // NO CONNECT + GPIO_INNC, /* [14] - 14_J20 */ // NO CONNECT + GPIO_FUNC0, /* [15] - PMC_WAKE_PCIE[0] */ // SOC PCIE WAKE# + GPIO_FUNC0, /* [16] - No Connect */ // POWER BUTTON (SIO) + GPIO_INNC, /* [17] - No Connect */ // NO CONNECT + GPIO_FUNC0, /* [18] - T360 */ // SUS STAT# + GPIO_FUNC0, /* [19] - SOC_USB_HOST_OC0 */ // USB OC0# + GPIO_FUNC0, /* [20] - SOC_USB_HOST_OC1 */ // USB OC1# + GPIO_INNC, /* [21] - SOC_SPI_CS1B */ // NO CONNECT + GPIO_OUT_LOW, /* [22] - No Connect */ // MEMORY VR VCCM OV1 !!! + GPIO_FS, /* [23] - No Connect */ // MEMORY VR VCCM OV2 !!! + GPIO_INNC, /* [24] - No Connect */ // NO CONNECT + GPIO_INNC, /* [25] - No Connect */ // NO CONNECT + GPIO_INNC, /* [26] - No Connect */ // NO CONNECT + GPIO_INNC, /* [27] - SW450-1 */ // MBREV0 + GPIO_INNC, /* [28] - SW450-2 */ // MBREV1 + GPIO_INNC, /* [29] - SW450-3 */ // MBREV2 + GPIO_INNC, /* [30] - SW450-4 */ // MBREV3 + GPIO_INNC, /* [31] - No Connect */ // NO CONNECT + GPIO_INNC, /* [32] - No Connect */ // NO CONNECT + GPIO_INNC, /* [33] - No Connect */ // NO CONNECT + GPIO_INNC, /* [34] - No Connect */ // NO CONNECT + GPIO_INNC, /* [35] - No Connect */ // NO CONNECT + GPIO_INNC, /* [36] - No Connect */ // NO CONNECT + GPIO_INNC, /* [37] - No Connect */ // NO CONNECT + GPIO_INNC, /* [38] - No Connect */ // NO CONNECT + GPIO_INNC, /* [39] - No Connect */ // NO CONNECT + GPIO_INNC, /* [40] - No Connect */ // NO CONNECT + GPIO_INNC, /* [41] - No Connect */ // NO CONNECT + GPIO_INNC, /* [42] - No Connect */ // NO CONNECT + GPIO_INNC, /* [43] - No Connect */ // NO CONNECT + GPIO_END +}; + +/* +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +};*/ + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gp_ssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, + //.core_dirq = &core_dedicated_irq, + //.sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/asrock/q1900m/irqroute.c b/src/mainboard/asrock/q1900m/irqroute.c new file mode 100644 index 0000000..df43ee9 --- /dev/null +++ b/src/mainboard/asrock/q1900m/irqroute.c @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/asrock/q1900m/irqroute.h b/src/mainboard/asrock/q1900m/irqroute.h new file mode 100644 index 0000000..3944c9de --- /dev/null +++ b/src/mainboard/asrock/q1900m/irqroute.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +//#define TPAD_IRQ_OFFSET 0 +//#define TOUCH_IRQ_OFFSET 1 +//#define I8042_IRQ_OFFSET 2 +//#define ALS_IRQ_OFFSET 3 +/* Corresponding SCORE GPIO pins */ +//#define TPAD_IRQ_GPIO 55 +//#define TOUCH_IRQ_GPIO 72 +//#define I8042_IRQ_GPIO 101 +//#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +//#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +//#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/asrock/q1900m/mainboard.c b/src/mainboard/asrock/q1900m/mainboard.c new file mode 100644 index 0000000..09d807d --- /dev/null +++ b/src/mainboard/asrock/q1900m/mainboard.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG(VGA_ROM_RUN) +#include <x86emu/x86emu.h> +#endif +#include <arch/acpi.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <smbios.h> +//#include <variant/onboard.h> +#include <soc/gpio.h> +#include <bootstate.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void mainboard_suspend_resume(void) +{ +} + +#if CONFIG(VGA_ROM_RUN) +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* + * bit 4 = CRT2 + * bit 5 = TV2 + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0008; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +//static void mainboard_init(struct device *dev) {} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + //dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +#if CONFIG(VGA_ROM_RUN) + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asrock/q1900m/romstage.c b/src/mainboard/asrock/q1900m/romstage.c new file mode 100644 index 0000000..7a4d5a6 --- /dev/null +++ b/src/mainboard/asrock/q1900m/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <soc/mrc_wrapper.h> +#include <soc/romstage.h> + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + /* I'm a bit desperate. */ + printk(BIOS_EMERG, "AAAAAAAA WE LIVEEEEEEEEEE\n"); + void *spd; + size_t spd_fsize; + + struct mrc_params mp = { + .mainboard = { + .dram_type = DRAM_DDR3, + .dram_info_location = DRAM_INFO_SPD_MEM, + .weaker_odt_settings = 1, + .dram_is_slotted = 1, + .spd_addrs = {0xf0, 0x00} + }, + }; + + spd = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); + + if (!spd) + die("SPD data not found."); + + mp.mainboard.dram_data[0] = spd; + //mp.mainboard.dram_data[1] = spd; + + rp->mrc_params = &mp; + romstage_common(rp); +} diff --git a/src/mainboard/asrock/q1900m/spd/spd0.spd.hex b/src/mainboard/asrock/q1900m/spd/spd0.spd.hex new file mode 100644 index 0000000..8ced790 --- /dev/null +++ b/src/mainboard/asrock/q1900m/spd/spd0.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6CFR6A-PBA +92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/asrock/q1900m/spd/spd1.spd.hex b/src/mainboard/asrock/q1900m/spd/spd1.spd.hex new file mode 100644 index 0000000..8ced790 --- /dev/null +++ b/src/mainboard/asrock/q1900m/spd/spd1.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6CFR6A-PBA +92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -- To view, visit https://review.coreboot.org/c/coreboot/+/39658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Gerrit-Change-Number: 39658 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

7 21

Change in coreboot[master]: LinuxBoot: fix `make clean` for linux builds
by Alexander Couzens (Code Review) Sept. 5, 2023

Sept. 5, 2023

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35438 ) Change subject: LinuxBoot: fix `make clean` for linux builds ...................................................................... LinuxBoot: fix `make clean` for linux builds The kernel_dir variable was never correct, because targets/linux.mk is using build directories based on the version e.g. kernel_4.19.73. Change-Id: I749200bd32d86303ae02903afd96f730ac36b307 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35438/1 diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 5840e8e..8b81c8a 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -14,7 +14,6 @@ ## project_dir=linuxboot -kernel_dir=$(project_dir)/kernel unexport $(COREBOOT_EXPORTS) @@ -65,7 +64,7 @@ linuxboot: kernel initramfs_compressed clean: - if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi + rm -rf $(project_dir)/kernel* rm -f $(project_dir)/u-root rm -f $(project_dir)/initramfs* -- To view, visit https://review.coreboot.org/c/coreboot/+/35438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I749200bd32d86303ae02903afd96f730ac36b307 Gerrit-Change-Number: 35438 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT
by Angel Pons (Code Review) Aug. 17, 2023

Aug. 17, 2023

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46960 ) Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ...................................................................... sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT). Newer Lynxpoint reference code shows LPT-H also uses these workarounds. Also, add the `ISWP` object (Name or Method) to test for WildcatPoint. Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/acpi/xhci.asl 2 files changed, 77 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46960/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a878dc2..134a7cf 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -27,6 +27,25 @@ , 5, HPTE, 1, // Address Enable } + + /* + * Check PCH type + * Return 1 if PCH is WildcatPoint + * Return 0 if PCH is LynxPoint + */ +#if CONFIG(INTEL_LYNXPOINT_LP) + Method (ISWP) + { + Local0 = \_SB.PCI0.LPCB.PDID & 0xfff0 + If (Local0 == 0x9cc0) { + Return (1) + } Else { + Return (0) + } + } +#else + Name (ISWP, 0) +#endif } // High Definition Audio (Azalia) 0:1b.0 diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index 2b3d433..203ee3b 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -17,6 +17,14 @@ Offset (0x10), , 16, XMEM, 16, // MEM_BASE + Offset (0x40), + , 11, + SWAI, 1, + , 20, + Offset (0x44), + , 12, + SAIP, 2, + , 18, Offset (0x74), D0D3, 2, , 6, @@ -214,25 +222,39 @@ } #if CONFIG(INTEL_LYNXPOINT_LP) - // Clear PCI 0xB0[14:13] - ^MB13 = 0 - ^MB14 = 0 + If (!\ISWP()) { + // Clear PCI 0xB0[14:13] + ^MB13 = 0 + ^MB14 = 0 - // Clear MMIO 0x816C[14,2] - CLK0 = 0 - CLK1 = 0 + // Clear MMIO 0x816C[14,2] + CLK0 = 0 + CLK1 = 0 - // Set MMIO 0x8154[31] - CLK2 = 1 + // Set MMIO 0x8154[31] + CLK2 = 1 - // Handle per-port reset if needed - LPS0 () + // Handle per-port reset if needed + LPS0 () - // Set MMIO 0x80e0[15] - AX15 = 1 + // Set MMIO 0x80e0[15] + AX15 = 1 + + // Clear PCI CFG offset 0x40[11] + ^SWAI = 0 + + // Clear PCI CFG offset 0x44[13:12] + ^SAIP = 0 + } #else // Set MMIO 0x8154[31] CLK2 = 1 + + // Clear PCI CFG offset 0x40[11] + ^SWAI = 0 + + // Clear PCI CFG offset 0x44[13:12] + ^SAIP = 0 #endif Return () @@ -273,22 +295,36 @@ } #if CONFIG(INTEL_LYNXPOINT_LP) - // Set PCI 0xB0[14:13] - ^MB13 = 1 - ^MB14 = 1 + If (!\ISWP()) { + // Set PCI 0xB0[14:13] + ^MB13 = 1 + ^MB14 = 1 - // Set MMIO 0x816C[14,2] - CLK0 = 1 - CLK1 = 1 + // Set MMIO 0x816C[14,2] + CLK0 = 1 + CLK1 = 1 - // Clear MMIO 0x8154[31] - CLK2 = 0 + // Clear MMIO 0x8154[31] + CLK2 = 0 - // Clear MMIO 0x80e0[15] - AX15 = 0 + // Clear MMIO 0x80e0[15] + AX15 = 0 + + // Set PCI CFG offset 0x40[11] + ^SWAI = 1 + + // Set PCI CFG offset 0x44[13:12] + ^SAIP = 1 + } #else // Clear MMIO 0x8154[31] CLK2 = 0 + + // Set PCI CFG offset 0x40[11] + ^SWAI = 1 + + // Set PCI CFG offset 0x44[13:12] + ^SAIP = 1 #endif // Put device in D3 -- To view, visit https://review.coreboot.org/c/coreboot/+/46960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9 Gerrit-Change-Number: 46960 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: abuild: Fix board variant handling
by Keith Hui (Code Review) Aug. 17, 2023

Aug. 17, 2023

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41918 ) Change subject: abuild: Fix board variant handling ...................................................................... abuild: Fix board variant handling Problem: Me: $ util/abuild/abuild -t asus/p2b -b p2b-ls abuild: No such target: asus/p2b, variant: p2b-ls Cause: We identify boards and variants using path names in tree, so I type in the test command above. abuild identifies all board variants the Kconfig way, in all caps and all underscores. Result: Expectation gap and abuild can't find anything where we expect it to. All variants with a hyphen in their names are affected. Fix: Add a substitution to replace hyphens with underscores. Test: I get my abuild with the command above, even a variant-specific test config works. Change-Id: I10d5b471dac41c50a85c4a309ec561b02687bb9a Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/41918/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index b6a6bfe..ca8a0cf 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -165,7 +165,7 @@ local targets local VARIANT_UC - VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]') + VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]' | tr '-' '_') targets=$(get_mainboards "$1") if [ -n "$targets" ]; then -- To view, visit https://review.coreboot.org/c/coreboot/+/41918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10d5b471dac41c50a85c4a309ec561b02687bb9a Gerrit-Change-Number: 41918 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: sb/intel/lynxpoint: Use Broadwell SerialIO implementation
by Angel Pons (Code Review) Aug. 15, 2023

Aug. 15, 2023

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46969 ) Change subject: sb/intel/lynxpoint: Use Broadwell SerialIO implementation ...................................................................... sb/intel/lynxpoint: Use Broadwell SerialIO implementation Add power state control methods for more devices using helper methods. Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 96 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46969/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 845949c..0e246f7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -16,6 +16,28 @@ External (\S6EN) External (\S7EN) +// Put SerialIO device in D0 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD0, 1, Serialized) +{ + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + +// Put SerialIO device in D3 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD3, 1, Serialized) +{ + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + // Serial IO Resource Consumption for BAR1 Device (SIOR) { @@ -193,32 +215,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -273,32 +283,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -337,6 +335,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SPI1) @@ -386,6 +400,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR0) @@ -435,6 +465,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR1) @@ -472,6 +518,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SDIO) -- To view, visit https://review.coreboot.org/c/coreboot/+/46969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Gerrit-Change-Number: 46969 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/asus/p2b: Add ACPI support for p3b-f
by Keith Hui (Code Review) Aug. 14, 2023

Aug. 14, 2023

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41098 ) Change subject: mb/asus/p2b: Add ACPI support for p3b-f ...................................................................... mb/asus/p2b: Add ACPI support for p3b-f Finally! Power button works to turn board on and off. ACPI hooks to manipulate power and message LEDs work. Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/Kconfig M src/mainboard/asus/p2b/dsdt.asl A src/mainboard/asus/p2b/suspend.asl A src/mainboard/asus/p2b/variants/p3b-f/suspend.asl 4 files changed, 393 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/41098/1 diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 1ad25e1..45018d6 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -29,7 +29,7 @@ select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F - select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS + select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS config MAX_CPUS diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 88be9ba..623b575 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -53,6 +53,7 @@ { Offset (0x03), TO12, 1, /* Device trap 12 */ +#if !CONFIG(BOARD_ASUS_P3B_F) Offset (0x08), FANM, 1, /* GPO0, meant for fan */ Offset (0x09), @@ -61,33 +62,25 @@ , 2, , 16, MSG0, 1 /* GPO30, message LED */ +#endif } - /* Prepare To Sleep, Arg0 is target S-state */ - Method (\_PTS, 1, NotSerialized) + OperationRegion (ECOS, SystemIO, 0x72, 0x02) + Field (ECOS, ByteAcc, NoLock, Preserve) { - /* Disable fan, blink power LED, if not turning off */ - If (LNotEqual (Arg0, 0x05)) - { - Store (Zero, FANM) - Store (Zero, PLED) - } - - /* Arms SMI for device 12 */ - Store (One, TO12) - /* Put out a POST code */ - Or (Arg0, 0xF0, P80) + CIDX, 8, + CDAT, 8 } - Method (\_WAK, 1, NotSerialized) + IndexField (CIDX, CDAT, ByteAcc, NoLock, Preserve) { - /* Re-enable fan, stop power led blinking */ - Store (One, FANM) - Store (One, PLED) - /* wake OK */ - Return(Package(0x02){0x00, 0x00}) + Offset (0x58), + RTCS, 8, + Offset (0x5F), + SUS3, 1, + , 3, + SLST, 4 } - /* Root of the bus hierarchy */ Scope (\_SB) { @@ -169,19 +162,9 @@ } } - /* ACPI Message */ - Scope (\_SI) - { - Method (_MSG, 1, NotSerialized) - { - If (LEqual (Arg0, Zero)) - { - Store (One, MSG0) - } - Else - { - Store (Zero, MSG0) - } - } - } +#if CONFIG(BOARD_ASUS_P3B_F) +#include "variants/p3b-f/suspend.asl" +#else +#include "suspend.asl" +#endif } diff --git a/src/mainboard/asus/p2b/suspend.asl b/src/mainboard/asus/p2b/suspend.asl new file mode 100644 index 0000000..5d2b540 --- /dev/null +++ b/src/mainboard/asus/p2b/suspend.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* ASUS P2B family board DSDT declarations (at top level) that does not apply to P3B-F */ + +/** + * ACPI message indicator. + * + * @param Arg0 Number of waiting messages + */ +Scope (\_SI) +{ + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + Store (One, MSG0) + } + Else + { + Store (Zero, MSG0) + } + } +} + +/** + * Prepare To Sleep. + * + * @param Arg0 Target ACPI S-state + */ +Method (\_PTS, 1, NotSerialized) +{ + /*SLST = Arg0*/ + /* Disable fan, blink power LED. S5 will turn them off too */ + If (Arg0 != 5) + { + FANM = 0 + PLED = 0 + } + + /* Arms SMI for device 12 */ + Store (One, TO12) + /* Put out a POST code */ + P80 = 0xF0 | Arg0 +} + +/** + * System wake. + * + * Returns a 2-DWORD package of: + * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal)) + * PSS: Actual S-state power supply entered if not 0 + * + * @param Arg0 Target ACPI S-state + * @return See description + */ +Method (\_WAK, 1, NotSerialized) +{ + /* Re-enable fan, stop power led blinking */ + FANM = 1 + PLED = 1 + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) +} + diff --git a/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl new file mode 100644 index 0000000..a84c700 --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include "southbridge/intel/i82371eb/i82371eb.h" + +/* ASUS P3B-F board specific (top level) DSDT declarations */ + +Name (PRW1, Package (0x04) +{ + Package (0x02) {0x09, 0x01}, + Package (0x02) {0x08, 0x01}, + Package (0x02) {0x0A, 0x01}, + Package (0x02) {0x0B, 0x01} +}) + +Name (PRW3, Package (0x04) +{ + Package (0x02) { 0x09, 0x03 }, + Package (0x02) { 0x08, 0x03 }, + Package (0x02) { 0x0A, 0x03 }, + Package (0x02) { 0x0B, 0x04 } +}) + +Name (PRWT, Package (0x04) +{ + 0x09, + 0x08, + 0x0A, + 0x0B +}) + +/* SPRW(n) = (SUS3==0) ? PRW1[n] : PRW3[n] */ +Method (SPRW, 1, NotSerialized) +{ + Store (Match (PRWT, MEQ, Arg0, MTR, 0x00, 0x00), Local0) + If (LEqual (SUS3, Zero)) + { + Return (DerefOf (Index (PRW1, Local0))) + } + Else + { + Return (DerefOf (Index (PRW3, Local0))) + } +} + +/* + * SMBus driver functions + * + * These functions communicate with the AS99127F ASIC on the P3B-F to handle hardware + * sequencing required around S3 suspend and resume. This chip is undocumented except it has + * W83781D-compatible hardware monitoring features, and seems to be responsible for hiding the + * flashchip from internal programming via flashrom. + * + * Note: The SMBus host controller interface is located in the southbridge. + */ + /* The SMBus controller hardware interface. Only byte accesses covered. */ + OperationRegion (SM00, SystemIO, SMBUS_IO_BASE, 7) + Field (SM00, ByteAcc, NoLock, Preserve) + { + HSTS, 8, + Offset (0x02), + CTLR, 8, + CMDR, 8, + ADDR, 8, + DAT0, 8, + DAT1, 8 + } + /* Wait for SMBus activity to complete, error or not */ + Method (SWFS, 0, NotSerialized) + { + And (HSTS, 0x06, Local0) + While (Local0 == 0) + { + Stall (1) + And (HSTS, 0x06, Local0) + } + } + + /** + * Writes a byte to a SMBus device. + * + * @param Arg0 SMBus device ID << 1 + * @param Arg1 Command (register index in our case) + * @param Arg2 Data + */ + Method (WBYT, 3, NotSerialized) + { + Store (Arg0, ADDR) + Store (Arg1, CMDR) + Store (Arg2, DAT0) + Store (0xFF, HSTS) + Store (0x48, CTLR) /* Start a byte data R/W access */ + SWFS () + } + + /** + * Reads a byte from a SMBus device. + * + * @param Arg0 SMBus device ID << 1 + * @param Arg1 Command (register index in our case) + * @return Data read + */ + Method (RBYT, 2, NotSerialized) + { + Or (Arg0, 0x01, ADDR) /* Set bit 0, this will be a read */ + Store (Arg1, CMDR) + Store (0xFF, HSTS) + Store (0x48, CTLR) /* Start a byte data R/W access */ + + /* If interrupted without success, restart and try again */ + And (HSTS, 0x02, Local0) + While (LEqual (Local0, Zero)) + { + Store (0xFF, HSTS) + Store (0x48, CTLR) + SWFS () + And (HSTS, 0x02, Local0) + } + + Return (DAT0) /* \DAT0 */ + } + + Method (SGOH, 2, NotSerialized) + { + /* SMBus address 0x48 */ + Store (0x90, Local0) + Store (RBYT (Local0, Arg0), Local1) + Or (Local1, Arg1, Local1) + WBYT (Local0, Arg0, Local1) + } + + Method (SGOL, 2, NotSerialized) + { + Store (0x90, Local0) + Store (RBYT (Local0, Arg0), Local1) + Not (Arg1, Local2) + And (Local1, Local2, Local1) + WBYT (Local0, Arg0, Local1) + } + + Method (FANC, 1, NotSerialized) + { + /* SMBus address 0x2d */ + WBYT (0x5A, 0x59, Arg0) + } + + Method (FANP, 1, NotSerialized) + { + WBYT (0x5A, 0x5A, Arg0) + } + + Method (EN18, 0, NotSerialized) + { + Store (0x5A, Local0) + Store (RBYT (Local0, 0x5F), Local1) + And (Local1, 0xDF, Local1) + WBYT (Local0, 0x5F, Local1) + } + + Method (DS18, 0, NotSerialized) + { + Store (0x5A, Local0) + Store (RBYT (Local0, 0x5F), Local1) + Or (Local1, 0x20, Local1) + WBYT (Local0, 0x5F, Local1) + } + +/** + * Prepare To Sleep, + * + * @param Arg0 Target ACPI S-state + */ + Method (\_PTS, 1, NotSerialized) + { + SLST = Arg0 + If (Arg0 == 0x01) + { + /* Disable BX.PMCR[CRst_En] */ + Store (\_SB.PCI0.NB.PMCR, Local0) + And (Local0, 0xFE, \_SB.PCI0.NB.PMCR) + + /* Isolate CPU_STP# and SUS_STAT1# signals at GENCFG register */ + Store (\_SB.PCI0.PX40.FXS1, Local0) + Or (Local0, 0x24, Local1) + Store (Local1, \_SB.PCI0.PX40.FXS1) + + \_SB.PCI0.ENTER_CONFIG_MODE (0x0A) + /* In SIO Dev A CR E4 = xxxx01xx (these bits are reserved per datasheet?) */ + And (\_SB.PCI0.KBWK, 0xF7, Local0) + Or (Local0, 0x04, \_SB.PCI0.KBWK) + \_SB.PCI0.EXIT_CONFIG_MODE () + } + + If (Arg0 == 0x03) + { + SGOH (0x83, 0x04) + SGOL (0x80, 0x04) + SGOH (0x80, 0x04) + SGOH (0x83, 0x01) + EN18 () + } + + /* Arms SMI for device 12 */ + TO12 = 1 + /* Put out a POST code */ + P80 = 0xF0 | Arg0 + } + +/** + * System wake. + * + * Returns a 2-DWORD package of: + * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal)) + * PSS: Actual S-state power supply entered if not 0 + * + * @param Arg0 Target ACPI S-state + * @return See description + */ + Method (\_WAK, 1, NotSerialized) // _WAK: Wake + { + DS18 () + Store (Zero, TO12) + /* Restore CPU_STP# and SUS_STAT1# signals */ + Store (\_SB.PCI0.PX40.FXS1, Local0) + And (Local0, 0xDB, \_SB.PCI0.PX40.FXS1) + SGOL (0x83, 0x01) + \_SB.PCI0.ENTER_CONFIG_MODE (0x0A) + And (\_SB.PCI0.MSWK, 0xFD, Local1) + Store (Local1, \_SB.PCI0.MSWK) + /* In SIO Dev A CR E4 = xxxx00xx */ + And (\_SB.PCI0.KBWK, 0xF3, Local0) + Store (Local0, \_SB.PCI0.KBWK) + \_SB.PCI0.EXIT_CONFIG_MODE () + /* Put out a POST code */ + P80 = 0xFF + Return(Package(0x02){0x00, 0x00}) + } + + Scope (\_GPE) + { + Method (_L0A, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Notify (\_SB.PCI0.SER2, 0x02) // Device Wake + Notify (\_SB.PCI0.SER3, 0x02) // Device Wake + } + + Method (_L09, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Notify (\_SB.PCI0, 0x02) // Device Wake + } + } + +Scope (\_SI) +{ + /** + * ACPI message indicator + * + * @param Arg0 Number of waiting messages + */ + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + SGOL (0x81, 0x02) + SGOH (0x81, 0x01) + SGOL (0x81, 0x01) + } + Else + { + SGOH (0x81, 0x02) + SGOL (0x81, 0x02) + } + } + + + /** + * System Status. OS calls to set system status indicator. + * Arg0: + * 0 = Indicator off + * 1 = Working + * 2 = Waking + * 3 = Sleeping: States S1, S2, S3 + * 4 = Sleeping with context saved to non-volatile storage. + * + * @param Arg0 System status indicator + */ + Method (_SST, 1, NotSerialized) // _SST: System Status + { + If (LEqual (Arg0, 0x00)) + { + SGOH (0x80, 0x40) + } + ElseIf (LEqual (Arg0, 0x03)) + { + SGOL (0x80, 0x40) + SGOL (0x80, 0x80) + FANC (0x81) + FANP (0x81) + } + Else + { + SGOL (0x80, 0x40) + SGOH (0x80, 0x80) + FANC (0x8F) + FANP (0x8F) + } + } +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/41098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea Gerrit-Change-Number: 41098 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Clarify RAM overclock options
by Angel Pons (Code Review) Aug. 13, 2023

Aug. 13, 2023

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47429 ) Change subject: nb/intel/sandybridge: Clarify RAM overclock options ...................................................................... nb/intel/sandybridge: Clarify RAM overclock options Rewrite them to more accurately describe what they are about. Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/Kconfig 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47429/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..b4834cd 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -44,19 +44,19 @@ System Agent/MRC.bin. You should answer Y. config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES - bool "Ignore vendor programmed fuses that limit max. DRAM frequency" + bool "[OVERCLOCKING] Ignore CAPID fuses that limit max. DRAM frequency" default n depends on USE_NATIVE_RAMINIT help - Ignore the mainboard's vendor programmed fuses that might limit the - maximum DRAM frequency. By selecting this option the fuses will be - ignored and the only limits on DRAM frequency are set by RAM's SPD and - hard fuses in southbridge's clockgen. - Disabled by default as it might causes system instability. + Ignore the CAPID fuses and devicetree settings that might limit the + maximum DRAM frequency on overclocking-capable parts. By selecting + this option, the fuse values will be ignored and the only limits on + DRAM frequency are determined by SPD values and hard limits in the + northbridge's MPLL. Disabled by default as it can cause instability. Handle with care! config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS - bool "Ignore XMP profile max DIMMs per channel" + bool "[OVERCLOCKING] Ignore XMP profile max DIMMs per channel" default n depends on USE_NATIVE_RAMINIT help -- To view, visit https://review.coreboot.org/c/coreboot/+/47429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0 Gerrit-Change-Number: 47429 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: bootsplash: Allow bootsplash compression
by Michał Żygowski (Code Review) Aug. 10, 2023

Aug. 10, 2023

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42806 ) Change subject: bootsplash: Allow bootsplash compression ...................................................................... bootsplash: Allow bootsplash compression TEST=include BMP bootsplash and select the compression, boot Protectli FW6 with SeaBIOS and observe the bootsplash on the screen Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Id9abc6f72e3f82ce60cd06376cdc4f49f0198823 --- M Makefile.inc M src/Kconfig 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42806/1 diff --git a/Makefile.inc b/Makefile.inc index 7f61a5e..af931f7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1218,9 +1218,16 @@ revision-type := raw BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))) +ifeq ($(CONFIG_COMPRESS_BOOTSPLASH),) cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX) bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash$(BOOTSPLASH_SUFFIX)-type := bootsplash +else +cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX).lzma +bootsplash$(BOOTSPLASH_SUFFIX).lzma-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) +bootsplash$(BOOTSPLASH_SUFFIX).lzma-compression := $(CBFS_COMPRESS_FLAG) +bootsplash$(BOOTSPLASH_SUFFIX).lzma-type := bootsplash +endif # Ensure that no payload segment overlaps with memory regions used by ramstage # (not for x86 since it can relocate itself in that case) diff --git a/src/Kconfig b/src/Kconfig index 1b49e2b..ec3a274 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -315,6 +315,15 @@ This will only add the image to the ROM. To actually run it check options under 'Display' section. +config COMPRESS_BOOTSPLASH + bool "Compress bootsplash image" + depends on PAYLOAD_SEABIOS + help + The bootsplash image can be compressed with LZMA. This is especially + useful when BMP bootsplash is used and occupies too much SPI flash + space. The bootsplash CBFS file name will be compressed and suffixed + with lzma extension to indicate SeaBIOS to decompress it when loaded. + config BOOTSPLASH_FILE string "Bootsplash path and filename" depends on BOOTSPLASH_IMAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/42806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9abc6f72e3f82ce60cd06376cdc4f49f0198823 Gerrit-Change-Number: 42806 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/dptf: Generate ACPI identifiers only for enabled devices
by Karthik Ramasubramanian (Code Review) Aug. 8, 2023

Aug. 8, 2023

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47148 ) Change subject: drivers/intel/dptf: Generate ACPI identifiers only for enabled devices ...................................................................... drivers/intel/dptf: Generate ACPI identifiers only for enabled devices DPTF configuration can be applied based on firmware configuration. Hence generate ACPI identifiers only for enabled devices. BUG=b:170229672 TEST=Build and boot to OS in Drawlat and Drawcia. Ensure that the ACPI identifier is enabled only for enabled devices. Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/intel/dptf/dptf.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47148/1 diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 0f1cc9c..e0e2202 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -232,6 +232,9 @@ { struct drivers_intel_dptf_config *config = config_of(dev); + if (!dev->enabled) + return; + write_device_definitions(dev); write_policies(config); write_controls(config); -- To view, visit https://review.coreboot.org/c/coreboot/+/47148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0 Gerrit-Change-Number: 47148 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cpu/car: Enable caching before FSP-T
by Gaggery Tsai (Code Review) Aug. 7, 2023

Aug. 7, 2023

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38252 ) Change subject: soc/intel/common/block/cpu/car: Enable caching before FSP-T ...................................................................... soc/intel/common/block/cpu/car: Enable caching before FSP-T This patch is required for Boot Guard enabled platform. Enable caching before entering FSP-T. TEST=Stitch boot guard ACM with signed KM and BPM && Enable FSP-T and boot all the way to the OS && Read MSR 0x13a and esnure boot guard verified boot and measured boot are enabled. Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24 --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38252/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 091fc4a..fd22903 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -35,6 +35,12 @@ cache_as_ram: post_code(0x21) + /* Enable caching */ + mov %cr0, %eax + and $~(CR0_CD | CR0_NW), %eax + invd + mov %eax, %cr0 + /* find fsp in cbfs */ lea fsp_name, %esi mov $1f, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/38252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24 Gerrit-Change-Number: 38252 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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