coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/skylake: Add Kconfig option for LGA1151v2
by Nico Huber (Code Review) 02 May '21

02 May '21

Attention is currently required from: Felix Singer, Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52692 ) Change subject: soc/intel/skylake: Add Kconfig option for LGA1151v2 ...................................................................... Patch Set 10: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52692/comment/15615b64_678fd7e0 PS5, Line 15: mainboard > nit: move to previous line Gone, but now there's another overlong line... Commit Message: https://review.coreboot.org/c/coreboot/+/52692/comment/10d1ad1b_a76fa812 PS10, Line 12: As of the year 2021 it's common for motherboards with Z370, H310C or B365 PCHs, Please reflow the paragraph so it fits in one line (72 chars). File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/52692/comment/6c853b52_ada96e96 PS5, Line 21: Intel chipsets with LGA1151v2 socket (e.g., B365, H310C, Z370) support > Hmm, chipsets don't have a socket. How about: […] Done https://review.coreboot.org/c/coreboot/+/52692/comment/cf9ecc9d_debf7fbf PS5, Line 256: # SkylakeFsp is FSP 1.1 and therefore incompatible. > Because it's not only about FSP_HEADER_PATH, but also about FSP_FD_PATH Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 10 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 01 May 2021 16:42:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Timofey Komarov <happycorsair(a)yandex.ru> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Add Kconfig option for LGA1151v2
by Timofey Komarov (Code Review) 02 May '21

02 May '21

Attention is currently required from: Timofey Komarov, Felix Singer, Angel Pons, Patrick Rudolph. Hello Felix Singer, build bot (Jenkins), Nico Huber, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52692 to look at the new patch set (#11). Change subject: soc/intel/skylake: Add Kconfig option for LGA1151v2 ...................................................................... soc/intel/skylake: Add Kconfig option for LGA1151v2 Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults for the combination of a Union Point PCH with LGA1151v2. As of the year 2021 it's common for motherboards with Z370, H310C or B365 PCHs, which are meant to be paired with Coffee Lake CPUs. Intel provides AmberLakeFspBinPkg to support this combination, which implements Intel FSP External Architecture Specification v2.1. Details: 1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and SKYLAKE_SOC_PCH_H. 2) Add Amberlake FSP support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead of KabylakeFspBinPkg. 3) Enable Coffee Lake CPUs support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select MAINBOARD_SUPPORTS_COFFEELAKE_CPU. 4) Increase stack and heap size in CAR. If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1), update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values. 5) Update maximal number of supported CPUs. If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16. Signed-off-by: Timofey Komarov <happycorsair(a)yandex.ru> Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c --- M src/soc/intel/skylake/Kconfig 1 file changed, 26 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/52692/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 11 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Add Kconfig option for LGA1151v2
by Nico Huber (Code Review) 02 May '21

02 May '21

Attention is currently required from: Timofey Komarov, Felix Singer, Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52692 ) Change subject: soc/intel/skylake: Add Kconfig option for LGA1151v2 ...................................................................... Patch Set 10: Code-Review+2 (2 comments) File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/52692/comment/413c0b66_ebb05a54 PS9, Line 327: default y : : if SKYLAKE_SOC_PCH_H : : config MAINBOARD_SUPPORTS_KABYLAKE_CPU : bool "Board can contain Kaby Lake CPU" : default y if SOC_INTEL_KABYLAKE > These should `default n if SOC_INTEL_SKYLAKE_LGA1151_V2`. Done File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/52692/comment/b6af62e9_9777df38 PS10, Line 333: default y if (!SOC_INTEL_SKYLAKE_LGA1151_V2 && SOC_INTEL_KABYLAKE) Nit, no parentheses needed. And as there is no other default line, it could also just say default !SOC_INTEL_SKYLAKE_LGA1151_V2 && SOC_INTEL_KABYLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 10 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 01 May 2021 16:38:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Add Kconfig option for LGA1151v2
by Timofey Komarov (Code Review) 02 May '21

02 May '21

Attention is currently required from: Timofey Komarov, Felix Singer, Angel Pons, Patrick Rudolph. Hello Felix Singer, build bot (Jenkins), Nico Huber, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52692 to look at the new patch set (#10). Change subject: soc/intel/skylake: Add Kconfig option for LGA1151v2 ...................................................................... soc/intel/skylake: Add Kconfig option for LGA1151v2 Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults for the combination of a Union Point PCH with LGA1151v2. As of the year 2021 it's common for motherboards with Z370, H310C or B365 PCHs, which are meant to be paired with Coffee Lake CPUs. Intel provides AmberLakeFspBinPkg to support this combination, which implements Intel FSP External Architecture Specification v2.1. Details: 1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and SKYLAKE_SOC_PCH_H. 2) Add Amberlake FSP support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead of KabylakeFspBinPkg. 3) Enable Coffee Lake CPUs support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select MAINBOARD_SUPPORTS_COFFEELAKE_CPU. 4) Increase stack and heap size in CAR. If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1), update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values. 5) Update maximal number of supported CPUs. If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16. Signed-off-by: Timofey Komarov <happycorsair(a)yandex.ru> Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c --- M src/soc/intel/skylake/Kconfig 1 file changed, 26 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/52692/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 10 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Add Kconfig option for LGA1151v2
by Nico Huber (Code Review) 02 May '21

02 May '21

Attention is currently required from: Timofey Komarov, Felix Singer, Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52692 ) Change subject: soc/intel/skylake: Add Kconfig option for LGA1151v2 ...................................................................... Patch Set 9: Code-Review+2 (1 comment) File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/52692/comment/0d145f55_1d2692c4 PS9, Line 327: default y : : if SKYLAKE_SOC_PCH_H : : config MAINBOARD_SUPPORTS_KABYLAKE_CPU : bool "Board can contain Kaby Lake CPU" : default y if SOC_INTEL_KABYLAKE These should `default n if SOC_INTEL_SKYLAKE_LGA1151_V2`. -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 9 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 01 May 2021 16:13:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Add Kconfig option for LGA1151v2
by Timofey Komarov (Code Review) 02 May '21

02 May '21

Attention is currently required from: Felix Singer, Nico Huber, Angel Pons, Patrick Rudolph. Timofey Komarov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52692 ) Change subject: soc/intel/skylake: Add Kconfig option for LGA1151v2 ...................................................................... Patch Set 9: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52692/comment/c4d67bf7_7b851505 PS5, Line 7: to use > AFAIK, "allow to use" is correct. Google says it's much more popular, too: […] Ack https://review.coreboot.org/c/coreboot/+/52692/comment/4912400e_12c7a83c PS5, Line 7: to use > AFAIK, "allow to use" is correct. Google says it's much more popular, too: […] Ack File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/52692/comment/651a6a7e_647112a0 PS5, Line 95: default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU > Alternatively, keep it in this change, but adapt the commit message; […] Done https://review.coreboot.org/c/coreboot/+/52692/comment/99ed9287_25421fea PS5, Line 256: # SkylakeFsp is FSP 1.1 and therefore incompatible. > Why move the comment? Because it's not only about FSP_HEADER_PATH, but also about FSP_FD_PATH https://review.coreboot.org/c/coreboot/+/52692/comment/51c87d6c_85d9baf9 PS5, Line 259: if SOC_INTEL_SKYLAKE_LGA1151_V2 > No need to break the line, this fits in 96 characters Done https://review.coreboot.org/c/coreboot/+/52692/comment/5b430977_794dcf6e PS5, Line 264: if SOC_INTEL_SKYLAKE_LGA1151_V2 > No need to break the line, this fits in 96 characters Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 9 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 01 May 2021 16:02:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Add Kconfig option for LGA1151v2
by Timofey Komarov (Code Review) 02 May '21

02 May '21

Attention is currently required from: Timofey Komarov, Felix Singer, Nico Huber, Patrick Rudolph. Hello Felix Singer, build bot (Jenkins), Nico Huber, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52692 to look at the new patch set (#9). Change subject: soc/intel/skylake: Add Kconfig option for LGA1151v2 ...................................................................... soc/intel/skylake: Add Kconfig option for LGA1151v2 Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults for the combination of a Union Point PCH with LGA1151v2. As of the year 2021 it's common for motherboards with Z370, H310C or B365 PCHs, which are meant to be paired with Coffee Lake CPUs. Intel provides AmberLakeFspBinPkg to support this combination, which implements Intel FSP External Architecture Specification v2.1. Details: 1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and SKYLAKE_SOC_PCH_H. 2) Add Amberlake FSP support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead of KabylakeFspBinPkg. 3) Enable Coffee Lake CPUs support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select MAINBOARD_SUPPORTS_COFFEELAKE_CPU. 3) Increase stack and heap size in CAR. If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1), update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values. 4) Update maximal number of supported CPUs. If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16. Signed-off-by: Timofey Komarov <happycorsair(a)yandex.ru> Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c --- M src/soc/intel/skylake/Kconfig 1 file changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/52692/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 9 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: aopen/dxplplusu: Add early GPIO settings
by Kyösti Mälkki (Code Review) 02 May '21

02 May '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52815 ) Change subject: aopen/dxplplusu: Add early GPIO settings ...................................................................... aopen/dxplplusu: Add early GPIO settings Required for 2nd COM port to work. Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/bootblock.c M src/mainboard/aopen/dxplplusu/devicetree.cb M src/southbridge/intel/i82801dx/i82801dx.h 3 files changed, 110 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/52815/1 diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c index 5a969cf..3463711 100644 --- a/src/mainboard/aopen/dxplplusu/bootblock.c +++ b/src/mainboard/aopen/dxplplusu/bootblock.c @@ -1,12 +1,120 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <bootblock_common.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <southbridge/intel/i82801dx/i82801dx.h> #include <superio/smsc/lpc47m10x/lpc47m10x.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) +#define GPIO_DEV PNP_DEV(0x2e, LPC47M10X2_PME) +#define PME_BASE 0xe00 + +/* + * JP3 + * 1-2 0:1f.0 0xd4 GEN_STA SAFE_MODE = 0 + * 2-3 0:1f.0 0xd4 GEN_STA SAFE_MODE = 1 + */ + +static void enable_gpio(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* These should go under sb/. */ + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); + + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_enable(GPIO_DEV, 0); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO0, PME_BASE); + pnp_set_enable(GPIO_DEV, 1); + pnp_exit_conf_state(GPIO_DEV); + + pci_write_config16(dev, GEN1_DEC, PME_BASE | 0x01); +} + +static void gpio_write(u8 addr, u8 val) +{ + outb(val, PME_BASE + addr); +} + +static void gpio_read_write(u8 addr, u8 amask, u8 omask) +{ + u8 val = inb(PME_BASE + addr); + val &= amask; + val |= omask; + outb(val, PME_BASE + addr); +} + +static void configure_gpios(void) +{ + /* GP10-17 */ + gpio_write(0x23, 0x00); /* push-pull output */ + gpio_write(0x24, 0x81); /* open-drain but input ? */ + gpio_write(0x25, 0x01); + gpio_write(0x26, 0x01); + gpio_write(0x27, 0x01); + gpio_write(0x28, 0x01); + gpio_write(0x29, 0x01); + gpio_write(0x2a, 0x00); /* push-pull output */ + + /* GP20-27 */ + gpio_write(0x2b, 0x01); + gpio_write(0x2c, 0x0c); /* nDS1 floppy select */ + gpio_write(0x2d, 0x00); /* push-pull output */ + gpio_write(0x2f, 0x01); + gpio_write(0x30, 0x01); + gpio_write(0x31, 0x01); + gpio_write(0x32, 0x04); /* nIO_SMI */ + + /* GP30-37 */ + gpio_write(0x33, 0x04); /* FAN_TACH2 */ + gpio_write(0x34, 0x01); + gpio_write(0x35, 0x01); + gpio_write(0x36, 0x01); + gpio_write(0x37, 0x01); + gpio_write(0x38, 0x01); + gpio_write(0x39, 0x04); /* nKBDRESET */ + gpio_write(0x3a, 0x04); /* A20M */ + + /* GP40-43 */ + gpio_write(0x3b, 0x84); /* DRVDEN0 open-drain */ + gpio_write(0x3c, 0x04); /* DRVDEN1 push/pull */ + gpio_write(0x3d, 0x84); /* nIO_PME open-drain */ + gpio_write(0x3e, 0x01); + + /* GP50-GP57 to UART signals */ + gpio_write(0x3f, 0x05); + gpio_write(0x40, 0x05); + gpio_write(0x41, 0x05); + gpio_write(0x42, 0x04); + gpio_write(0x43, 0x05); + gpio_write(0x44, 0x04); + gpio_write(0x45, 0x05); + gpio_write(0x46, 0x04); + + /* GP60-GP61 */ + gpio_write(0x47, 0x86); /* LED1 invert open-drain*/ + gpio_write(0x48, 0x81); /* open-drain but input */ + + /* Set initial output bits */ + gpio_read_write(0x4b, 0xff, 0x81); /* GP1 */ + gpio_read_write(0x4c, ~0x01, 0x00); /* GP2 */ + gpio_read_write(0x4d, 0xff, 0x80); /* GP3 */ + gpio_read_write(0x4e, ~0x08, 0x00); /* GP4 */ + + /* LED1 off */ + gpio_write(0x5d, 0x00); +} void bootblock_mainboard_early_init(void) { + enable_gpio(); + configure_gpios(); + /* Get the serial port configured. */ lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index 166be3d..79b90be 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -45,7 +45,7 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 off # Com2 + device pnp 2e.5 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 9864720..c8cea07 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -72,6 +72,7 @@ #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B #define COM_DEC 0xE0 +#define GEN1_DEC 0xE4 #define LPC_EN 0xE6 #define FUNC_DIS 0xF2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Gerrit-Change-Number: 52815 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: aopen/dxplplusu: Fix IOAPIC in ASL
by Kyösti Mälkki (Code Review) 02 May '21

02 May '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52814 ) Change subject: aopen/dxplplusu: Fix IOAPIC in ASL ...................................................................... aopen/dxplplusu: Fix IOAPIC in ASL Change-Id: I8a2abe2cf20952491d181766a3ca492de355fc88 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/acpi_tables.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/52814/1 diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index a7a3d07..65d1f6c8 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -44,7 +44,7 @@ /* P64H2 Bus A IOAPIC */ if (bdev) - dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0)); + dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(30, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, -- To view, visit https://review.coreboot.org/c/coreboot/+/52814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a2abe2cf20952491d181766a3ca492de355fc88 Gerrit-Change-Number: 52814 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/e7505: Fix for RESOURCE_ALLOCATOR_V4
by Kyösti Mälkki (Code Review) 02 May '21

02 May '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52813 ) Change subject: nb/intel/e7505: Fix for RESOURCE_ALLOCATOR_V4 ...................................................................... nb/intel/e7505: Fix for RESOURCE_ALLOCATOR_V4 Memory region 0xa0000 to 0xc0000 was not reserved, the first PCI memory resources might get assigned in this space. FIXES: aopen/dxplplusu PCI EHCI 0:1d.7 memory resource. Change-Id: Ia17025bde83b91d71ad719de6348197cf92e267e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/e7505/northbridge.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/52813/1 diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index fc771b3..4908ecd 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -46,8 +46,8 @@ /* Report the memory regions */ idx = 10; - ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); + ram_resource(dev, idx++, 0, tolmk); + mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); if (tomk > basek_4G) ram_resource(dev, idx++, basek_4G, tomk - basek_4G); -- To view, visit https://review.coreboot.org/c/coreboot/+/52813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia17025bde83b91d71ad719de6348197cf92e267e Gerrit-Change-Number: 52813 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021