coreboot-gerrit May 2021

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Change in coreboot[master]: console/*: Use same indents for switch/case
by Felix Singer (Code Review) 10 Jun '23

10 Jun '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49204 ) Change subject: console/*: Use same indents for switch/case ...................................................................... console/*: Use same indents for switch/case Use same indents for switch/case to fix linter issues. Change-Id: I13c723c335d18bbdd2dcb041f44b187df6c5d728 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/console/vtxprintf.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49204/1 diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index c7bb585..16044c3 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -127,12 +127,12 @@ repeat: ++fmt; /* this also skips first '%' */ switch (*fmt) { - case '-': flags |= LEFT; goto repeat; - case '+': flags |= PLUS; goto repeat; - case ' ': flags |= SPACE; goto repeat; - case '#': flags |= SPECIAL; goto repeat; - case '0': flags |= ZEROPAD; goto repeat; - } + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= SPECIAL; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } /* get field width */ field_width = -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/49204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c723c335d18bbdd2dcb041f44b187df6c5d728 Gerrit-Change-Number: 49204 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/car/bootblock: Add post-console init callbacks
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36711 ) Change subject: soc/intel/car/bootblock: Add post-console init callbacks ...................................................................... soc/intel/car/bootblock: Add post-console init callbacks Change-Id: I8f3a1a098fa9f62496b23bf0a6584ab84917521d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/bootblock.c M src/cpu/intel/car/bootblock.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36711/1 diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index 664c2b5..063b444 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -35,8 +35,16 @@ bootblock_early_cpu_init(); } +void __weak bootblock_northbridge_init(void) { } +void __weak bootblock_southbridge_init(void) { } +void __weak bootblock_cpu_init(void) { } + void bootblock_soc_init(void) { /* Halt if there was a built in self test failure */ report_bist_failure(saved_bist); + /* Post console init */ + bootblock_northbridge_init(); + bootblock_southbridge_init(); + bootblock_cpu_init(); } diff --git a/src/cpu/intel/car/bootblock.h b/src/cpu/intel/car/bootblock.h index 5adfd87..af9e45e 100644 --- a/src/cpu/intel/car/bootblock.h +++ b/src/cpu/intel/car/bootblock.h @@ -18,4 +18,8 @@ void bootblock_early_northbridge_init(void); void bootblock_early_southbridge_init(void); +void bootblock_northbridge_init(void); +void bootblock_southbridge_init(void); +void bootblock_cpu_init(void); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f3a1a098fa9f62496b23bf0a6584ab84917521d Gerrit-Change-Number: 36711 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/smbios: Validate data for type17
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44017 ) Change subject: arch/x86/smbios: Validate data for type17 ...................................................................... arch/x86/smbios: Validate data for type17 Validate that the memory frequency reported is within the spec. Helps identifying platforms where the unit is wrong (MT/s vs MHz). Change-Id: I8b3d51464a92ed25017127f911a2292b0e10fb04 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44017/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 700de23..f27006b 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1078,6 +1078,38 @@ return len; } +static void smbios_type17_validate_dimm(struct dimm_info *dimm) +{ + u16 minf, maxf; + + switch (dimm->ddr_type) { + case MEMORY_TYPE_DDR4: + minf = 800; maxf = 1600; + break; + case MEMORY_TYPE_LPDDR4: + minf = 1600; maxf = 2133; + break; + case MEMORY_TYPE_DDR3: + minf = 400; maxf = 1067; + break; + case MEMORY_TYPE_LPDDR3: + minf = 800; maxf = 1067; + break; + case MEMORY_TYPE_DDR2: + minf = 400; maxf = 534; + break; + case MEMORY_TYPE_LPDDR2: + minf = 400; maxf = 534; + break; + default: + printk(BIOS_ERR, "SMBIOS: Unknown DIMM type %x\n", dimm->ddr_type); + return; + } + + if (dimm->ddr_frequency < minf || dimm->ddr_frequency > maxf) + printk(BIOS_ERR, "SMBIOS: Type 17 has invalid memory frequency: %d MHz\n", dimm->ddr_frequency); +} + static int smbios_write_type17(unsigned long *current, int *handle) { int len = sizeof(struct smbios_type17); @@ -1094,6 +1126,7 @@ i++) { struct dimm_info *dimm; dimm = &meminfo->dimm[i]; + smbios_type17_validate_dimm(dimm); len = create_smbios_type17_for_dimm(dimm, current, handle); *current += len; totallen += len; -- To view, visit https://review.coreboot.org/c/coreboot/+/44017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b3d51464a92ed25017127f911a2292b0e10fb04 Gerrit-Change-Number: 44017 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: smbios: Bump to 3.1
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44013 ) Change subject: smbios: Bump to 3.1 ...................................................................... smbios: Bump to 3.1 Set the entry point revision to the SMBIOS defined value and bump version to 3.1. All new fields introduced in 3.1 are already present and filled with valid data. Change-Id: Ieaf876d0297fd12b1ddfe8b3a69704ef03225930 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44013/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index d7e8747..1f22076 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1374,7 +1374,7 @@ memcpy(se->anchor, "_SM_", 4); se->length = sizeof(struct smbios_entry); se->major_version = 3; - se->minor_version = 0; + se->minor_version = 1; se->max_struct_size = max_struct_size; se->struct_count = handle; memcpy(se->intermediate_anchor_string, "_DMI_", 5); @@ -1392,7 +1392,8 @@ memcpy(se3->anchor, "_SM3_", 5); se3->length = sizeof(struct smbios_entry30); se3->major_version = 3; - se3->minor_version = 0; + se3->minor_version = 1; + se3->entry_point_rev = 1; se3->struct_table_address = (u64)tables; se3->struct_table_length = len; -- To view, visit https://review.coreboot.org/c/coreboot/+/44013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaf876d0297fd12b1ddfe8b3a69704ef03225930 Gerrit-Change-Number: 44013 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/smbios: Bump to version 3.2
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44015 ) Change subject: arch/x86/smbios: Bump to version 3.2 ...................................................................... arch/x86/smbios: Bump to version 3.2 Add new fields for type 17 and fill it with valid data. Rename configured_clock_speed to configured_memory_speed in type 17. All other structs and enums are already up to date. Change-Id: Iae56ad6bcde76ed25dc678b7bfed3b330ceaa77e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu2/mainboard.c 5 files changed, 31 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44015/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index be51075..700de23 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -317,7 +317,7 @@ memset(t, 0, sizeof(struct smbios_type17)); t->memory_type = dimm->ddr_type; /* Memory speed is in MT/s */ - t->configured_clock_speed = dimm->ddr_frequency * 2; + t->configured_memory_speed = dimm->ddr_frequency * 2; t->speed = dimm->ddr_frequency * 2; t->type = SMBIOS_MEMORY_DEVICE; @@ -366,6 +366,19 @@ /* no handle for error information */ t->memory_error_information_handle = 0xFFFE; t->attributes = dimm->rank_per_dimm; + + t->memory_technology = MEMORY_TECHNOLOGY_DRAM; + t->operating_mode_capability = MEMORY_OPERATING_MODE_CAP_UNKNOWN; + t->fw_version = smbios_add_string(t->eos, ""); + t->manufacturer_id = dimm->mod_id; + t->product_id = 0x0000; + t->sub_ctrl_manufacturer_id = 0x0000; + t->sub_ctrl_product_id = 0x0000; + t->non_volatile_size = ~0ULL; + t->volatile_size = ~0UL; + t->cache_size = ~0UL; + t->logical_size = ~0UL; + t->handle = *handle; *handle += 1; t->length = sizeof(struct smbios_type17) - 2; @@ -1376,7 +1389,7 @@ memcpy(se->anchor, "_SM_", 4); se->length = sizeof(struct smbios_entry); se->major_version = 3; - se->minor_version = 1; + se->minor_version = 2; se->max_struct_size = max_struct_size; se->struct_count = handle; memcpy(se->intermediate_anchor_string, "_DMI_", 5); @@ -1394,7 +1407,7 @@ memcpy(se3->anchor, "_SM3_", 5); se3->length = sizeof(struct smbios_entry30); se3->major_version = 3; - se3->minor_version = 1; + se3->minor_version = 2; se3->entry_point_rev = 1; se3->struct_table_address = (u64)tables; diff --git a/src/include/smbios.h b/src/include/smbios.h index cb354f7..aee81be 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -842,10 +842,21 @@ u8 part_number; u8 attributes; u32 extended_size; - u16 configured_clock_speed; + u16 configured_memory_speed; u16 minimum_voltage; u16 maximum_voltage; u16 configured_voltage; + u8 memory_technology; + u16 operating_mode_capability; + u8 fw_version; + u16 manufacturer_id; + u16 product_id; + u16 sub_ctrl_manufacturer_id; + u16 sub_ctrl_product_id; + u64 non_volatile_size; + u64 volatile_size; + u64 cache_size; + u64 logical_size; u8 eos[2]; } __packed; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 48f88d3..d7c96a4 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -197,7 +197,7 @@ t->memory_type = MEMORY_TYPE_DDR; t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; t->speed = 400; - t->configured_clock_speed = 400; + t->configured_memory_speed = 400; t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); len = t->length + smbios_string_table_len(t->eos); *current += len; diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 3c7f2f7..0f5fce3 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -222,7 +222,7 @@ t->part_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].PartNumber); t->attributes = agesa_dmi->T17[0][0][0].Attributes; t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; - t->configured_clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed * 2; + t->configured_memory_speed = agesa_dmi->T17[0][0][0].ConfigSpeed * 2; t->minimum_voltage = 1500; /* From SPD: 1.5V */ t->maximum_voltage = 1500; diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 531fcd0..6326b97 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -208,7 +208,7 @@ agesa_dmi->T17[0][0][0].PartNumber); t->attributes = agesa_dmi->T17[0][0][0].Attributes; t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; - t->configured_clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed * 2; + t->configured_memory_speed = agesa_dmi->T17[0][0][0].ConfigSpeed * 2; t->minimum_voltage = 1500; /* From SPD: 1.5V */ t->maximum_voltage = 1500; -- To view, visit https://review.coreboot.org/c/coreboot/+/44015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae56ad6bcde76ed25dc678b7bfed3b330ceaa77e Gerrit-Change-Number: 44015 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron/bsl6: Reorder selects alphabetically
by Felix Singer (Code Review) 10 Jun '23

10 Jun '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49062 ) Change subject: mb/kontron/bsl6: Reorder selects alphabetically ...................................................................... mb/kontron/bsl6: Reorder selects alphabetically Change-Id: I4f0a1742556d11757990891c58fa2e3431b989a5 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/kontron/bsl6/Kconfig 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/49062/1 diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index fd52d3e..efab85c 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -3,17 +3,17 @@ config BOARD_KONTRON_BSL6_COMMON def_bool n select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_SKYLAKE - select SKYLAKE_SOC_PCH_H - select EXCLUDE_NATIVE_SD_INTERFACE - select NO_FADT_8042 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select MAINBOARD_HAS_LPC_TPM - select EC_KONTRON_KEMPLD - select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_I2C_NCT7802Y + select EC_KONTRON_KEMPLD + select EXCLUDE_NATIVE_SD_INTERFACE + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select NO_FADT_8042 + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_SKYLAKE config BOARD_KONTRON_BSL6_OPTIONS bool -- To view, visit https://review.coreboot.org/c/coreboot/+/49062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f0a1742556d11757990891c58fa2e3431b989a5 Gerrit-Change-Number: 49062 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]mb/google/dedede: Modify fmd file to add CSE RW binary
by V Sowmya (Code Review) 10 Jun '23

10 Jun '23

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46331 ) Change subject: [WIP]mb/google/dedede: Modify fmd file to add CSE RW binary ...................................................................... [WIP]mb/google/dedede: Modify fmd file to add CSE RW binary Change-Id: Ibcf86f4bdb5fa5ab834da37f416ce692e5c121dd Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46331/1 diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd index 09b2abc..61f2b67 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd @@ -7,13 +7,15 @@ RW_LEGACY(CBFS)@0x0 0x1000 RW_SECTION_A@0x1000 0x420000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x40ffc0 - RW_FWID_A@0x41ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x27ffc0 + RW_FWID_A@0x28ffc0 0x40 + FW_MAIN_A_EXT(CBFS)@0x290000 0x190000 } RW_SECTION_B@0x421000 0x420000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x40ffc0 - RW_FWID_B@0x41ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x27ffc0 + RW_FWID_B@0x28ffc0 0x40 + FW_MAIN_B_EXT(CBFS)@0x290000 0x190000 } RW_MISC@0x841000 0x3e000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/46331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf86f4bdb5fa5ab834da37f416ce692e5c121dd Gerrit-Change-Number: 46331 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: post_code: replace die postcodes with die_with_post_code
by Sindhoor Tilak (Code Review) 10 Jun '23

10 Jun '23

Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43131 ) Change subject: post_code: replace die postcodes with die_with_post_code ...................................................................... post_code: replace die postcodes with die_with_post_code This change replaces failure postcode calls with die_with_post_code calls Change-Id: I6188da11df046131eed1e77c41ae229852c2b5ac Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> --- M src/arch/x86/postcar_loader.c M src/drivers/intel/fsp1_1/fsp_util.c M src/lib/ramtest.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/xeon_sp/romstage.c 5 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43131/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index fd1c172..7b3088f 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -97,7 +97,8 @@ void prepare_and_run_postcar(struct postcar_frame *pcf) { if (postcar_frame_init(pcf, 0)) - die("Unable to initialize postcar frame.\n"); + die_with_post_code(POST_EXIT_CAR_INIT_FAIL, + "Unable to initialize postcar frame.\n"); fill_postcar_frame(pcf); diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 9e7865d..a5ed5b2 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -123,8 +123,8 @@ fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC); if ((u32)fsp_header_ptr < 0xff) { /* output something in case there is no serial */ - post_code(0x4F); - die("Can't find the FSP!\n"); + die_with_post_code(POST_FSP_FAILURE, + "Can't find the FSP!\n"); } } diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index c6cd7a4..9b381f7 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -108,7 +108,8 @@ } } if (failures) { - post_code(0xea); + die_with_post_code(POST_RAM_TEST_FAIL, + "\nDRAM did _NOT_ verify!\n"); printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); return 1; } @@ -126,7 +127,7 @@ */ printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start); if (ram_bitset_nodie(start)) - die("DRAM ERROR"); + die_with_post_code(POST_RAM_FAILURE, "DRAM ERROR"); printk(BIOS_DEBUG, "Done.\n"); } @@ -198,8 +199,7 @@ write_phys(dst, backup); if (fail) { - post_code(0xea); - die("RAM INIT FAILURE!\n"); + die_with_post_code(POST_RAM_FAILURE, "RAM INIT FAILURE!\n"); } phys_memory_barrier(); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9fb80f8..991afc0 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -120,9 +120,9 @@ if (CONFIG(SMM_TSEG)) smm_list_regions(); - post_code(0x44); if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); + die_with_post_code(POST_EXIT_CAR_INIT_FAIL, + "Unable to initialize postcar frame.\n"); /* * We need to make sure ramstage will be run cached. At this point exact diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 9f4d78d..2d1b02e 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -25,7 +25,8 @@ unlock_pam_regions(); if (postcar_frame_init(&pcf, 1 * KiB)) - die("Unable to initialize postcar frame.\n"); + die_with_post_code(POST_EXIT_CAR_INIT_FAIL, + "Unable to initialize postcar frame.\n"); /* * We need to make sure ramstage will be run cached. At this point exact -- To view, visit https://review.coreboot.org/c/coreboot/+/43131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6188da11df046131eed1e77c41ae229852c2b5ac Gerrit-Change-Number: 43131 Gerrit-PatchSet: 1 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Advertise PM timer
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46848 ) Change subject: soc/intel/xeon_sp/cpx: Advertise PM timer ...................................................................... soc/intel/xeon_sp/cpx: Advertise PM timer Unclear why it was missing and if it's working. Test: Tianocore now boots. Change-Id: I7e68430c3e720561b85834c5f8c43c1c24da852f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/46848/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 3066dda2..a4a3fc3 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -142,7 +142,7 @@ fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - + fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->pm1_evt_len = 4; @@ -169,6 +169,13 @@ fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + /* * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. * The bit_width field intentionally overflows here. -- To view, visit https://review.coreboot.org/c/coreboot/+/46848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e68430c3e720561b85834c5f8c43c1c24da852f Gerrit-Change-Number: 46848 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Enable SATA ports
by Andrey Petrov (Code Review) 10 Jun '23

10 Jun '23

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39918 ) Change subject: soc/intel/xeon_sp/cpx: Enable SATA ports ...................................................................... soc/intel/xeon_sp/cpx: Enable SATA ports Looks like FSP does not explicity configure SATA ports as enabled. As result some payloads (SeaBIOS, TianoCore) can detect the drives but Linux kernel does not. Turns out the kernel does not touch disabled ports, while SeaBIOS just checks all available ports. Interestingly, SKX FSP seems to be enabling all the ports. This change hooks up some common SATA code which enables all ports. TEST=booted on Cedar Island CRB, make sure 7-pin SATA drive works Change-Id: Iba8f8c8812168deace1abaa7cf3996b870648686 --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/39918/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 70703d0..2f637b1 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -17,6 +17,8 @@ select POSTCAR_CONSOLE select POSTCAR_STAGE select FSP_USES_CB_STACK + select SOC_INTEL_COMMON_BLOCK_SATA + select SOC_AHCI_PORT_IMPLEMENTED_INVERT config FSP_HEADER_PATH string "Location of FSP headers" -- To view, visit https://review.coreboot.org/c/coreboot/+/39918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba8f8c8812168deace1abaa7cf3996b870648686 Gerrit-Change-Number: 39918 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

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