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Change subject: elog: Add a log for Chrome OS diagnostics boot in coreboot/bootmode
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54948/comment/196222cf_5dbb71d7
PS1, Line 9: Add an elog type 0xb6 for Chrome OS diagnostics related events.
> The Chrome OS diagnostics is more like the fourth 'bootmode' of Chrome OS. […]
I think Paul was suggesting to also note that a log message is added as well.
Patchset:
PS1:
src/security/vboot/bootmode.c: In function 'vboot_diagnostic_boot_requested':
src/security/vboot/bootmode.c:33:9: error: implicit declaration of function 'vb2api_diagnostic_boot_requested'; did you mean 'vboot_diagnostic_boot_requested'? [-Werror=implicit-function-declaration]
return vb2api_diagnostic_boot_requested(vboot_get_context());
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vboot_diagnostic_boot_requested
You are going to need to update the vboot submodule pointer in a separate commit before this one or together.
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Change subject: amdfwtool: Add a function to extract firmwares
......................................................................
Patch Set 6:
(10 comments)
File util/amdfwtool/extract.c:
https://review.coreboot.org/c/coreboot/+/54901/comment/3fe9f2ed_2063eaf1
PS6, Line 15: 0
Use amd_fw_type enums here?
https://review.coreboot.org/c/coreboot/+/54901/comment/4ad26995_aecc240d
PS6, Line 17: 8
> Can this be sorted?
That's the order they go into the image 😄 The PSP needs the items in the order it plans to consume them.
https://review.coreboot.org/c/coreboot/+/54901/comment/2b49c595_1b89dad5
PS6, Line 68: psp_cookie = ppsp->header.cookie;
Since this is only used in if/else decisions for naming below, would it look cleaner to make the decision here instead?
https://review.coreboot.org/c/coreboot/+/54901/comment/dc749790_5ba0b080
PS6, Line 75: if (token == 6 || token == 0xb)
Use the amd_fw_type enums? BTW what is 6?
https://review.coreboot.org/c/coreboot/+/54901/comment/00898b73_38a69526
PS6, Line 91: PspDirL10_Typex
What's the 0 there, i.e. L10? Is the plan to replace that with the subprogram value?
Oh, you have token as uint32, so you're already getting type/subprog/rsvd. In that case, I'd change it to %04x to be clearer (I assume you'll have a script later that can parse the filenames and use them as arguments back into amdfwtool).
https://review.coreboot.org/c/coreboot/+/54901/comment/2dc34d84_85a04e72
PS6, Line 110: extract_bios_fws
All comments in extract_psp_fws() apply here too
https://review.coreboot.org/c/coreboot/+/54901/comment/47f058fb_d4c36521
PS6, Line 178: romsig_offset
This has a strange look here after the init of romsig_offsets. I'd put it on the next line.
https://review.coreboot.org/c/coreboot/+/54901/comment/f08dd056_59a89a5d
PS6, Line 206: romsig_offsets[index] != 0xFFFFFFFF
Does this for() loop also need a check for not reading past the size of the buffer? For example, if you have an image size of 0x800000, you wouldn't want to read from offset 0xFA0000.
https://review.coreboot.org/c/coreboot/+/54901/comment/53911b00_dc391439
PS6, Line 238: ppsp = (psp_directory_table *)&buffer[psp2_offset];
: extract_psp_fws(buffer, ppsp, image_base, NULL);
Probably surround these with
if (psp2_offset) {
}
https://review.coreboot.org/c/coreboot/+/54901/comment/efdaf53a_d6454241
PS6, Line 242: pbdt = (bios_directory_table *)&buffer[bhd2_offset];
: extract_bios_fws(buffer, pbdt, image_base, NULL);
same as above
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Hello Philipp Deppenwiese, build bot (Jenkins), Michał Żygowski, Christian Walter, Aaron Durbin, Piotr Król,
I'd like you to reexamine a change. Please visit
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Change subject: tpm: Remove USER_TPMx options, make TPM1/TPM2 menuconfig visible
......................................................................
tpm: Remove USER_TPMx options, make TPM1/TPM2 menuconfig visible
We would like to have an easy way to completely disable TPM support on a
board. For boards that don't pre-select a TPM protocol via the
MAINBOARD_HAS_TPMx options, this is already possible with the
USER_NO_TPM option. In order to make this available for all boards, this
patch just removes the whole USER_TPMx option group and directly makes
the TPM1 and TPM2 options visible to menuconfig. The MAINBOARD_HAS_TPMx
options can still be used to select defaults and to prevent selection of
a protocol that the TPM is known to not support, but the NO_TPM option
always remains available.
Also fix some mainboards that selected TPM2 directly, which they're not
supposed to do (that's what MAINBOARD_HAS_TPM2 is for), and add a
missing dependency to TPM_CR50 so it is set correctly for a NO_TPM
scenario.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: Ib0a73da3c42fa4e8deffecb53f29ee38cbb51a93
---
M configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms
M configs/config.libretrend_lt1000
M src/mainboard/google/drallion/Kconfig
M src/mainboard/protectli/vault_kbl/Kconfig
M src/security/tpm/Kconfig
M src/security/tpm/tss/vendor/cr50/Kconfig
6 files changed, 33 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/54641/3
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Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54900 )
Change subject: amdfwtool: Print the entry type when dumping the firmwares
......................................................................
Patch Set 2:
(2 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/54900/comment/c6e50c0e_8f1752f8
PS2, Line 653: %x:
Maybe %02x or more in order to align of the strings. There are a small number that are only one digit, most are two, and some of the older ones are three.
And would it look better to add a space after the colon?
https://review.coreboot.org/c/coreboot/+/54900/comment/b7be4670_c71d1f7a
PS2, Line 664: %x
Whatever you decide above, repeat here
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Change subject: amdfwtool: Set the region_type as 0 for entry "BIOS level 2"
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/54871/comment/3b3f351a_dafc0a9c
PS2, Line 1047: region_type
> So this changes the region type from 0xFF to 0?
Yes, only for the type 0x70 entry, which is the pointer to the 2nd level of the table. I don't see any description for valid values for this field however I'd missed it when writing the code.
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Hello build bot (Jenkins), Joel Kitching, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/54099
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Change subject: vboot: Add VB2_CONTEXT_EC_TRUSTED
......................................................................
vboot: Add VB2_CONTEXT_EC_TRUSTED
This patch makes coreboot set VB2_CONTEXT_EC_TRUSTED based on the EC"s
boot mode. Vboot will check VB2_CONTEXT_EC_TRUSTED to determine
whether it can enter recovery mode or not.
BUG=b:180927027, b:187871195
BRANCH=none
TEST=build
Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Change-Id: I9fa09dd7ae5baa1efb4e1ed4f0fe9a6803167c93
---
M src/security/vboot/vboot_logic.c
1 file changed, 12 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/54099/6
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Change subject: mb/amd/majolica: enable crypto coprocessor PCIe device
......................................................................
Patch Set 1: Code-Review+2
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