coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

1 participants
6269 discussions

Change in coreboot[master]: add BASIC interpreter or similar payload to project ideas
by Olaf Hernandez Beristain (Code Review) 10 Jun '23

10 Jun '23

Olaf Hernandez Beristain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48420 ) Change subject: add BASIC interpreter or similar payload to project ideas ...................................................................... add BASIC interpreter or similar payload to project ideas Change-Id: Ib5cfd6ddf6ddaa384c66c313c993fbfcc911e3c3 --- M Documentation/contributing/project_ideas.md 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/48420/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 141023f..c4c26c5 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -247,3 +247,14 @@ ### Mentors * Patrick Rudolph <patrick.rudolph(a)9elements.com> * Christian Walter <christian.walter(a)9elements.com> + +## Create a BASIC interpreter or similar payload +A payload that can run a BASIC interpreter or similar. Possibly could be a subset of [GW-BASIC](https://github.com/microsoft/GW-BASIC). +In fact any code interpreter would be great. Another option is [Forth/Fcode](https://www.openfirmware.info/Forth/FCode) + + +### Requirements +* coreboot knowledge: Should know how to build coreboot images and + include payloads. +* understanding low level programming +* know how interpreter works -- To view, visit https://review.coreboot.org/c/coreboot/+/48420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5cfd6ddf6ddaa384c66c313c993fbfcc911e3c3 Gerrit-Change-Number: 48420 Gerrit-PatchSet: 1 Gerrit-Owner: Olaf Hernandez Beristain <olafitohb(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/intel: Add unaligned flag (%) sections that don't need alignment
by Hung-Te Lin (Code Review) 10 Jun '23

10 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37314 ) Change subject: mb/intel: Add unaligned flag (%) sections that don't need alignment ...................................................................... mb/intel: Add unaligned flag (%) sections that don't need alignment Sections that won't be updated independently and don't need to be aligned. Note: glkrvp/chromeos.fmd had unaligned RW_SECTION_{A,B} and is fixed now. leafhill/leafhill.8192.fmd had unaligned UNIFIED_MRC_CACHE and is fixed. Change-Id: I9333dddd9ead3610216009fb6fd1ad6df5f05cf3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/intel/baskingridge/chromeos.fmd M src/mainboard/intel/cannonlake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd M src/mainboard/intel/galileo/vboot.fmd M src/mainboard/intel/glkrvp/chromeos.fmd M src/mainboard/intel/icelake_rvp/chromeos.fmd M src/mainboard/intel/kblrvp/chromeos.fmd M src/mainboard/intel/kunimitsu/chromeos.fmd M src/mainboard/intel/leafhill/leafhill.16384.fmd M src/mainboard/intel/leafhill/leafhill.8192.fmd M src/mainboard/intel/minnow3/minnow3.fmd M src/mainboard/intel/strago/chromeos.fmd M src/mainboard/intel/wtm2/chromeos.fmd 14 files changed, 88 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37314/1 diff --git a/src/mainboard/intel/baskingridge/chromeos.fmd b/src/mainboard/intel/baskingridge/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/baskingridge/chromeos.fmd +++ b/src/mainboard/intel/baskingridge/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd index 62e0f5d..0a7be5f 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd index 4d349bd..d4f9021 100644 --- a/src/mainboard/intel/galileo/vboot.fmd +++ b/src/mainboard/intel/galileo/vboot.fmd @@ -20,13 +20,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -40,11 +40,11 @@ RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 + RO_UNUSED@0x4000% 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x7f000 COREBOOT(CBFS)@0x80000 0x170000 } diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd index 5d4ba46..fbaca9b 100644 --- a/src/mainboard/intel/glkrvp/chromeos.fmd +++ b/src/mainboard/intel/glkrvp/chromeos.fmd @@ -4,9 +4,9 @@ IFWI@0x1000 0x1ff000 RO_VPD(PRESERVE)@0x200000 0x4000 RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 COREBOOT(CBFS)@0x1000 0x1ab000 GBB@0x1ac000 0x40000 RO_UNUSED@0x1ec000 0x10000 @@ -27,17 +27,17 @@ FPF_STATUS@0x3B000 0x1000 TMP_UNUSED_HOLE@0x3C000 0xE000 } - RW_SECTION_A@0x44a000 0x477800 { + RW_SECTION_A@0x44a000 0x478000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4677c0 - RW_FWID_A@0x4777c0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x467fc0 + RW_FWID_A@0x477fc0% 0x40 } - RW_SECTION_B@0x8c1800 0x477800 { + RW_SECTION_B@0x8c2000 0x478000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4677c0 - RW_FWID_B@0x4777c0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x467fc0 + RW_FWID_B@0x477fc0% 0x40 } - RW_NVRAM(PRESERVE)@0xd39000 0x6000 + RW_NVRAM(PRESERVE)@0xd3a000 0x6000 SMMSTORE(PRESERVE)@0xd40000 0x40000 RW_LEGACY(CBFS)@0xd80000 0x1b0000 BIOS_UNUSABLE@0xf3f000 0x40000 diff --git a/src/mainboard/intel/icelake_rvp/chromeos.fmd b/src/mainboard/intel/icelake_rvp/chromeos.fmd index f4db8b4..037de53 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/icelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/kblrvp/chromeos.fmd b/src/mainboard/intel/kblrvp/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kblrvp/chromeos.fmd +++ b/src/mainboard/intel/kblrvp/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/kunimitsu/chromeos.fmd b/src/mainboard/intel/kunimitsu/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.fmd +++ b/src/mainboard/intel/kunimitsu/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/leafhill/leafhill.16384.fmd b/src/mainboard/intel/leafhill/leafhill.16384.fmd index a91ba9a..a7a6b26 100644 --- a/src/mainboard/intel/leafhill/leafhill.16384.fmd +++ b/src/mainboard/intel/leafhill/leafhill.16384.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x2ff000 - FMAP@0x300000 0x800 - COREBOOT(CBFS)@0x300800 0xc1d800 + FMAP@0x300000% 0x800 + COREBOOT(CBFS)@0x300800% 0xc1d800 UNIFIED_MRC_CACHE@0xf1e000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/leafhill/leafhill.8192.fmd b/src/mainboard/intel/leafhill/leafhill.8192.fmd index 3f4d21b..3fe71e0 100644 --- a/src/mainboard/intel/leafhill/leafhill.8192.fmd +++ b/src/mainboard/intel/leafhill/leafhill.8192.fmd @@ -1,9 +1,9 @@ FLASH 8M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x321000 0x800 - COREBOOT(CBFS)@0x321800 0x300000 - UNIFIED_MRC_CACHE@0x621800 0x21000 { + FMAP@0x321000% 0x800 + COREBOOT(CBFS)@0x321800% 0x300800 + UNIFIED_MRC_CACHE@0x622000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd index d51b5ee..9733567 100644 --- a/src/mainboard/intel/minnow3/minnow3.fmd +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x301000 0x800 - COREBOOT(CBFS)@0x301800 0x3dc800 + FMAP@0x301000% 0x800 + COREBOOT(CBFS)@0x301800% 0x3dc800 UNIFIED_MRC_CACHE@0x6de000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/strago/chromeos.fmd b/src/mainboard/intel/strago/chromeos.fmd index 923c8ee..5dec9ec 100644 --- a/src/mainboard/intel/strago/chromeos.fmd +++ b/src/mainboard/intel/strago/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x6f000 COREBOOT(CBFS)@0x70000 0x180000 } diff --git a/src/mainboard/intel/wtm2/chromeos.fmd b/src/mainboard/intel/wtm2/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/wtm2/chromeos.fmd +++ b/src/mainboard/intel/wtm2/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/37314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9333dddd9ead3610216009fb6fd1ad6df5f05cf3 Gerrit-Change-Number: 37314 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: Documentation/vendorcode/eltan/security.md: Fix bugs in the guide
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43483 ) Change subject: Documentation/vendorcode/eltan/security.md: Fix bugs in the guide ...................................................................... Documentation/vendorcode/eltan/security.md: Fix bugs in the guide ELTAN verified boot seems to be using vboot 2.1 key format not vboot 1.0. Generating vboot 1.0 keys results in public key of incorrect size (according to the verified boot implementation in vendorcode) which results in errors during booting. Fix the cbfstool extraction command to take account for stage file which may have certain sections removed. Add note about endianess of digest generated by openssl. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I27cf8e3f8e22876f671092fe4d3265a98564d996 --- M Documentation/vendorcode/eltan/security.md 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43483/1 diff --git a/Documentation/vendorcode/eltan/security.md b/Documentation/vendorcode/eltan/security.md index 9dd47c0..1c05cd5 100644 --- a/Documentation/vendorcode/eltan/security.md +++ b/Documentation/vendorcode/eltan/security.md @@ -42,7 +42,7 @@ Create private key in RSA2048 format: `openssl genrsa -F4 -out <private_key_file> 2048` Create public key using private key: -`futility --vb1 create <private_key_file> <public_key_file_without_extension>` +`futility --vb21 create <private_key_file> <public_key_file_without_extension>` The public key will be included into coreboot and used for verified boot only. @@ -79,9 +79,15 @@ The total number of items must match `VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS`. For every part the SHA (SHA-256) must be calculated. First extract the binary from the coreboot -image using: `cbfstool <coreboot_file_name> extract -n <cbfs_name> -f <item_binary_file_name>` +image using: `cbfstool <coreboot_file_name> extract -n <cbfs_name> -f <item_binary_file_name> -m x86 -U` +Note the `-m x86 -U` flags are required for correct extraction of stages. Certain stages are +put in CBFS without certain program sections so extraction process must also remove these sections. + followed by: `openssl dgst -sha256 -binary -out <hash_file_name> <item_binary_file_name>` +The SHA256 digest will be in big endian so it must be converted to little endian with: +`< <hash_file_name> xxd -p -c1 | tac | xxd -p -r > <hash_file_name_le>` + Replace -sha256 with -sha512 when `VENDORCODE_ELTAN_VBOOT_USE_SHA512` is enabled. All the hashes must be combined to a hash binary. The hashes need to be placed in the same order as -- To view, visit https://review.coreboot.org/c/coreboot/+/43483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27cf8e3f8e22876f671092fe4d3265a98564d996 Gerrit-Change-Number: 43483 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/prodrive/hermes: Cache check_board_settings_checksum
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48646 ) Change subject: mb/prodrive/hermes: Cache check_board_settings_checksum ...................................................................... mb/prodrive/hermes: Cache check_board_settings_checksum Change-Id: I46e063fd9c2808ae427bdbfb3a8b0a63c59dec47 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/eeprom.c 1 file changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48646/1 diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index f88b587..a0bb639 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -42,6 +42,12 @@ struct eeprom_board_settings BoardSettings; uint32_t crc; + static bool checked; + static bool valid; + + if (checked) + goto out; + if (read_write_config(&BoardSettings, off, 0, sizeof(BoardSettings))) { printk(BIOS_ERR, "CFG EEPROM: Failed to read board settings\n"); return 0; @@ -49,11 +55,14 @@ crc = CRC(((uint8_t *)&BoardSettings) + sizeof(uint32_t), sizeof(BoardSettings) - sizeof(uint32_t), crc32_byte); - if (crc != BoardSettings.signature) { + + valid = crc == BoardSettings.signature; + checked = true; +out: + if (!valid) printk(BIOS_ERR, "CFG EEPROM: Board settings have invalid checksum\n"); - return 0; - } - return 1; + + return valid; } /* Read data from offset and write it to offset in UPD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e063fd9c2808ae427bdbfb3a8b0a63c59dec47 Gerrit-Change-Number: 48646 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: add a command to write SR1
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48629 ) Change subject: add a command to write SR1 ...................................................................... add a command to write SR1 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: Ic4f74173b3e74b352b2dcff63d8c2c132cc6fe6f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/drivers/spi/spi_flash.c M src/include/spi_flash.h M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/jasperlake/romstage/romstage.c 5 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/48629/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f2610a1..acdcc19 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -530,6 +530,14 @@ return -1; } +int spi_flash_wr_status(const struct spi_flash *flash, u8 value) +{ + if (flash->ops->wr_status) + return flash->ops->wr_status(flash, value); + + return -1; +} + int spi_flash_is_write_protected(const struct spi_flash *flash, const struct region *region) { diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 1061e99..9d53911 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -47,6 +47,7 @@ const void *buf); int (*erase)(const struct spi_flash *flash, u32 offset, size_t len); int (*status)(const struct spi_flash *flash, u8 *reg); + int (*wr_status)(const struct spi_flash *flash, u8 value); }; /* Current code assumes all callbacks are supplied in this object. */ @@ -144,6 +145,7 @@ const void *buf); int spi_flash_erase(const struct spi_flash *flash, u32 offset, size_t len); int spi_flash_status(const struct spi_flash *flash, u8 *reg); +int spi_flash_wr_status(const struct spi_flash *flash, u8 value); /* * Return the vendor dependent SPI flash write protection state. diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index bafe131..67e660d 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -53,6 +53,7 @@ #define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) #define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) #define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) +#define SPIBAR_HSFSTS_CYCLE_WR_STATUS SPIBAR_HSFSTS_FCYCLE(7) #define SPIBAR_HSFSTS_FGO (1 << 16) #define SPIBAR_HSFSTS_FLOCKDN (1 << 15) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index da99490..f7945d9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -243,6 +243,24 @@ return SUCCESS; } +static int fast_spi_status_write(const struct spi_flash *flash, uint8_t value) +{ + int ret; + uint8_t val = value; + size_t xfer_len = sizeof(uint8_t); + + BOILERPLATE_CREATE_CTX(ctx); + + fill_xfer_fifo(ctx, (void *) &val, xfer_len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WR_STATUS, + 0, xfer_len); + if (ret != SUCCESS) + return ret; + + return SUCCESS; +} + static int fast_spi_flash_status(const struct spi_flash *flash, uint8_t *reg) { @@ -263,6 +281,7 @@ .write = fast_spi_flash_write, .erase = fast_spi_flash_erase, .status = fast_spi_flash_status, + .wr_status = fast_spi_status_write, }; /* diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 1fa6c2d..64d5014 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -14,6 +14,11 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <spi_flash.h> +#include <region_file.h> +#include <fmap.h> + +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -120,6 +125,48 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } +static void save_and_restore_sr1(void) +{ + int i; + u8 spi_sts1, spi_sts2; + const struct spi_flash *spi = boot_device_spi_flash(); + struct region_device rdev; + struct region_file cache_file; + const char *name = "RW_LEGACY"; + const uint32_t invalid = ~MRC_DATA_SIGNATURE; + + if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) { + printk(BIOS_ERR, "SR save/res: Couldn't find '%s' region. Invalidation failed\n", + name); + return; + } + + if (region_file_init(&cache_file, &rdev) < 0) { + printk(BIOS_ERR, "SR save/res: region file invalid for '%s'. Invalidation failed\n", + name); + return; + } + + for (i=0; i < 500; i++) { + spi_flash_status(spi, &spi_sts1); + printk(BIOS_DEBUG, "SPI_STATUS before write: 0x%x\n", spi_sts1); + + spi_flash_wr_status (spi, 0x00); + spi_flash_status(spi, &spi_sts2); + printk(BIOS_DEBUG, "SPI_STATUS after 0x0: 0x%x\n", spi_sts2); + + printk(BIOS_DEBUG, "SPI_STATUS Updating RW_LEGACY\n"); + /* Push an update that consists of 4 bytes that is smaller than the + * MRC metadata as well as an invalid signature. */ + if (region_file_update_data(&cache_file, &invalid, sizeof(invalid)) < 0) + printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); + + spi_flash_wr_status (spi, spi_sts1); + spi_flash_status(spi, &spi_sts2); + printk(BIOS_DEBUG, "SPI_STATUS after restore: 0x%x\n", spi_sts2); + } +} + void mainboard_romstage_entry(void) { bool s3wake; @@ -133,6 +180,9 @@ heci_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; + + save_and_restore_sr1(); + fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) -- To view, visit https://review.coreboot.org/c/coreboot/+/48629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f74173b3e74b352b2dcff63d8c2c132cc6fe6f Gerrit-Change-Number: 48629 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb: Add unaligned flag (%) sections that don't need alignment
by Hung-Te Lin (Code Review) 10 Jun '23

10 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37317 ) Change subject: mb: Add unaligned flag (%) sections that don't need alignment ...................................................................... mb: Add unaligned flag (%) sections that don't need alignment Fix all FMD files with unaligned sections. Change-Id: Icfd1e68990a272fbde9a0238f8a8b75db1549b05 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd M src/mainboard/lenovo/t400/vboot-rwa.fmd M src/mainboard/lenovo/t410/vboot-rwa.fmd M src/mainboard/lenovo/t420/vboot-rwa.fmd M src/mainboard/lenovo/t420s/vboot-rwa.fmd M src/mainboard/lenovo/t520/vboot-rwa.fmd M src/mainboard/lenovo/x200/vboot-rwa.fmd M src/mainboard/lenovo/x201/vboot-rwa.fmd M src/mainboard/lenovo/x220/vboot-rwa.fmd M src/mainboard/opencellular/elgon/vboot.fmd M src/mainboard/samsung/lumpy/chromeos.fmd M src/mainboard/samsung/stumpy/chromeos.fmd M src/mainboard/siemens/mc_apl1/mc_apl1.fmd M src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd M src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd M src/mainboard/up/squared/vboot-ro.fmd M src/mainboard/up/squared/vboot-roa.fmd M src/mainboard/up/squared/vboot-roab.fmd 19 files changed, 104 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37317/1 diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd index 0d2c9da..fb8960b 100644 --- a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -2,15 +2,15 @@ SI_BIOS 0x1000000 { RW_SECTION_A 0x7c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% 0x74ffc0 + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd index 0d2c9da..fb8960b 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -2,15 +2,15 @@ SI_BIOS 0x1000000 { RW_SECTION_A 0x7c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% 0x74ffc0 + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t400/vboot-rwa.fmd b/src/mainboard/lenovo/t400/vboot-rwa.fmd index 4af3fcd..9112721 100644 --- a/src/mainboard/lenovo/t400/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t400/vboot-rwa.fmd @@ -8,16 +8,16 @@ SI_BIOS@0x600000 0x200000 { RW_SECTION_A 0x100000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 CONSOLE 0x10000 SMMSTORE(PRESERVE) 0x40000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t410/vboot-rwa.fmd b/src/mainboard/lenovo/t410/vboot-rwa.fmd index 8f50d33..885aa0d 100644 --- a/src/mainboard/lenovo/t410/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t410/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A 0x180000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } UNIFIED_MRC_CACHE 0x20000 { RECOVERY_MRC_CACHE 0x10000 @@ -20,9 +20,9 @@ WP_RO { RO_VPD(PRESERVE) 0x1000 RO_SECTION 0x11e000 { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/t420/vboot-rwa.fmd b/src/mainboard/lenovo/t420/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t420/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t520/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/x200/vboot-rwa.fmd b/src/mainboard/lenovo/x200/vboot-rwa.fmd index 4af3fcd..9112721 100644 --- a/src/mainboard/lenovo/x200/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x200/vboot-rwa.fmd @@ -8,16 +8,16 @@ SI_BIOS@0x600000 0x200000 { RW_SECTION_A 0x100000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 CONSOLE 0x10000 SMMSTORE(PRESERVE) 0x40000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd index 0d1aa5d..dc035e9 100644 --- a/src/mainboard/lenovo/x201/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x201/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A 0x180000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } UNIFIED_MRC_CACHE 0x20000 { RECOVERY_MRC_CACHE 0x10000 @@ -19,9 +19,9 @@ WP_RO { RO_VPD(PRESERVE) 0x1000 RO_SECTION { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/x220/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/opencellular/elgon/vboot.fmd b/src/mainboard/opencellular/elgon/vboot.fmd index 0d6af2d..dbb31cb 100644 --- a/src/mainboard/opencellular/elgon/vboot.fmd +++ b/src/mainboard/opencellular/elgon/vboot.fmd @@ -4,8 +4,8 @@ RO_SECTION@0x0 0x3fc000 { # 0 - 0x10000 is free for firmware usage. # bootblock starts at 0x20000 - FMAP@0x0 0x1000 - RO_FRID@0x1000 0x100 + FMAP@0x0% 0x1000 + RO_FRID@0x1000% 0x100 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. @@ -17,13 +17,13 @@ } RW_SECTION_A@0x400000 0x5fa000 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x5f7f00 - RW_FWID_A@0x5f9f00 0x100 + FW_MAIN_A(CBFS)@0x2000% 0x5f7f00 + RW_FWID_A@0x5f9f00% 0x100 } RW_SECTION_B@0x9fa000 0x5fa000 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x5f7f00 - RW_FWID_B@0x5f9f00 0x100 + FW_MAIN_B(CBFS)@0x2000% 0x5f7f00 + RW_FWID_B@0x5f9f00% 0x100 } RW_ELOG(PRESERVE)@0xff4000 0x4000 RW_VPD(PRESERVE)@0xff8000 0x8000 diff --git a/src/mainboard/samsung/lumpy/chromeos.fmd b/src/mainboard/samsung/lumpy/chromeos.fmd index 9852a22..95ec048 100644 --- a/src/mainboard/samsung/lumpy/chromeos.fmd +++ b/src/mainboard/samsung/lumpy/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/samsung/stumpy/chromeos.fmd b/src/mainboard/samsung/stumpy/chromeos.fmd index 9852a22..95ec048 100644 --- a/src/mainboard/samsung/stumpy/chromeos.fmd +++ b/src/mainboard/samsung/stumpy/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 36772d6..2dd2173 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI 0x2ff000 - FMAP 0x800 - COREBOOT(CBFS) 0xb9d800 + FMAP% 0x800 + COREBOOT(CBFS)% 0xb9d800 UNIFIED_MRC_CACHE 0x21000 { RECOVERY_MRC_CACHE 0x10000 RW_MRC_CACHE 0x10000 diff --git a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd index 8af2e9a..c9d1c148 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd @@ -4,9 +4,9 @@ IFWI 0x2ff000 RO_VPD 0x4000 RO_SECTION 0xb8f000 { - FMAP 0x800 - RO_FRID 0x40 - RO_FRID_PAD 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_FRID_PAD% 0x7c0 COREBOOT(CBFS) 0xb4e000 GBB 0x40000 } diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd index a295680..96f359e 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd +++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x500000 0xb00000 { RW_SECTION_A@0x0 0x33e000 { VBLOCK_A@0x0 0x20000 - FW_MAIN_A(CBFS)@0x20000 0x31dfc0 - RW_FWID_A@0x33dfc0 0x40 + FW_MAIN_A(CBFS)@0x20000% 0x31dfc0 + RW_FWID_A@0x33dfc0% 0x40 } RW_SECTION_B@0x33e000 0x33e000 { VBLOCK_B@0x0 0x20000 - FW_MAIN_B(CBFS)@0x20000 0x31dfc0 - RW_FWID_B@0x33dfc0 0x40 + FW_MAIN_B(CBFS)@0x20000% 0x31dfc0 + RW_FWID_B@0x33dfc0% 0x40 } MISC_RW@0x67d000 0x62000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -25,9 +25,9 @@ WP_RO@0x6df000 0x421000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x41d000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x32d000 } diff --git a/src/mainboard/up/squared/vboot-ro.fmd b/src/mainboard/up/squared/vboot-ro.fmd index 72f92fe..afebc8c 100644 --- a/src/mainboard/up/squared/vboot-ro.fmd +++ b/src/mainboard/up/squared/vboot-ro.fmd @@ -3,11 +3,11 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0xe91000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0xb8d800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0xb8d800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0xb4d000 } diff --git a/src/mainboard/up/squared/vboot-roa.fmd b/src/mainboard/up/squared/vboot-roa.fmd index 330ce03..b23e69f 100644 --- a/src/mainboard/up/squared/vboot-roa.fmd +++ b/src/mainboard/up/squared/vboot-roa.fmd @@ -3,11 +3,11 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0x502000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0x1fe800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0x1fe800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0x1be000 } @@ -28,8 +28,8 @@ } RW_SECTION_A@0x52f000 0x98f000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x97efc0 - RW_FWID_A@0x98efc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x97efc0 + RW_FWID_A@0x98efc0% 0x40 } BIOS_UNUSABLE@0xebe000 0x40000 } diff --git a/src/mainboard/up/squared/vboot-roab.fmd b/src/mainboard/up/squared/vboot-roab.fmd index 4ddcbc0..90e8e37 100644 --- a/src/mainboard/up/squared/vboot-roab.fmd +++ b/src/mainboard/up/squared/vboot-roab.fmd @@ -3,12 +3,12 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0x503000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0x1ff800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 - GBB@0x800 0x40000 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0x1ff800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 + GBB@0x800% 0x40000 COREBOOT(CBFS)@0x40800 0x1bf000 } } @@ -28,13 +28,13 @@ } RW_SECTION_A@0x530000 0x4c7000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4b6fc0 - RW_FWID_A@0x4c6fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x4b6fc0 + RW_FWID_A@0x4c6fc0% 0x40 } RW_SECTION_B@0x9f7000 0x4c7000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4b6fc0 - RW_FWID_B@0x4c6fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x4b6fc0 + RW_FWID_B@0x4c6fc0% 0x40 } BIOS_UNUSABLE@0xebe000 0x40000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/37317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfd1e68990a272fbde9a0238f8a8b75db1549b05 Gerrit-Change-Number: 37317 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: configs/config.ocp_tiogapass: Update config
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48675 ) Change subject: configs/config.ocp_tiogapass: Update config ...................................................................... configs/config.ocp_tiogapass: Update config Builtest DEBUG_RESOURCES and remove unnecessary external microcode binary inclusion. Change-Id: Ib3851f2d0bd5ee340b7b8b5fa6e1a55eac1491d6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M configs/config.ocp_tiogapass 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/48675/1 diff --git a/configs/config.ocp_tiogapass b/configs/config.ocp_tiogapass index ca0a5b7..e14bc24 100644 --- a/configs/config.ocp_tiogapass +++ b/configs/config.ocp_tiogapass @@ -1,5 +1,4 @@ CONFIG_VENDOR_OCP=y CONFIG_BOARD_OCP_TIOGAPASS=y -CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y -CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y -CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04" +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_DEBUG_RESOURCES=y \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/48675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3851f2d0bd5ee340b7b8b5fa6e1a55eac1491d6 Gerrit-Change-Number: 48675 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: [TEST ONLY]hermes: Open LPC MMIO window
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48659 ) Change subject: [TEST ONLY]hermes: Open LPC MMIO window ...................................................................... [TEST ONLY]hermes: Open LPC MMIO window Change-Id: I41c34058e954af112aad6eb102efc5c32a0dc7b2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/mainboard.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48659/1 diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index b24dd56..b9222a3 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -1,10 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/mmio.h> +#include <console/console.h> +#include <intelblocks/lpc_lib.h> +#include <soc/pci_devs.h> #include <device/device.h> #include "gpio.h" /* FIXME: Example code below */ +#define LPC_MMIO_RANGE (0xfc800000 - 0x10000) + static void mb_configure_dp1_pwr(bool enable) { gpio_output(GPP_K3, enable); @@ -65,6 +71,15 @@ gpio_output(GPP_G4, enable); } +static void mainboard_init(struct device *dev) +{ + printk(BIOS_ERR, "BMC MMIO: read32(%x) = %x\n", LPC_MMIO_RANGE, read32((void *)LPC_MMIO_RANGE)); + printk(BIOS_ERR, "BMC MMIO: write32(%x, 0xdeadbeef)\n", LPC_MMIO_RANGE); + write32((void *)LPC_MMIO_RANGE, 0xdeadbeef); + printk(BIOS_ERR, "BMC MMIO: read32(%x) = %x\n", LPC_MMIO_RANGE, read32((void *)LPC_MMIO_RANGE)); + +} + static void mainboard_enable(struct device *dev) { /* FIXME: Do runtime configuration once the board is production ready */ @@ -82,6 +97,11 @@ mb_usb31_fp_pwr_enable(1); mb_usb2_fp1_pwr_enable(1); mb_usb2_fp2_pwr_enable(1); + + dev->ops->init = mainboard_init; + + lpc_open_mmio_window(LPC_MMIO_RANGE, 0x10000); + } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/48659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41c34058e954af112aad6eb102efc5c32a0dc7b2 Gerrit-Change-Number: 48659 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: [WIP]security: Add option to lock regions for SMMSTORE
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40829 ) Change subject: [WIP]security: Add option to lock regions for SMMSTORE ...................................................................... [WIP]security: Add option to lock regions for SMMSTORE On many server boards the flash is updateable out of band using the BMC and the bios region doesn't need to be writeable except for the SMM_STORE. Add an option to write-protect the COREBOOT and FMAP region. UNTESTED. Change-Id: I1096be9650f2af3e886f12f7db50c5060e0d40e1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/security/lockdown/lockdown.c 2 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/40829/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index 30b5237..d24c5e5 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -72,6 +72,23 @@ is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. by the payload or the OS). +config BOOTMEDIA_LOCK_COREBOOT_FMAP_RO + depends on BOOTMEDIA_LOCK_CONTROLLER + bool "Write-protect COREBOOT and FMAP region in boot medium" + help + Select this if you want to write-protect the COREBOOT and FMAP region + as specified in the FMAP. You will be able to write every region outside + of COREBOOT and FMAP using the internal controller (eg. SMM_STORE). + + The locking will take place during the chipset lockdown. + Chipset lockdown is platform specific und might be done unconditionally, + when INTEL_CHIPSET_LOCKDOWN is set or has to be triggered later + (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to update coreboot using the internal + controller any more. + endchoice config BOOTMEDIA_LOCK_IN_VERSTAGE diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c index 62d0a29..b4698d7 100644 --- a/src/security/lockdown/lockdown.c +++ b/src/security/lockdown/lockdown.c @@ -28,8 +28,11 @@ } else if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = CTRLR_WP; + } else if (CONFIG(BOOTMEDIA_LOCK_COREBOOT_FMAP_RO)) { + printk(BIOS_DEBUG, "'COREBOOT and FMAP'"); + lock_type = CTRLR_WP; } - printk(BIOS_DEBUG, "using CTRL...\n"); + printk(BIOS_DEBUG, " using CTRL...\n"); } else { if (CONFIG(BOOTMEDIA_LOCK_WHOLE_RO)) { printk(BIOS_DEBUG, "'readonly'"); @@ -38,7 +41,7 @@ printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = MEDIA_WP; } - printk(BIOS_DEBUG, "using flash chip...\n"); + printk(BIOS_DEBUG, " using flash chip...\n"); } if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { @@ -46,6 +49,11 @@ printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n"); else rdev = &dev; + } else if (CONFIG(BOOTMEDIA_LOCK_COREBOOT_FMAP_RO)) { + if (fmap_locate_area_as_rdev("COREBOOT", &dev) < 0) + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'COREBOOT'\n"); + else + rdev = &dev; } else { rdev = boot_device_ro(); } @@ -54,6 +62,15 @@ printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection\n"); else printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection\n"); + + if (CONFIG(BOOTMEDIA_LOCK_COREBOOT_FMAP_RO)) { + if (fmap_locate_area_as_rdev("FMAP", &dev) < 0) + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'FMAP'\n"); + else if (boot_device_wp_region(&dev, lock_type) >= 0) + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection\n"); + else + printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection\n"); + } } static void lock(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/40829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1096be9650f2af3e886f12f7db50c5060e0d40e1 Gerrit-Change-Number: 40829 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub
by Philipp Hug (Code Review) 10 Jun '23

10 Jun '23

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41826 ) Change subject: WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub ...................................................................... WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub Set PchTraceHubMode and CpuTraceHubMode if TraceHubMode is set. To use Intel DCI: * enable the following PCI devices 14.1 xDCI and 1f.7 Trace Hub * set the TraceHubMode to 2 in the devicetree for remote debugging * set CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT=3 in KConfig TODO=Add documentation TEST=Tested on lemp9, debugging works Change-Id: I86e2aff3002a8d2a9e4d121cafaef79aa3ee981b Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/41826/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a30f732..f7f8828 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -335,6 +335,21 @@ enum serirq_mode serirq_mode; + /* + * TraceHubMode config + * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode + */ + uint8_t TraceHubMode; + + /* Debug interface selection */ + enum { + DEBUG_INTERFACE_RAM = (1 << 0), + DEBUG_INTERFACE_UART_8250IO = (1 << 1), + DEBUG_INTERFACE_USB3 = (1 << 3), + DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_TRACEHUB = (1 << 5), + } debug_interface_flag; + /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c1afd1e..8a8168b 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -67,8 +67,16 @@ * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub * BIT2 - Not used. */ - m_cfg->PcdDebugInterfaceFlags = - CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; + + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -- To view, visit https://review.coreboot.org/c/coreboot/+/41826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86e2aff3002a8d2a9e4d121cafaef79aa3ee981b Gerrit-Change-Number: 41826 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

2 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2021