Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48629 )
Change subject: add a command to write SR1 ......................................................................
add a command to write SR1
Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com Change-Id: Ic4f74173b3e74b352b2dcff63d8c2c132cc6fe6f Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/drivers/spi/spi_flash.c M src/include/spi_flash.h M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/jasperlake/romstage/romstage.c 5 files changed, 80 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/48629/1
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f2610a1..acdcc19 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -530,6 +530,14 @@ return -1; }
+int spi_flash_wr_status(const struct spi_flash *flash, u8 value) +{ + if (flash->ops->wr_status) + return flash->ops->wr_status(flash, value); + + return -1; +} + int spi_flash_is_write_protected(const struct spi_flash *flash, const struct region *region) { diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 1061e99..9d53911 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -47,6 +47,7 @@ const void *buf); int (*erase)(const struct spi_flash *flash, u32 offset, size_t len); int (*status)(const struct spi_flash *flash, u8 *reg); + int (*wr_status)(const struct spi_flash *flash, u8 value); };
/* Current code assumes all callbacks are supplied in this object. */ @@ -144,6 +145,7 @@ const void *buf); int spi_flash_erase(const struct spi_flash *flash, u32 offset, size_t len); int spi_flash_status(const struct spi_flash *flash, u8 *reg); +int spi_flash_wr_status(const struct spi_flash *flash, u8 value);
/* * Return the vendor dependent SPI flash write protection state. diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index bafe131..67e660d 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -53,6 +53,7 @@ #define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) #define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) #define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) +#define SPIBAR_HSFSTS_CYCLE_WR_STATUS SPIBAR_HSFSTS_FCYCLE(7)
#define SPIBAR_HSFSTS_FGO (1 << 16) #define SPIBAR_HSFSTS_FLOCKDN (1 << 15) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index da99490..f7945d9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -243,6 +243,24 @@ return SUCCESS; }
+static int fast_spi_status_write(const struct spi_flash *flash, uint8_t value) +{ + int ret; + uint8_t val = value; + size_t xfer_len = sizeof(uint8_t); + + BOILERPLATE_CREATE_CTX(ctx); + + fill_xfer_fifo(ctx, (void *) &val, xfer_len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WR_STATUS, + 0, xfer_len); + if (ret != SUCCESS) + return ret; + + return SUCCESS; +} + static int fast_spi_flash_status(const struct spi_flash *flash, uint8_t *reg) { @@ -263,6 +281,7 @@ .write = fast_spi_flash_write, .erase = fast_spi_flash_erase, .status = fast_spi_flash_status, + .wr_status = fast_spi_status_write, };
/* diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 1fa6c2d..64d5014 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -14,6 +14,11 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <spi_flash.h> +#include <region_file.h> +#include <fmap.h> + +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
#define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -120,6 +125,48 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); }
+static void save_and_restore_sr1(void) +{ + int i; + u8 spi_sts1, spi_sts2; + const struct spi_flash *spi = boot_device_spi_flash(); + struct region_device rdev; + struct region_file cache_file; + const char *name = "RW_LEGACY"; + const uint32_t invalid = ~MRC_DATA_SIGNATURE; + + if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) { + printk(BIOS_ERR, "SR save/res: Couldn't find '%s' region. Invalidation failed\n", + name); + return; + } + + if (region_file_init(&cache_file, &rdev) < 0) { + printk(BIOS_ERR, "SR save/res: region file invalid for '%s'. Invalidation failed\n", + name); + return; + } + + for (i=0; i < 500; i++) { + spi_flash_status(spi, &spi_sts1); + printk(BIOS_DEBUG, "SPI_STATUS before write: 0x%x\n", spi_sts1); + + spi_flash_wr_status (spi, 0x00); + spi_flash_status(spi, &spi_sts2); + printk(BIOS_DEBUG, "SPI_STATUS after 0x0: 0x%x\n", spi_sts2); + + printk(BIOS_DEBUG, "SPI_STATUS Updating RW_LEGACY\n"); + /* Push an update that consists of 4 bytes that is smaller than the + * MRC metadata as well as an invalid signature. */ + if (region_file_update_data(&cache_file, &invalid, sizeof(invalid)) < 0) + printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); + + spi_flash_wr_status (spi, spi_sts1); + spi_flash_status(spi, &spi_sts2); + printk(BIOS_DEBUG, "SPI_STATUS after restore: 0x%x\n", spi_sts2); + } +} + void mainboard_romstage_entry(void) { bool s3wake; @@ -133,6 +180,9 @@ heci_init(HECI1_BASE_ADDRESS);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; + + save_and_restore_sr1(); + fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48629 )
Change subject: add a command to write SR1 ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48629/1/src/soc/intel/jasperlake/ro... File src/soc/intel/jasperlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48629/1/src/soc/intel/jasperlake/ro... PS1, Line 150: for (i=0; i < 500; i++) { spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/48629/1/src/soc/intel/jasperlake/ro... PS1, Line 154: spi_flash_wr_status (spi, 0x00); space prohibited between function name and open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48629/1/src/soc/intel/jasperlake/ro... PS1, Line 164: spi_flash_wr_status (spi, spi_sts1); space prohibited between function name and open parenthesis '('
Ravishankar Sarawadi has uploaded a new patch set (#2) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/48629 )
Change subject: add a command to write SR1 ......................................................................
add a command to write SR1
Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com Change-Id: Ic4f74173b3e74b352b2dcff63d8c2c132cc6fe6f Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/drivers/spi/spi_flash.c M src/include/spi_flash.h M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c 6 files changed, 133 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/48629/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48629 )
Change subject: add a command to write SR1 ......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/c/coreboot/+/48629/2/src/soc/intel/jasperlake/ro... File src/soc/intel/jasperlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48629/2/src/soc/intel/jasperlake/ro... PS2, Line 150: for (i=0; i < 500; i++) { spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/48629/2/src/soc/intel/jasperlake/ro... PS2, Line 154: spi_flash_wr_status (spi, 0x00); space prohibited between function name and open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48629/2/src/soc/intel/jasperlake/ro... PS2, Line 164: spi_flash_wr_status (spi, spi_sts1); space prohibited between function name and open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48629/2/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48629/2/src/soc/intel/tigerlake/rom... PS2, Line 151: for (i=0; i < 500; i++) { spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/48629/2/src/soc/intel/tigerlake/rom... PS2, Line 155: spi_flash_wr_status (spi, 0x00); space prohibited between function name and open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48629/2/src/soc/intel/tigerlake/rom... PS2, Line 165: spi_flash_wr_status (spi, spi_sts1); space prohibited between function name and open parenthesis '('
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48629?usp=email )
Change subject: add a command to write SR1 ......................................................................
Abandoned
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build bot (Jenkins) (Code Review) -
Ravishankar Sarawadi (Code Review)
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Rizwan Qureshi (Code Review)
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Stefan Reinauer (Code Review)