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Change in coreboot[master]: soc/amd: move southbridge_smi_handler to common code
by build bot (Jenkins) (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50463 ) Change subject: soc/amd: move southbridge_smi_handler to common code ...................................................................... Patch Set 1: (2 comments) File src/soc/amd/picasso/smihandler.c: https://review.coreboot.org/c/coreboot/+/50463/comment/6a884c65_30bdccaf PS1, Line 235: } adding a line without newline at end of file File src/soc/amd/stoneyridge/smihandler.c: https://review.coreboot.org/c/coreboot/+/50463/comment/bbf94eac_df8ac549 PS1, Line 230: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/50463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I650498321736eee3d33af51216eda1b650f11744 Gerrit-Change-Number: 50463 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 02:44:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: include cpu/x86/smm dircetory in common SMM Makefile
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50464 ) Change subject: soc/amd: include cpu/x86/smm dircetory in common SMM Makefile ...................................................................... soc/amd: include cpu/x86/smm dircetory in common SMM Makefile Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78 --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/cpu/smm/Makefile.inc M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc 4 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/50464/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 3501282..e6bccc3 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm # Beware that all-y also adds the compilation unit to verstage on PSP all-y += config.c diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc index c881522..df54d93 100644 --- a/src/soc/amd/common/block/cpu/smm/Makefile.inc +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) +subdirs-y += ../../../../../../cpu/x86/smm + ramstage-y += smm_relocate.c smm-y += smi_handler.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ddab522..d81eddc 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae -subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage # Beware that all-y also adds the compilation unit to verstage on PSP diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index f711c3a..856f6e6 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae -subdirs-y += ../../../cpu/x86/smm bootblock-y += uart.c bootblock-y += BiosCallOuts.c -- To view, visit https://review.coreboot.org/c/coreboot/+/50464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78 Gerrit-Change-Number: 50464 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: move southbridge_smi_handler to common code
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50463 ) Change subject: soc/amd: move southbridge_smi_handler to common code ...................................................................... soc/amd: move southbridge_smi_handler to common code Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I650498321736eee3d33af51216eda1b650f11744 --- M src/soc/amd/cezanne/smihandler.c M src/soc/amd/common/block/cpu/smm/Makefile.inc A src/soc/amd/common/block/cpu/smm/smi_handler.c M src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 6 files changed, 61 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/50463/1 diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index 2d9e487..b941293 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <cpu/x86/smm.h> +#include <amdblocks/smm.h> -void southbridge_smi_handler(void) +void *get_smi_source_handler(int source) { + return NULL; } diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc index 0639890..c881522 100644 --- a/src/soc/amd/common/block/cpu/smm/Makefile.inc +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) ramstage-y += smm_relocate.c +smm-y += smi_handler.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/common/block/cpu/smm/smi_handler.c b/src/soc/amd/common/block/cpu/smm/smi_handler.c new file mode 100644 index 0000000..00c03f0 --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/smi_handler.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> +#include <amdblocks/smm.h> +#include <cpu/x86/smm.h> +#include <soc/smi.h> + +static void process_smi_sources(uint32_t reg) +{ + const uint32_t status = smi_read32(reg); + int bit_zero = 32 / sizeof(uint32_t) * (reg - SMI_REG_SMISTS0); + void (*source_handler)(void); + int i; + + for (i = 0 ; i < 32 ; i++) { + if (status & (1 << i)) { + source_handler = get_smi_source_handler(i + bit_zero); + if (source_handler) + source_handler(); + } + } + + if (reg == SMI_REG_SMISTS0) + if (status & GEVENT_MASK) + /* Gevent[23:0] are assumed to be mainboard-specific */ + mainboard_smi_gpi(status & GEVENT_MASK); + + /* Clear all events in this register */ + smi_write32(reg, status); +} + +void southbridge_smi_handler(void) +{ + const uint16_t smi_src = smi_read16(SMI_REG_POINTER); + + if (smi_src & SMI_STATUS_SRC_SCI) + /* Clear events to prevent re-entering SMI if event isn't handled */ + clear_smi_sci_status(); + if (smi_src & SMI_STATUS_SRC_0) + process_smi_sources(SMI_REG_SMISTS0); + if (smi_src & SMI_STATUS_SRC_1) + process_smi_sources(SMI_REG_SMISTS1); + if (smi_src & SMI_STATUS_SRC_2) + process_smi_sources(SMI_REG_SMISTS2); + if (smi_src & SMI_STATUS_SRC_3) + process_smi_sources(SMI_REG_SMISTS3); + if (smi_src & SMI_STATUS_SRC_4) + process_smi_sources(SMI_REG_SMISTS4); +} diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h index 0fbef42..637f034 100644 --- a/src/soc/amd/common/block/include/amdblocks/smm.h +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -10,3 +10,4 @@ void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); +void *get_smi_source_handler(int source); diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 626daad..77bdaea 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -15,6 +15,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/psp.h> #include <amdblocks/smi.h> +#include <amdblocks/smm.h> #include <elog.h> #include <soc/smu.h> @@ -222,7 +223,7 @@ { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, }; -static void *get_source_handler(int source) +void *get_smi_source_handler(int source) { int i; @@ -231,47 +232,4 @@ return smi_sources[i].handler; return NULL; -} - -static void process_smi_sources(uint32_t reg) -{ - const uint32_t status = smi_read32(reg); - int bit_zero = 32 / sizeof(uint32_t) * (reg - SMI_REG_SMISTS0); - void (*source_handler)(void); - int i; - - for (i = 0 ; i < 32 ; i++) { - if (status & (1 << i)) { - source_handler = get_source_handler(i + bit_zero); - if (source_handler) - source_handler(); - } - } - - if (reg == SMI_REG_SMISTS0) - if (status & GEVENT_MASK) - /* Gevent[23:0] are assumed to be mainboard-specific */ - mainboard_smi_gpi(status & GEVENT_MASK); - - /* Clear all events in this register */ - smi_write32(reg, status); -} - -void southbridge_smi_handler(void) -{ - const uint16_t smi_src = smi_read16(SMI_REG_POINTER); - - if (smi_src & SMI_STATUS_SRC_SCI) - /* Clear events to prevent re-entering SMI if event isn't handled */ - clear_smi_sci_status(); - if (smi_src & SMI_STATUS_SRC_0) - process_smi_sources(SMI_REG_SMISTS0); - if (smi_src & SMI_STATUS_SRC_1) - process_smi_sources(SMI_REG_SMISTS1); - if (smi_src & SMI_STATUS_SRC_2) - process_smi_sources(SMI_REG_SMISTS2); - if (smi_src & SMI_STATUS_SRC_3) - process_smi_sources(SMI_REG_SMISTS3); - if (smi_src & SMI_STATUS_SRC_4) - process_smi_sources(SMI_REG_SMISTS4); -} +} \ No newline at end of file diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index ffcbaea..ca0f792 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -14,6 +14,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> #include <amdblocks/smi.h> +#include <amdblocks/smm.h> #include <elog.h> /* bits in smm_io_trap */ @@ -217,7 +218,7 @@ { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, }; -static void *get_source_handler(int source) +void *get_smi_source_handler(int source) { int i; @@ -226,47 +227,4 @@ return smi_sources[i].handler; return NULL; -} - -static void process_smi_sources(uint32_t reg) -{ - const uint32_t status = smi_read32(reg); - int bit_zero = 32 / sizeof(uint32_t) * (reg - SMI_REG_SMISTS0); - void (*source_handler)(void); - int i; - - for (i = 0 ; i < 32 ; i++) { - if (status & (1 << i)) { - source_handler = get_source_handler(i + bit_zero); - if (source_handler) - source_handler(); - } - } - - if (reg == SMI_REG_SMISTS0) - if (status & GEVENT_MASK) - /* Gevent[23:0] are assumed to be mainboard-specific */ - mainboard_smi_gpi(status & GEVENT_MASK); - - /* Clear all events in this register */ - smi_write32(reg, status); -} - -void southbridge_smi_handler(void) -{ - const uint16_t smi_src = smi_read16(SMI_REG_POINTER); - - if (smi_src & SMI_STATUS_SRC_SCI) - /* Clear events to prevent re-entering SMI if event isn't handled */ - clear_smi_sci_status(); - if (smi_src & SMI_STATUS_SRC_0) - process_smi_sources(SMI_REG_SMISTS0); - if (smi_src & SMI_STATUS_SRC_1) - process_smi_sources(SMI_REG_SMISTS1); - if (smi_src & SMI_STATUS_SRC_2) - process_smi_sources(SMI_REG_SMISTS2); - if (smi_src & SMI_STATUS_SRC_3) - process_smi_sources(SMI_REG_SMISTS3); - if (smi_src & SMI_STATUS_SRC_4) - process_smi_sources(SMI_REG_SMISTS4); -} +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/50463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I650498321736eee3d33af51216eda1b650f11744 Gerrit-Change-Number: 50463 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50415 ) Change subject: soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util ...................................................................... soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50415 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 3 files changed, 7 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Marshall Dawson: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index 1e4561d..e3379f3 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -65,6 +65,13 @@ smi_write32(SMI_REG_SMITRIG0, reg); } +void southbridge_smi_set_eos(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_EOS; + smi_write32(SMI_REG_SMITRIG0, reg); +} + void soc_route_sci(uint8_t event) { smi_write8(SMI_SCI_MAP(event), event); diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 4931de8..faf4f7b 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -293,10 +293,3 @@ if (smi_src & SMI_STATUS_SRC_4) process_smi_sources(SMI_REG_SMISTS4); } - -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); -} diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index c8a113c..45dd07d 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -288,10 +288,3 @@ if (smi_src & SMI_STATUS_SRC_4) process_smi_sources(SMI_REG_SMISTS4); } - -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/50415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779 Gerrit-Change-Number: 50415 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/stoneyridge: Move some SMI utility functions
by Kyösti Mälkki (Code Review) 09 Feb '21

09 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42989 ) Change subject: soc/amd/stoneyridge: Move some SMI utility functions ...................................................................... soc/amd/stoneyridge: Move some SMI utility functions Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/gpio.c D src/soc/amd/stoneyridge/smi.c M src/soc/amd/stoneyridge/smi_util.c M src/soc/amd/stoneyridge/smihandler.c 5 files changed, 22 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42989/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 0d7b5d1..09320b2 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -64,7 +64,6 @@ ramstage-y += pmutil.c ramstage-y += sata.c ramstage-y += memmap.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index a595014..bd9d1b1 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -33,11 +33,6 @@ { GPIO_69, GEVENT_17 }, }; -void soc_route_sci(uint8_t event) -{ - smi_write8(SMI_SCI_MAP(event), event); -} - void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) { *table = gpio_event_table; diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c deleted file mode 100644 index fb6d348..0000000 --- a/src/soc/amd/stoneyridge/smi.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Utilities for SMM setup - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <amdblocks/acpimmio.h> -#include <soc/southbridge.h> -#include <soc/smi.h> - -/** Set the EOS bit and enable SMI generation from southbridge */ -void global_smi_enable(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ - reg |= SMITRG0_EOS; /* Set EOS bit */ - smi_write32(SMI_REG_SMITRIG0, reg); -} diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 2c5085b..b65bfc0 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> @@ -56,6 +57,27 @@ smi_write32(SMI_REG_SMITRIG0, reg32); } +/** Set the EOS bit and enable SMI generation from southbridge */ +void global_smi_enable(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ + reg |= SMITRG0_EOS; /* Set EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void southbridge_smi_set_eos(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_EOS; + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void soc_route_sci(uint8_t event) +{ + smi_write8(SMI_SCI_MAP(event), event); +} + /** * Configure generation of SCIs. */ diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index be55458..a36ab73 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -287,10 +287,3 @@ if (smi_src & SMI_STATUS_SRC_4) process_smi_sources(SMI_REG_SMISTS4); } - -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Gerrit-Change-Number: 42989 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Move some SMI utility functions
by Kyösti Mälkki (Code Review) 09 Feb '21

09 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42988 ) Change subject: soc/amd/picasso: Move some SMI utility functions ...................................................................... soc/amd/picasso: Move some SMI utility functions Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/gpio.c D src/soc/amd/picasso/smi.c M src/soc/amd/picasso/smi_util.c M src/soc/amd/picasso/smihandler.c 5 files changed, 22 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42988/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..9a72d60 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -61,7 +61,6 @@ ramstage-y += acp.c ramstage-y += sata.c ramstage-y += memmap.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index c402fb5..47c005e 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -33,11 +33,6 @@ { GPIO_129, GEVENT_17 }, }; -void soc_route_sci(uint8_t event) -{ - smi_write8(SMI_SCI_MAP(event), event); -} - void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) { *table = gpio_event_table; diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c deleted file mode 100644 index fb6d348..0000000 --- a/src/soc/amd/picasso/smi.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Utilities for SMM setup - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <amdblocks/acpimmio.h> -#include <soc/southbridge.h> -#include <soc/smi.h> - -/** Set the EOS bit and enable SMI generation from southbridge */ -void global_smi_enable(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ - reg |= SMITRG0_EOS; /* Set EOS bit */ - smi_write32(SMI_REG_SMITRIG0, reg); -} diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 2c5085b..b65bfc0 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> @@ -56,6 +57,27 @@ smi_write32(SMI_REG_SMITRIG0, reg32); } +/** Set the EOS bit and enable SMI generation from southbridge */ +void global_smi_enable(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ + reg |= SMITRG0_EOS; /* Set EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void southbridge_smi_set_eos(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_EOS; + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void soc_route_sci(uint8_t event) +{ + smi_write8(SMI_SCI_MAP(event), event); +} + /** * Configure generation of SCIs. */ diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 992dc2b..a9a2b2e 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -291,10 +291,3 @@ if (smi_src & SMI_STATUS_SRC_4) process_smi_sources(SMI_REG_SMISTS4); } - -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075 Gerrit-Change-Number: 42988 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/amd/picasso: Move APM_CNT_SMMINFO callsite
by Kyösti Mälkki (Code Review) 09 Feb '21

09 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42987 ) Change subject: soc/amd/picasso: Move APM_CNT_SMMINFO callsite ...................................................................... soc/amd/picasso: Move APM_CNT_SMMINFO callsite Triggering SMI is not part of the semantics of global_smi_enable(). Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/smi.c 2 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/42987/1 diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index c42f400..6c6149f 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -85,12 +85,18 @@ smm_state->smbase = staggered_smbase; } +static void post_mp_init(void) +{ + global_smi_enable(); + apm_control(APM_CNT_SMMINFO); +} + static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .relocation_handler = relocation_handler, - .post_mp_init = global_smi_enable, + .post_mp_init = post_mp_init, }; void mp_init_cpus(struct bus *cpu_bus) diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index 125dde6..fb6d348 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -4,7 +4,6 @@ * Utilities for SMM setup */ -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <amdblocks/acpimmio.h> @@ -18,6 +17,4 @@ reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); - - outb(APM_CNT_SMMINFO, APM_CNT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d Gerrit-Change-Number: 42987 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/amd: factor out common SMM relocation code
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50462 ) Change subject: soc/amd: factor out common SMM relocation code ...................................................................... soc/amd: factor out common SMM relocation code The common code gets moved to soc/amd/common/block/cpu/smm, since it is related to the CPU cores and soc/amd/common/block/smi is about the SMI/ SCI functionality in the FCH part. Also relocation_handler gets renamed to smm_relocation_handler to keep it clear what it does, since it got moved to another compilation unit. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/cpu/Kconfig A src/soc/amd/common/block/cpu/smm/Makefile.inc A src/soc/amd/common/block/cpu/smm/smm_relocate.c A src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/cpu.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/cpu.c 9 files changed, 79 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/50462/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 6e844c2..7bd9873 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -31,6 +31,7 @@ select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SSE2 diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index c155975..996605e 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -28,6 +28,12 @@ endif # SOC_AMD_COMMON_BLOCK_NONCAR +config SOC_AMD_COMMON_BLOCK_SMM + bool + default n + help + Add common SMM relocation and handler functionality to the build. + config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H bool select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc new file mode 100644 index 0000000..0639890 --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) + +ramstage-y += smm_relocate.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c new file mode 100644 index 0000000..1d7cc68 --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/smm.h> +#include <console/console.h> +#include <cpu/amd/amd64_save_state.h> +#include <cpu/amd/msr.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> +#include <types.h> + +static struct smm_relocation_params smm_reloc_params; + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); + params->tseg_base.hi = 0; + params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); + params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); + + params->tseg_mask.lo |= SMM_TSEG_WB; +} + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); +} + +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) +{ + struct smm_relocation_params *relo_params = &smm_reloc_params; + amd64_smm_state_save_area_t *smm_state; + + wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); + wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); + + smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); + smm_state->smbase = staggered_smbase; +} diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h new file mode 100644 index 0000000..0fbef42 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <types.h> + +struct smm_relocation_params { + msr_t tseg_base; + msr_t tseg_mask; +}; + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4868d84..f504d09 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -42,6 +42,7 @@ select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 8ee065d..088660e 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> +#include <amdblocks/smm.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/amd64_save_state.h> #include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> @@ -22,12 +21,6 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_params { - msr_t tseg_base; - msr_t tseg_mask; -}; - -static struct smm_relocation_params smm_reloc_params; /* * Do essential initialization tasks before APs can be fired up - @@ -42,45 +35,6 @@ x86_mtrr_check(); } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - smm_region(&tseg_base, &tseg_size); - - params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); - params->tseg_base.hi = 0; - params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); - params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - - params->tseg_mask.lo |= SMM_TSEG_WB; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - amd64_smm_state_save_area_t *smm_state; - - wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); - wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); - - smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - static void post_mp_init(void) { global_smi_enable(); @@ -91,7 +45,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, - .relocation_handler = relocation_handler, + .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b400e1b..728e063 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_UART select SSE2 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 9992fc5..badea8b 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/smm.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/amd64_save_state.h> #include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> @@ -21,12 +20,6 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_params { - msr_t tseg_base; - msr_t tseg_mask; -}; - -static struct smm_relocation_params smm_reloc_params; /* * Do essential initialization tasks before APs can be fired up - @@ -47,50 +40,11 @@ + 1; } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - smm_region(&tseg_base, &tseg_size); - - params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); - params->tseg_base.hi = 0; - params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); - params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - - params->tseg_mask.lo |= SMM_TSEG_WB; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - amd64_smm_state_save_area_t *smm_state; - - wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); - wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); - - smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, - .relocation_handler = relocation_handler, + .relocation_handler = smm_relocation_handler, .post_mp_init = global_smi_enable, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/50462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb Gerrit-Change-Number: 50462 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace
by Kyösti Mälkki (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: HAOUAS Elyes. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50461 ) Change subject: sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Split from CB:45862. -- To view, visit https://review.coreboot.org/c/coreboot/+/50461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b40dc5b6f54bf68113826e693ca5963fec83d38 Gerrit-Change-Number: 50461 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 10 Feb 2021 00:50:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace
by Kyösti Mälkki (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: HAOUAS Elyes. Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50461 to review the following change. Change subject: sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace ...................................................................... sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace Make it look more like the file under amd/pi/hudson. Change-Id: I5b40dc5b6f54bf68113826e693ca5963fec83d38 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/agesa/hudson/acpi/fch.asl 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/50461/1 diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 7777d72..400f15f 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -7,14 +7,14 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) CDW1 |= 4 // Unrecognized UUID - Return(Arg3) + Return (Arg3) } } @@ -129,7 +129,7 @@ Local0 -= TOM1 MM1L = Local0 - Return(CRES) /* note to change the Name buffer */ + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ #if CONFIG(HUDSON_IMC_FWM) @@ -170,21 +170,21 @@ Method(OSFL, 0){ - if (OSVR != Ones) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */ if (CondRefOf(\_OSI)) { - OSVR = 1 /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { OSVR = 2 } } else { - If(WCMP(\_OS,"Linux")) { - OSVR = 3 /* Linux */ + If (WCMP(\_OS,"Linux")) { + OSVR = 3 /* Linux */ } Else { - OSVR = 4 /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } - Return(OSVR) + Return (OSVR) } -- To view, visit https://review.coreboot.org/c/coreboot/+/50461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b40dc5b6f54bf68113826e693ca5963fec83d38 Gerrit-Change-Number: 50461 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021