Attention is currently required from: YH Lin, Tim Wawrzynczak.
Hello YH Lin, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60022
to look at the new patch set (#3).
Change subject: mb/google/brya/var/taeko: Add define SOC_INTEL_ALDERLAKE_PCH_P in Kconfig.name
......................................................................
mb/google/brya/var/taeko: Add define SOC_INTEL_ALDERLAKE_PCH_P in Kconfig.name
We occurred an issue on taeko and brya that FW versions after 14388
will fail to boot up.
After adding SOC_INTEL_ALDERLAKE_PCH_P in Kconfig.name we can solve
this issue.
BUG=b:210089175
TEST=emerge-brya coreboot and can boot up taeko successfully.
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: Ic58f8fee87559f2d5ad107ca3c9da882e4eb2381
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60022/3
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Attention is currently required from: YH Lin, Tim Wawrzynczak.
Hello YH Lin, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60022
to look at the new patch set (#2).
Change subject: mb/google/brya/var/taeko: Add SOC_INTEL_ALDERLAKE_PCH_P token in Kconfig.name
......................................................................
mb/google/brya/var/taeko: Add SOC_INTEL_ALDERLAKE_PCH_P token in Kconfig.name
We occurred an issue on taeko and brya that FW versions after 14388
will fail to boot up.
After adding SOC_INTEL_ALDERLAKE_PCH_P in Kconfig.name we can solve
this issue.
BUG=b:210089175
TEST=emerge-brya coreboot and can boot up taeko successfully.
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: Ic58f8fee87559f2d5ad107ca3c9da882e4eb2381
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60022/2
--
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Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60022 )
Change subject: mb/google/brya/var/taeko: Add SOC_INTEL_ALDERLAKE_PCH_P token in Kconfig.name
......................................................................
mb/google/brya/var/taeko: Add SOC_INTEL_ALDERLAKE_PCH_P token in Kconfig.name
We occurred an issue on taeko and brya that FW versions after 14388
will fail to boot up and bios boot logs will show Cannot find PCIE
Root port 5 and PCIE Root port 9.
After adding SOC_INTEL_ALDERLAKE_PCH_P in Kconfig.name we can solve
this issue.
BUG=b:210089175
TEST=emerge-brya coreboot and can boot up taeko successfully.
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: Ic58f8fee87559f2d5ad107ca3c9da882e4eb2381
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60022/1
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index ead3348..1498e09 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -98,11 +98,13 @@
bool "-> Taeko"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9763E
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_GOOGLE_TAEKO4ES
bool "-> Taeko4ES"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9763E
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_GOOGLE_FELWINTER
bool "-> Felwinter"
--
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59334 )
Change subject: mb/google/brya/var/vell: update memory settings
......................................................................
Patch Set 14:
(1 comment)
File src/mainboard/google/brya/variants/vell/memory.c:
https://review.coreboot.org/c/coreboot/+/59334/comment/a9fe0ce4_086b9e18
PS12, Line 68:
> Done
Still no change?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58603 )
Change subject: [RFC]cpu/x86/mp_init.c: Copy BSP chip_info to AP devices
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/58603/comment/1e06fe79_728cada6
PS1, Line 392: new->chip_info = info->cpu->chip_info;
> > Technically, different chips would be the case on multi-socket systems. […]
To me it's the same thing. There is not supposed to be a difference.
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Change subject: mb/google/brya/var/vell: update memory settings
......................................................................
Patch Set 13:
(3 comments)
File src/mainboard/google/brya/variants/vell/memory.c:
https://review.coreboot.org/c/coreboot/+/59334/comment/83c7624b_40f34ac9
PS12, Line 16: .targets = {40, 36, 35, 35, 35},
> Below there is a space after/before the brackets. Please make it consistent.
Done
https://review.coreboot.org/c/coreboot/+/59334/comment/82631db8_492a3d11
PS12, Line 67: 1
> Sorry I don't see any changes?
Done
https://review.coreboot.org/c/coreboot/+/59334/comment/ee154e90_e6fb490c
PS12, Line 68:
> Sorry I don't see any changes?
Done
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Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
Patch Set 17:
(3 comments)
File src/mainboard/google/brya/variants/vell/gpio.c:
https://review.coreboot.org/c/coreboot/+/59305/comment/46cbb39c_2947faef
PS15, Line 13: PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
> no need for this, already set as such in brya baseboard gpio. […]
Done
https://review.coreboot.org/c/coreboot/+/59305/comment/6c37ae9a_cd32760c
PS15, Line 45: PAD_CFG_GPI(GPP_E17, NONE, DEEP),
> no need for this, already set as such in brya baseboard gpio. […]
Done
https://review.coreboot.org/c/coreboot/+/59305/comment/fe95ce9c_36a6a35c
PS15, Line 90: PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
> no need for this, already set as such in brya baseboard gpio. […]
Done
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