coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/cannonlake: Configure common FSP memory settings only once
by Paul Menzel (Code Review) 12 Dec '21

12 Dec '21

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60058 ) Change subject: soc/intel/cannonlake: Configure common FSP memory settings only once ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Gerrit-Change-Number: 60058 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 12 Dec 2021 14:08:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Add define SOC_INTEL_ALDERLAKE_PCH_P in Kco...
by Felix Singer (Code Review) 12 Dec '21

12 Dec '21

Attention is currently required from: Joey Peng, Tim Wawrzynczak. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60022 ) Change subject: mb/google/brya/var/taeko: Add define SOC_INTEL_ALDERLAKE_PCH_P in Kconfig.name ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60022/comment/da8ad9cf_6d29f2d6 PS4, Line 7: mb/google/brya/var/taeko: Add define SOC_INTEL_ALDERLAKE_PCH_P in Kconfig.name How about: mb/google/brya/{taeko,taeko4es}: Select SOC_INTEL_ALDERLAKE_PCH_P -- To view, visit https://review.coreboot.org/c/coreboot/+/60022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic58f8fee87559f2d5ad107ca3c9da882e4eb2381 Gerrit-Change-Number: 60022 Gerrit-PatchSet: 4 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sun, 12 Dec 2021 13:28:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Configure common FSP memory settings only once
by Felix Singer (Code Review) 12 Dec '21

12 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60058 ) Change subject: soc/intel/cannonlake: Configure common FSP memory settings only once ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60058/comment/414c4cc8_2c1b0a9c PS2, Line 10: dimm > nit: DIMM Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Gerrit-Change-Number: 60058 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 12 Dec 2021 13:24:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Configure common FSP memory settings only once
by Felix Singer (Code Review) 12 Dec '21

12 Dec '21

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60058 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Configure common FSP memory settings only once ...................................................................... soc/intel/cannonlake: Configure common FSP memory settings only once `meminit_memcfg()` does common memory configuration, which is not specific to each DIMM. Thus, move it out of the for-loop and call it once. Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/cnl_memcfg_init.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/60058/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Gerrit-Change-Number: 60058 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Rename SA_DEV_SLOT_DSP
by Felix Singer (Code Review) 12 Dec '21

12 Dec '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60049 ) Change subject: soc/intel/cannonlake: Rename SA_DEV_SLOT_DSP ...................................................................... soc/intel/cannonlake: Rename SA_DEV_SLOT_DSP Device 4 was introduced with a wrong name, since it is the SA Thermal Subsystem and it does nothing have to do with DSP. Thus, rename it accordingly. Change-Id: I8edc764413df5f323098e60d0a3f0f87a7e656cb Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60049 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/pci_devs.h 2 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 32c5cbb..fc12890 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -59,9 +59,9 @@ }, }, { - .slot = SA_DEV_SLOT_DSP, + .slot = SA_DEV_SLOT_TS, .fns = { - ANY_PIRQ(SA_DEVFN_DSP), + ANY_PIRQ(SA_DEVFN_TS), }, }, { diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 50ba611..6998eb1 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -34,9 +34,9 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) -#define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) -#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) +#define SA_DEV_SLOT_TS 0x04 +#define SA_DEVFN_TS PCI_DEVFN(SA_DEV_SLOT_TS, 0) +#define SA_DEV_TS PCI_DEV(0, SA_DEV_SLOT_TS, 0) #define SA_DEV_SLOT_IPU 0x05 #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/60049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8edc764413df5f323098e60d0a3f0f87a7e656cb Gerrit-Change-Number: 60049 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cannonlake: Configure common FSP memory settings only once
by Angel Pons (Code Review) 12 Dec '21

12 Dec '21

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60058 ) Change subject: soc/intel/cannonlake: Configure common FSP memory settings only once ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60058/comment/e33eeb63_8b0a46b5 PS2, Line 10: dimm nit: DIMM -- To view, visit https://review.coreboot.org/c/coreboot/+/60058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Gerrit-Change-Number: 60058 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 12 Dec 2021 13:21:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Configure common FSP memory settings only once
by Felix Singer (Code Review) 12 Dec '21

12 Dec '21

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60058 to look at the new patch set (#2). Change subject: soc/intel/cannonlake: Configure common FSP memory settings only once ...................................................................... soc/intel/cannonlake: Configure common FSP memory settings only once `meminit_memcfg()` does common memory configuration, which is not specific to each dimm. Thus, move it out of the for-loop and call it once. Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/cnl_memcfg_init.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/60058/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Gerrit-Change-Number: 60058 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Call `meminit_memcfg()` only once
by Felix Singer (Code Review) 12 Dec '21

12 Dec '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60058 ) Change subject: soc/intel/cannonlake: Call `meminit_memcfg()` only once ...................................................................... soc/intel/cannonlake: Call `meminit_memcfg()` only once `meminit_memcfg()` does common memory configuration, which is not specific to each dimm. Thus, move it out of the for-loop and call it once. Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/cnl_memcfg_init.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/60058/1 diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index a9f9e95..448e56c 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -136,7 +136,7 @@ default: die("no valid way to read mem info"); } - - meminit_memcfg(mem_cfg, cnl_cfg); } + + meminit_memcfg(mem_cfg, cnl_cfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Gerrit-Change-Number: 60058 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/U-Boot: Fix various build errors
by Paul Menzel (Code Review) 12 Dec '21

12 Dec '21

Attention is currently required from: Bill XIE, Martin Roth, Stefan Reinauer, Simon Glass. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60028 ) Change subject: payloads/U-Boot: Fix various build errors ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60028/comment/6cb2d741_014a4744 PS2, Line 9: Target of U-Boot payload is inconsistent between Kconfig and : Makefile.inc. : : Perform full clone in order to get tags. : : Make Kconfig prompt for revision consistent with the revision : in Makefile. Format it as a list? -- To view, visit https://review.coreboot.org/c/coreboot/+/60028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0f11c16274456a452a0422e19fab0c61d8b5d5b Gerrit-Change-Number: 60028 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Comment-Date: Sun, 12 Dec 2021 11:34:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/Makefile.inc: Add warning for image built with no payload
by Paul Menzel (Code Review) 12 Dec '21

12 Dec '21

Attention is currently required from: Nicholas Chin. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60025 ) Change subject: payloads/Makefile.inc: Add warning for image built with no payload ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057 Gerrit-Change-Number: 60025 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin Gerrit-Comment-Date: Sun, 12 Dec 2021 11:32:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021