coreboot-gerrit December 2021

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Change in coreboot[master]: mainboard: Fix DPTF device state in the devicetree on CFL boards
by Felix Singer (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Tim Crawford, Patrick Rudolph, Jeremy Soller, Tim Wawrzynczak, Christian Walter. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60203 ) Change subject: mainboard: Fix DPTF device state in the devicetree on CFL boards ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I tested this on a google/dratini. 00:04. […] Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/60203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I561598c252c5da64ece569c6ba336852e713ccab Gerrit-Change-Number: 60203 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Tue, 21 Dec 2021 23:51:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add options to separate signed firmwares
by Karthik Ramasubramanian (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59866 ) Change subject: amdfwtool: Add options to separate signed firmwares ...................................................................... Patch Set 2: (1 comment) File util/amdfwtool/amdfwtool.h: https://review.coreboot.org/c/coreboot/+/59866/comment/6f6d7f04_a4ef0e16 PS2, Line 225: amd_fw_header > Directly from the AMD. […] Please refer to the bug here for details: b/203597980#comment4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Gerrit-Change-Number: 59866 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Dec 2021 23:45:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variant/taniks: Add devicetree settings
by Tim Wawrzynczak (Code Review) 22 Dec '21

22 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59998 ) Change subject: mb/google/brya/variant/taniks: Add devicetree settings ...................................................................... mb/google/brya/variant/taniks: Add devicetree settings Based on schematic G570_MB_CHROME_1207_1630_ADC and gpio table of taniks, generate overridetree.cb settings for taniks. BUG=b:209926534 TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/taniks/Makefile.inc A src/mainboard/google/brya/variants/taniks/fw_config.c M src/mainboard/google/brya/variants/taniks/overridetree.cb 3 files changed, 515 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taniks/Makefile.inc b/src/mainboard/google/brya/variants/taniks/Makefile.inc index 7d1f886..6947beb 100644 --- a/src/mainboard/google/brya/variants/taniks/Makefile.inc +++ b/src/mainboard/google/brya/variants/taniks/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/taniks/fw_config.c b/src/mainboard/google/brya/variants/taniks/fw_config.c new file mode 100644 index 0000000..8a7c6b4 --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/fw_config.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */ + +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_NC(GPP_R7, NONE), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98357_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index 4f2c04a..deb31ce 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -1,6 +1,462 @@ +fw_config + field DB_USB 0 1 + option DB_USB_ABSENT 0 + option DB_USB3_WITH_A 1 + end + field DB_SD 2 3 + option DB_SD_ABSENT 0 + option DB_SD_OZ711LV2LN 1 + option DB_SD_GL9750 2 + option DB_SD_RTS5232S 3 + end + field KB_BL 4 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 5 7 + option AUDIO_UNKNOWN 0 + option AUDIO_MAX98357_ALC5682I_I2S 1 + end + field KB_LAYOUT 8 9 + option KB_LAYOUT_DEFAULT 0 + end + field WIFI_SAR_ID 10 11 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 + option WIFI_SAR_ID_2 2 + option WIFI_SAR_ID_3 3 + end + field BOOT_NVME_MASK 12 + option BOOT_NVME_DISABLED 0 + option BOOT_NVME_ENABLED 1 + end + field BOOT_EMMC_MASK 13 + option BOOT_EMMC_DISABLED 0 + option BOOT_EMMC_ENABLED 1 + end +end chip soc/intel/alderlake + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + register "TcssAuxOri" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "SaGv" = "SaGv_Enabled" - device domain 0 on - end + register "PsysPmax" = "145" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" #DB Type-A Port A1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" # USB3/2 Type A port A1 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 74), + TEMP_PCT(75, 74), + TEMP_PCT(70, 74), + TEMP_PCT(65, 74), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(51, 74), + TEMP_PCT(47, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 45), + TEMP_PCT(37, 35), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(51, 74), + TEMP_PCT(47, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 45), + TEMP_PCT(37, 35), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(51, 74), + TEMP_PCT(47, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 45), + TEMP_PCT(37, 35), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 12000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 74, 4620, 115, 1150, }, + [4] = { 60, 4290, 90, 900, }, + [5] = { 45, 3980, 55, 550, }, + [6] = { 35, 3170, 30, 300, }, + [7] = { 30, 2640, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + }" + end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO AUDIO_MAX98357_ALC5682I_I2S + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + # Parameter T5 >= 180ms + register "generic.reset_delay_ms" = "180" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + # Parameter T1 >= 20ms + register "generic.enable_delay_ms" = "20" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "20" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO AUDIO_MAX98357_ALC5682I_I2S + end + end + end + device ref pcie_rp5 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp6 off end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on + probe DB_SD DB_SD_OZ711LV2LN + probe DB_SD DB_SD_GL9750 + probe DB_SD DB_SD_RTS5232S + end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + device generic 2 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port3 on + probe DB_USB DB_USB3_WITH_A + end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port3 on + probe DB_USB DB_USB3_WITH_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(7, 1)" + device ref usb2_port7 on + probe DB_USB DB_USB3_WITH_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(9, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(9, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(7, 1)" + device ref usb3_port3 on + probe DB_USB DB_USB3_WITH_A + end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/59998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6 Gerrit-Change-Number: 59998 Gerrit-PatchSet: 6 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variant/taniks: Add devicetree settings
by Tim Wawrzynczak (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: YH Lin, Joey Peng, Paul Menzel, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59998 ) Change subject: mb/google/brya/variant/taniks: Add devicetree settings ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6 Gerrit-Change-Number: 59998 Gerrit-PatchSet: 5 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 21 Dec 2021 23:23:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/herobrine: Update GPIOs to Proto1
by Shelley Chen (Code Review) 22 Dec '21

22 Dec '21

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60285 ) Change subject: mb/google/herobrine: Update GPIOs to Proto1 ...................................................................... mb/google/herobrine: Update GPIOs to Proto1 Update all the BOARD_GOOGLE_HEROBRINE GPIOs to those of the Proto1 board. BUG=b:211644878 BRANCH=NONE TEST=emerge-herobrine coreboot Change-Id: Iebf1d00a0ccbbc97a5bcb821a0ee1b6289e0a2ce Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/board.h M src/mainboard/google/herobrine/mainboard.c 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/60285/1 diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h index 4278c11..e13f84c 100644 --- a/src/mainboard/google/herobrine/board.h +++ b/src/mainboard/google/herobrine/board.h @@ -22,9 +22,9 @@ /* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices. */ #if CONFIG(HEROBRINE_HAS_FINGERPRINT) -#define GPIO_FPMCU_BOOT0 GPIO(77) +#define GPIO_FPMCU_BOOT0 (CONFIG(BOARD_GOOGLE_HEROBRINE_PROTO0) ? GPIO(77) : GPIO(68)) #define GPIO_FP_RST_L GPIO(78) -#define GPIO_EN_FP_RAILS GPIO(42) +#define GPIO_EN_FP_RAILS (CONFIG(BOARD_GOOGLE_HEROBRINE_PROTO0) ? GPIO(42) : GPIO(77)) #else #define GPIO_FPMCU_BOOT0 dead_code_t(gpio_t) #define GPIO_FP_RST_L dead_code_t(gpio_t) diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index f2432d9..aea88c9 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -75,6 +75,15 @@ qupv3_se_fw_load_and_init(QUPV3_1_SE4, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */ qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_SPI, MIXED); + } else { /* BOARD_GOOGLE_HEROBRINE */ + /* Trackpad I2C */ + qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); + /* SAR sensor I2C */ + qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); + /* Audio I2C */ + qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); + /* Fingerprint SPI */ + qupv3_se_fw_load_and_init(QUPV3_1_SE1, SE_PROTOCOL_SPI, MIXED); } /* Take FPMCU out of reset. Power was already applied -- To view, visit https://review.coreboot.org/c/coreboot/+/60285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebf1d00a0ccbbc97a5bcb821a0ee1b6289e0a2ce Gerrit-Change-Number: 60285 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_PR...
by Shelley Chen (Code Review) 22 Dec '21

22 Dec '21

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60284 ) Change subject: mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_PROTO0 ...................................................................... mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_PROTO0 Deprecating Herobrine Proto0 board. The Proto board is very different from the Proto0 board (ie: Most GPIOs have been remapped). Deprecating and reusing the GOOGLE_BOARD_HEROBRINE Kconfig for Proto1 and reslotting the old GOOGLE_BOARD_HEROBRINE source under GOOGLE_BOARD_HEROBRINE_PROTO0 config. Want to keep the code around in case somebody needs it but we can remove this code in future after we recall all the Proto0 devices. BUG=b:211644878 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I67a0b282710031b927ce9022c7c535bd8d4ca1aa Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/herobrine/Kconfig.name M src/mainboard/google/herobrine/mainboard.c 3 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/60284/1 diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index c4c943e..f724a52 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -47,6 +47,7 @@ config MAINBOARD_PART_NUMBER default "Herobrine" if BOARD_GOOGLE_HEROBRINE + default "Herobrine_Proto0" if BOARD_GOOGLE_HEROBRINE_PROTO0 default "Senor" if BOARD_GOOGLE_SENOR default "Piglin" if BOARD_GOOGLE_PIGLIN default "Hoglin" if BOARD_GOOGLE_HOGLIN diff --git a/src/mainboard/google/herobrine/Kconfig.name b/src/mainboard/google/herobrine/Kconfig.name index c0e995c..706e0d6 100644 --- a/src/mainboard/google/herobrine/Kconfig.name +++ b/src/mainboard/google/herobrine/Kconfig.name @@ -6,6 +6,10 @@ bool "-> Herobrine" select BOARD_GOOGLE_HEROBRINE_COMMON +config BOARD_GOOGLE_HEROBRINE_PROTO0 + bool "-> Herobrine_Proto0" + select BOARD_GOOGLE_HEROBRINE_COMMON + config BOARD_GOOGLE_SENOR bool "-> Senor" select BOARD_GOOGLE_HEROBRINE_COMMON diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index a2e0786..f2432d9 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -59,7 +59,7 @@ qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* Touch I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE7, SE_PROTOCOL_UART, FIFO); /* BT UART */ - if (CONFIG(BOARD_GOOGLE_HEROBRINE)) { + if (CONFIG(BOARD_GOOGLE_HEROBRINE_PROTO0)) { /* Audio I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67a0b282710031b927ce9022c7c535bd8d4ca1aa Gerrit-Change-Number: 60284 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Enable vboot integration
by Julius Werner (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Jakub Czapiga, Jan Dabros, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60080 ) Change subject: libpayload: Enable vboot integration ...................................................................... Patch Set 5: (4 comments) File payloads/libpayload/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/60080/comment/8ad84b3d_8e42fcd4 PS5, Line 5: menu "Verified boot (vboot)" You don't have a menu for CBFS so I don't think you should have one here either. (Instead, if you want to make things look a little prettier in menuconfig, you could indent the dependent options a bit, e.g. "-> TPM2 Mode" or something like that.) https://review.coreboot.org/c/coreboot/+/60080/comment/adb39aaa_74d74af5 PS5, Line 22: config VBOOT_TEST_PRINT Now you took VBOOT_DEBUG out but added this? We shouldn't need any of this. Just always enable debug messages. There is no reason to do anything special for ARCH_MOCK here. (Unit tests here are still the libpayload/depthcharge unit tests, not the vboot unit tests, so the vboot code called by them is still just firmware code that calls vb2ex_printf() and not printf() directly. libpayload/depthcharge can then decide whether that callback actually prints something or not with their own unit test printing configs.) File payloads/libpayload/vboot/Makefile.inc: https://review.coreboot.org/c/coreboot/+/60080/comment/adf7a8f7_b5e29e91 PS3, Line 23: VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 > I intentionally left it without any check, because I wanted to allow building vboot for ARCH_MOCK. […] Ack File payloads/libpayload/vboot/Makefile.inc: https://review.coreboot.org/c/coreboot/+/60080/comment/a6e429a8_e6d585cc PS5, Line 47: $(VBOOT_BUILD_DIR)/vboot_fw.a Why not just use the `fwlib` target here? -- To view, visit https://review.coreboot.org/c/coreboot/+/60080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d9d766a461edaa0081041c020ecf580fd2ca64e Gerrit-Change-Number: 60080 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 21 Dec 2021 22:58:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeOS: Refactor ACPI CNVS generation
by Tim Wawrzynczak (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Furquan Shaikh, Marshall Dawson, Nick Vaccaro, Julius Werner, Kyösti Mälkki, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55502 ) Change subject: ChromeOS: Refactor ACPI CNVS generation ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Gerrit-Change-Number: 55502 Gerrit-PatchSet: 18 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Dec 2021 22:46:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeOS: Refactor ACPI CNVS generation
by Tim Wawrzynczak (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Furquan Shaikh, Marshall Dawson, Nick Vaccaro, Julius Werner, Kyösti Mälkki, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55502 ) Change subject: ChromeOS: Refactor ACPI CNVS generation ...................................................................... Patch Set 18: (2 comments) Patchset: PS15: > > just assumptions about the paths involved, snippets from dmesg: […] You are correct about \_SB, spec says: `All Device/Bus Objects are defined under this namespace` However, let's please fix one thing at a time 😊 This code is pretty old now and someone would also need to push a kernel patch upstream to apply the same fix to the chromeos ACPI kernel driver and I would need to make sure they land in our tree at the same time so as not to break everybody working on ToT. File src/vendorcode/google/chromeos/gnvs.c: https://review.coreboot.org/c/coreboot/+/55502/comment/fc9641c1_f8a4340f PS10, Line 115: .acpi_inject_dsdt = chromeos_dsdt_generator, > Good eye... […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Gerrit-Change-Number: 55502 Gerrit-PatchSet: 18 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Dec 2021 22:46:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/libc/fmap: Implement new FlashMap API
by Julius Werner (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Jakub Czapiga. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59494 ) Change subject: libpayload/libc/fmap: Implement new FlashMap API ...................................................................... Patch Set 9: Code-Review+2 (1 comment) Patchset: PS7: > Ok, I know, what is happening here. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Gerrit-Change-Number: 59494 Gerrit-PatchSet: 9 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Tue, 21 Dec 2021 22:43:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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