coreboot-gerrit December 2021

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Change in coreboot[master]: [WIP] mb/google/guybrush: enable amdfw separation
by Kangheui Won (Code Review) 22 Dec '21

22 Dec '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60292 ) Change subject: [WIP] mb/google/guybrush: enable amdfw separation ...................................................................... [WIP] mb/google/guybrush: enable amdfw separation Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I332e6b84362c12ff3b437db46788d2c27da9af0a --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/chromeos.fmd 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/60292/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index ded66ab..fa864cc 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -55,6 +55,10 @@ bool "Enable PSP_verstage" default y if VBOOT +config SEPARATE_SIGNED_AMDFW + bool "Separate signed amd fw from FW_MAIN region" + default y if VBOOT + config VBOOT_STARTS_IN_BOOTBLOCK bool default y if VBOOT && !VBOOT_STARTS_BEFORE_BOOTBLOCK diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd index a6dbc2c..a0d2fef 100644 --- a/src/mainboard/google/guybrush/chromeos.fmd +++ b/src/mainboard/google/guybrush/chromeos.fmd @@ -2,11 +2,13 @@ SI_BIOS { RW_MRC_CACHE(PRESERVE) 64K RW_SECTION_A 3M { + SIGNED_AMDFW_A 1M VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 256 } RW_SECTION_B 3M { + SIGNED_AMDFW_B 1M VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 256 -- To view, visit https://review.coreboot.org/c/coreboot/+/60292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I332e6b84362c12ff3b437db46788d2c27da9af0a Gerrit-Change-Number: 60292 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: pass psp fw hash table
by Kangheui Won (Code Review) 22 Dec '21

22 Dec '21

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Change in coreboot[master]: amdfwtool: generate hashes for signed fw
by Kangheui Won (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60290 ) Change subject: amdfwtool: generate hashes for signed fw ...................................................................... amdfwtool: generate hashes for signed fw Generate SHA256/SHA384 hash of the signed firmware so we can pass it to the PSP. The PSP will use these hashes to verify that those signed firmwares are what we integrated. BUG=b:203597980 TEST=build guybrush Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 --- M src/soc/amd/cezanne/Makefile.inc M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 5 files changed, 154 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/60290/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 69f78f1..c6a1e68 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -305,6 +305,19 @@ build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed + +cbfs-files-y += apu/amdfw_a_hash +apu/amdfw_a_hash-file := $(obj)/amdfw_a.rom.signed.hash +apu/amdfw_a_hash-type := raw + +$(obj)/amdfw_a.rom.signed.hash: $(obj)/amdfw_a.rom + +cbfs-files-y += apu/amdfw_b_hash +apu/amdfw_b_hash-file := $(obj)/amdfw_b.rom.signed.hash +apu/amdfw_b_hash-type := raw + +$(obj)/amdfw_b.rom.signed.hash: $(obj)/amdfw_b.rom + endif # CONFIG_SEPARATE_SIGNED_AMDFW endif diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index 1805459..03f0e1e 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -8,6 +8,10 @@ WERROR=-Werror -Wno-unused-function CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} +HOSTPKGCONFIG ?= pkg-config +CFLAGS += $(shell $(HOSTPKGCONFIG) --cflags libcrypto 2>/dev/null) +LDFLAGS += $(shell $(HOSTPKGCONFIG) --libs libcrypto 2>/dev/null) + all: $(TARGET) $(TARGET): $(OBJ) diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc index f772299..64b3af4 100644 --- a/util/amdfwtool/Makefile.inc +++ b/util/amdfwtool/Makefile.inc @@ -4,9 +4,14 @@ AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Werror -Wno-unused-function +HOSTPKGCONFIG ?= pkg-config + +AMDFWTOOLCFLAGS += $(shell $(HOSTPKGCONFIG) --cflags libcrypto 2>/dev/null) +LDFLAGS += $(shell $(HOSTPKGCONFIG) --libs libcrypto 2>/dev/null) + $(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER) $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< $(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) printf " AMDFWTOOL\n" - $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) -o $@ + $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) $(LDFLAGS) -o $@ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 3cd207a..22f2ad3 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -48,6 +48,7 @@ #include <fcntl.h> #include <errno.h> +#include <openssl/sha.h> #include <stdbool.h> #include <stdio.h> #include <sys/stat.h> @@ -569,6 +570,47 @@ return psp_id; } +static int add_sha(amd_fw_entry *entry, void *buf) +{ + uint8_t hash[SHA384_DIGEST_LENGTH]; + SHA256_CTX sha256; + SHA512_CTX sha384; + struct amd_fw_header *header = (struct amd_fw_header *)buf; + size_t len = header->size_total - sizeof(struct amd_fw_header); + uint8_t *body = (uint8_t *)buf + sizeof(struct amd_fw_header); + + /* Exclude signature at the end of file from hash calculation. + * sig_id == 2 -> SHA384, RSA4096 is used + * sig_id == 2 -> SHA256, RSA2048 is used + */ + if (header->sig_id == 2) + len -= 0x200; + else if (header->sig_id == 0) + len -= 0x100; + else + return -1; + + if (len > header->size_total) + return -1; + + if (header->sig_id == 2) { + SHA384_Init(&sha384); + SHA384_Update(&sha384, body, len); + SHA384_Final(hash, &sha384); + entry->sha_len = SHA384_DIGEST_LENGTH; + } else if (header->sig_id == 0) { + SHA256_Init(&sha256); + SHA256_Update(&sha256, body, len); + SHA256_Final(hash, &sha256); + entry->sha_len = SHA256_DIGEST_LENGTH; + } + + memcpy(entry->sha, hash, entry->sha_len); + entry->subtype = header->fw_subtype; + + return 0; +} + static void integrate_firmwares(context *ctx, embedded_firmware *romsig, amd_fw_entry *fw_table) @@ -660,6 +702,69 @@ } } +static void write_or_fail(int fd, void *ptr, size_t size) +{ + ssize_t written; + written = write(fd, ptr, size); + if (written > 0) { + size -= written; + if (size) + size -= write(fd, (uint8_t *)ptr + written, size); + } + + if (size) { + fprintf(stderr, "Error writing to file: %s\n", strerror(errno)); + exit(-1); + } +} + +static void write_psp_firmware_hash(const char *filename, + amd_fw_entry *fw_table) +{ + unsigned int i; + struct psp_fw_hash_table hash_header; + int fd = open(filename, O_RDWR | O_CREAT | O_TRUNC, 0666); + + if (fd < 0) { + fprintf(stderr, "Error opening file: %s: %s\n", + filename, strerror(errno)); + exit(-1); + } + + memset(&hash_header, 0, sizeof(hash_header)); + + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + if (fw_table[i].sha_len == SHA256_DIGEST_LENGTH) + hash_header.no_of_entries_256++; + else if (fw_table[i].sha_len == SHA384_DIGEST_LENGTH) + hash_header.no_of_entries_384++; + } + + write_or_fail(fd, &hash_header, sizeof(hash_header)); + + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + if (fw_table[i].sha_len == SHA256_DIGEST_LENGTH) { + uint16_t type = fw_table[i].type; + uint16_t subtype = fw_table[i].subtype; + write_or_fail(fd, &type, sizeof(type)); + write_or_fail(fd, &subtype, sizeof(subtype)); + write_or_fail(fd, fw_table[i].sha, SHA256_DIGEST_LENGTH); + } + } + + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + if (fw_table[i].sha_len == SHA384_DIGEST_LENGTH) { + uint16_t type = fw_table[i].type; + uint16_t subtype = fw_table[i].subtype; + write_or_fail(fd, &type, sizeof(type)); + write_or_fail(fd, &subtype, sizeof(subtype)); + write_or_fail(fd, fw_table[i].sha, SHA384_DIGEST_LENGTH); + } + } + + close(fd); +} + static void process_signed_psp_firmwares(const char *signed_rom, amd_fw_entry *fw_table, uint64_t signed_start_addr) @@ -669,6 +774,7 @@ int signed_rom_fd; ssize_t bytes; uint8_t *buf; + char *signed_rom_hash; struct amd_fw_header header; struct stat fd_stat; @@ -760,6 +866,9 @@ } } + if (add_sha(&fw_table[i], buf)) + exit(-1); + fw_table[i].addr_signed = signed_start_addr; fw_table[i].file_size = (uint32_t)fd_stat.st_size; @@ -770,6 +879,16 @@ } close(signed_rom_fd); + + signed_rom_hash = malloc(strlen(signed_rom) + 6); + if (!signed_rom_hash) { + fprintf(stderr, "malloc(%lu) failed\n", strlen(signed_rom) + 6); + exit(-1); + } + strcpy(signed_rom_hash, signed_rom); + strcat(signed_rom_hash, ".hash"); + write_psp_firmware_hash(signed_rom_hash, fw_table); + free(signed_rom_hash); } static void integrate_psp_firmwares(context *ctx, diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 9ea0b29..9c9bb63 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -237,12 +237,15 @@ #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) typedef struct _amd_fw_entry { amd_fw_type type; + uint8_t subtype; char *filename; uint8_t subprog; int level; uint64_t other; uint64_t addr_signed; uint32_t file_size; + uint8_t sha[48]; + uint32_t sha_len; } amd_fw_entry; struct amd_fw_header { @@ -267,6 +270,15 @@ uint8_t reserved_80[128]; } __attribute__((packed)); +struct psp_fw_hash_table { + uint16_t version; + uint16_t no_of_entries_256; + uint16_t no_of_entries_384; + /* These two are pointers but the PSP is 32-bit only. */ + uint32_t fw_hash_256; + uint32_t fw_hash_384; +} __attribute__((packed)); + typedef struct _amd_cb_config { bool have_whitelist; bool unlock_secure; -- To view, visit https://review.coreboot.org/c/coreboot/+/60290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Gerrit-Change-Number: 60290 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: add svc_set_fw_hash_table
by Kangheui Won (Code Review) 22 Dec '21

22 Dec '21

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Change in coreboot[master]: soc/amd/cezanne: Separate signed amdfw
by Kangheui Won (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59867 to look at the new patch set (#5). Change subject: soc/amd/cezanne: Separate signed amdfw ...................................................................... soc/amd/cezanne: Separate signed amdfw Put signed amd firmwares into SIGNED_AMDFW_[AB] region which is outside FW_MAIN_[AB]. Vboot only verifies FW_MAIN_[AB] so these regions will not be verified by vboot; instead the PSP will verify them. As a result we have less to load and verify from SPI rom which means faster boot time. BUG=b:206909680 TEST=build guybrush with modified fmap and Kconfig Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: If4fd3cff11a38d82afb8c5ce379f1d1b5b9adfbf --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59867/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4fd3cff11a38d82afb8c5ce379f1d1b5b9adfbf Gerrit-Change-Number: 59867 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Add options to separate signed firmwares
by Kangheui Won (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Hello Jason Glenesk, build bot (Jenkins), Marshall Dawson, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59866 to look at the new patch set (#3). Change subject: amdfwtool: Add options to separate signed firmwares ...................................................................... amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another file. If sig_opt in file header is 1 it means that the firmware is signed by AMD and will be verified by the PSP. If we put them outside FW_MAIN_[AB] we can skip vboot verification on them, improving overall verification time. BUG=b:206909680 TEST=build amdfwtool Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 172 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59866/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Gerrit-Change-Number: 59866 Gerrit-PatchSet: 3 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add timestamp for cse_fw_sync
by Maulik V Vaghela (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Paul Menzel, Sridhar Siricilla, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60135 ) Change subject: soc/intel/alderlake: Add timestamp for cse_fw_sync ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Gerrit-Change-Number: 60135 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 04:38:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] ChromeOS: Move CRHW device object
by Kyösti Mälkki (Code Review) 22 Dec '21

22 Dec '21

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58421 ) Change subject: [WIP] ChromeOS: Move CRHW device object ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: Postponed, from CB:55502 You are correct about \_SB, spec says: > All Device/Bus Objects are defined under this namespace However, let's please fix one thing at a time 😊 This code is pretty old now and someone would also need to push a kernel patch upstream to apply the same fix to the chromeos ACPI kernel driver and I would need to make sure they land in our tree at the same time so as not to break everybody working on ToT. -- To view, visit https://review.coreboot.org/c/coreboot/+/58421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I449d0206fbaee94cea99f745cf297ad293e8306c Gerrit-Change-Number: 58421 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 04:02:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: Add Hynix LP5 DRAM support
by Kevin Chiu (Code Review) 22 Dec '21

22 Dec '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60288 ) Change subject: mb/google/brya/var/vell: Add Hynix LP5 DRAM support ...................................................................... mb/google/brya/var/vell: Add Hynix LP5 DRAM support Add Hynix H9JCNNNCP3MLYR-N6E LP5 DRAM part for vell: DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> --- M src/mainboard/google/brya/variants/vell/memory/Makefile.inc M src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/60288/1 diff --git a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc index 8288400..05f4689 100644 --- a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc @@ -5,4 +5,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B -SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt index f029f6b..2e3eb01 100644 --- a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt @@ -6,3 +6,4 @@ DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) +H9JCNNNCP3MLYR-N6E 1 (0001) diff --git a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt index 3baf5d4..f81efc5 100644 --- a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt @@ -11,3 +11,4 @@ # Part Name MT62F512M32D2DR-031 WT:B MT62F1G32D4DR-031 WT:B +H9JCNNNCP3MLYR-N6E -- To view, visit https://review.coreboot.org/c/coreboot/+/60288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e Gerrit-Change-Number: 60288 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ChromeOS: Refactor ACPI CNVS generation
by Kyösti Mälkki (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Nick Vaccaro, Julius Werner, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55502 ) Change subject: ChromeOS: Refactor ACPI CNVS generation ...................................................................... Patch Set 18: (1 comment) Patchset: PS15: > You are correct about \_SB, spec says: […] Of course. I think CB:58421 has the problematic \CRHW to \_SB.CRHW change now, and I don't mind delaying it, even indefinetely. -- To view, visit https://review.coreboot.org/c/coreboot/+/55502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Gerrit-Change-Number: 55502 Gerrit-PatchSet: 18 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 22 Dec 2021 03:56:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021