coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST
by Meera Ravindranath (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tim Wawrzynczak, Meera Ravindranath, Nick Vaccaro. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60320 to look at the new patch set (#4). Change subject: mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST ...................................................................... mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST During a warm reboot, if the GPIO is programmed as DEEP or PLTRST, the PAD_CFG_DW0 resets to default state while the GPIO lock configuration register resides in the reset type of RSMRST and cannot be modified (EDS:630603). This way, GPIO loses all the programmed values and coreboot cannot re program them due to the lock bit not being cleared. This prevents the enumeration of SD card and Touch pad after a warm reset. Hence, change GPIO_PAD_RST to RSMRST to sync both the resets. BUG=b:211573253 TEST=Boot to OS, issue warm reboot and see SD card and Touch pad enumerating. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/60320/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee Gerrit-Change-Number: 60320 Gerrit-PatchSet: 4 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jsl: Add CdClock config
by Angel Pons (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jsl: Add CdClock config ...................................................................... Patch Set 16: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60009/comment/33731f0f_b84f7e8c PS16, Line 7: CdClock nit: `CdClock frequency` https://review.coreboot.org/c/coreboot/+/60009/comment/811022c0_1fc010c3 PS16, Line 9: This dev tree config controls the CdClock for Jasper Lake. I'd reword and expand this a bit, stating what `CdClock` means and removing the redundant `for Jasper Lake` part (already in the summary as `soc/intel/jsl`): Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Patchset: PS16: After addressing my comments, LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 16 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 11:07:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/herobrine: Add support QUP FW for I2C and SPI
by Felix Singer (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Ravi kumar, Sudheer Amrabadi. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59556 ) Change subject: src/mainboard/herobrine: Add support QUP FW for I2C and SPI ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59556/comment/f08717b2_1ede45d3 PS5, Line 7: src/mainboard/herobrine mb/google/herobrine -- To view, visit https://review.coreboot.org/c/coreboot/+/59556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fdd09bb437547e6d12eb60c4b2917d2a3074618 Gerrit-Change-Number: 59556 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 11:06:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
by Angel Pons (Code Review) 23 Dec '21

23 Dec '21

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Change in coreboot[master]: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
by Angel Pons (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Henry Sun, Ren Kuo, Paul Menzel, Simon Yang, Kane Chen, Karthik Ramasubramanian. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60301 ) Change subject: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60301/comment/c2c01cb3_7a6f18b4 PS6, Line 9: With the default core display clock of 172.8 MHz,it improved the : stability of start up in Chrome OS in secure mode. : The rare fail system will not hang up in Chrome OS from secure mode. : The core display clock = 172.8 MHz in coreboot is form Intel's : recommendation. Hmmm, this paragraph is a bit confusing to understand. If I understand it correctly: - Magolor has a rare stability issue when booting ChromeOS in secure mode, where the system may hang. - Reducing the initial CD clock frequency to 172.8 MHz avoids this problem. If my understanding is correct, here's my suggestion: When using the default initial core display clock frequency, Magolor has a rare stability issue where the startup of Chrome OS in secure mode may hang. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommendation avoids this problem. https://review.coreboot.org/c/coreboot/+/60301/comment/003da546_c7c1e771 PS6, Line 18: Check the DUTs can boot up in secure mode. Out of curiosity, can the CdClk frequency be increased back to regular speeds when OS GFX drivers take over? -- To view, visit https://review.coreboot.org/c/coreboot/+/60301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Gerrit-Change-Number: 60301 Gerrit-PatchSet: 6 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 10:52:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jsl: Add CdClock config
by Angel Pons (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jsl: Add CdClock config ...................................................................... Patch Set 16: (4 comments) File src/mainboard/google/dedede/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/60009/comment/53e99b47_e5db9faf PS16, Line 208: # Core Display Clock Frequency selection : register "CdClock" = "0xff" With the changes I've suggested in my other comments, this is no longer needed. File src/soc/intel/jasperlake/chip.h: https://review.coreboot.org/c/coreboot/+/60009/comment/ef71ade3_933d8627 PS16, Line 411: 0xff: 648 MHz Looks like 0xff is the default setting (a value of 7 also specifies 648 MHz). However, the devicetree values default to 0 if unspecified, so 172.8 MHz CdClock would be used as default instead. One way to avoid this is to make the devicetree values +1 and handle a value of 0 as a special case. See comments in fsp_params.c on how to implement this. https://review.coreboot.org/c/coreboot/+/60009/comment/b2296532_8c182529 PS16, Line 408: /* : * Core Display Clock Frequency selection : * 0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz, : * 6: 556.8 MHz, 7: 648 MHz, 8: 652.8 MHz, 0xff: 648 MHz : */ : uint8_t CdClock; Why not use an enum? /* Core Display Clock Frequency selection, FSP values + 1 */ enum { CD_CLOCK_172_8_MHZ = 1, CD_CLOCK_180_MHZ = 2, CD_CLOCK_192_MHZ = 3, CD_CLOCK_307_MHZ = 4, CD_CLOCK_312_MHZ = 5, CD_CLOCK_552_MHZ = 6, CD_CLOCK_556_8_MHZ = 7, CD_CLOCK_648_MHZ = 8, CD_CLOCK_652_8_MHZ = 9, } cd_clock; Note that I've added 1 to the values to allow having a non-zero default value, see my other comments. Also note that I've shortened the comment, as the enum values' names already specify the corresponding frequency. File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/60009/comment/024c30ef_95a71312 PS16, Line 212: params->CdClock = config->CdClock; To handle non-zero default values: params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff; Note that I've renamed the devicetree setting to `cd_clock`, as it no longer has a 1:1 mapping to the `CdClock` FSP UPD. -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 16 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 10:37:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Add more Westmere/Ironlake device IDs
by Felix Singer (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Stefan Reinauer, Angel Pons, Michael Niewöhner, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60215 ) Change subject: util/inteltool: Add more Westmere/Ironlake device IDs ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60215/comment/52eb7f72_9591bef3 PS2, Line 8: Please add a document number where these IDs are documented. -- To view, visit https://review.coreboot.org/c/coreboot/+/60215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b Gerrit-Change-Number: 60215 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 23 Dec 2021 10:33:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: Update PL and PsysPL
by Curtis Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tim Wawrzynczak. Curtis Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60323 ) Change subject: mb/google/brya/var/brask: Update PL and PsysPL ...................................................................... mb/google/brya/var/brask: Update PL and PsysPL Update all the ADL-P 15W/28W/45W SKU's PL and PsysPL. These config values are generated iPDG application with ADL-P platform package tool. RDC Kit ID for the iPDG tools: * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Libraries: 613643 * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:211365920 BRANCH=none TEST=Compare the measured power from adapter with the value of 'psys' from the command 'dump_intel_rapl_consumption'. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: I4a827ae40e26294db20d5d1b2121dcce5118e290 --- M src/mainboard/google/brya/variants/brask/ramstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/60323/1 diff --git a/src/mainboard/google/brya/variants/brask/ramstage.c b/src/mainboard/google/brya/variants/brask/ramstage.c index f5105fe..c2a5ec3 100644 --- a/src/mainboard/google/brya/variants/brask/ramstage.c +++ b/src/mainboard/google/brya/variants/brask/ramstage.c @@ -10,20 +10,26 @@ const struct cpu_power_limits limits[] = { /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 45000, 45000, 95000, 95000, 125000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 45000, 45000, 115000, 115000, 215000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, }; const struct system_power_limits sys_limits[] = { /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 135 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 230 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/60323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a827ae40e26294db20d5d1b2121dcce5118e290 Gerrit-Change-Number: 60323 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Update the ADL-P SKU parameters for VR domains
by Curtis Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Curtis Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60322 ) Change subject: soc/intel/alderlake: Update the ADL-P SKU parameters for VR domains ...................................................................... soc/intel/alderlake: Update the ADL-P SKU parameters for VR domains We support all the ADL-P 15W/28W/45W SKU's and map thame with the latest VR configurations. These config values are generated iPDG application with ADL-P platform package tool. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Libraries: 613643 * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755 --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/vr_config.c 4 files changed, 49 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60322/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b6cb7d8..cddadd6 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4001,6 +4001,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_ID_7 0x4601 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_10 0x4619 #define PCI_DEVICE_ID_INTEL_ADL_M_ID_1 0x4602 #define PCI_DEVICE_ID_INTEL_ADL_M_ID_2 0x460a #define PCI_DEVICE_ID_INTEL_ADL_N_ID_1 0x4617 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 1003894..93d8eee 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -21,14 +21,14 @@ /* Types of different SKUs */ enum soc_intel_alderlake_power_limits { - ADL_P_282_CORE, + ADL_P_142_242_282_15W_CORE, ADL_P_482_28W_CORE, ADL_P_682_28W_CORE, - ADL_P_682_45W_CORE, + ADL_P_442_482_45W_CORE, + ADL_P_642_682_45W_CORE, ADL_M_282_12W_CORE, ADL_M_282_15W_CORE, ADL_M_242_CORE, - ADL_P_242_CORE, ADL_P_442_45W_CORE, ADL_POWER_LIMITS_COUNT }; @@ -48,12 +48,15 @@ enum soc_intel_alderlake_power_limits limits; enum soc_intel_alderlake_cpu_tdps cpu_tdp; } cpuid_to_adl[] = { - { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_CORE, TDP_15W }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_242_CORE, TDP_15W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_28W_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, ADL_P_442_45W_CORE, TDP_45W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index bacc025..c956fd4 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -2,7 +2,7 @@ device cpu_cluster 0 on end - register "power_limits_config[ADL_P_282_CORE]" = "{ + register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, .tdp_pl4 = 123, @@ -20,7 +20,13 @@ .tdp_pl4 = 140, }" - register "power_limits_config[ADL_P_682_45W_CORE]" = "{ + register "power_limits_config[ADL_P_442_482_45W_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 95, + .tdp_pl4 = 125, + }" + + register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, .tdp_pl4 = 215, @@ -42,18 +48,6 @@ .tdp_pl4 = 68, }" - register "power_limits_config[ADL_P_242_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 55, - .tdp_pl4 = 123, - }" - - register "power_limits_config[ADL_P_442_45W_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 95, - .tdp_pl4 = 125, - }" - # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 1964c12..dbc5f50 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -10,8 +10,7 @@ /* * VR Configurations for IA and GT domains for ADL-P SKU's. - * Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation - * for ADL-P 482(28W) and 442(45W). + * Per doc#627345 ADL_P Partial Intel PlatformDesignStudio Rev 2.0.0, update PD * * +----------------+-----------+-------+-------+---------+-------------+----------+ * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | @@ -19,11 +18,19 @@ * +----------------+-----------+-------+-------+---------+-------------+----------+ * | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 | * + +-----------+-------+-------+---------+-------------+----------+ - * | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | + * | | GT | 3.2 | 3.2 | 55 | 57 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ - * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 40 | 28000 | + * | ADL-P 482(45W) | IA | 2.3 | 2.3 | 120 | 47 | 28000 | + * + 442(45W) +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 3.2 | 3.2 | 55 | 47 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ADL-P 682(28W) | IA | 2.3 | 2.3 | 109 | 40 | 28000 | * + +-----------+-------+-------+---------+-------------+----------+ - * | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | + * | | GT | 3.2 | 3.2 | 55 | 40 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 32 | 28000 | + * + +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 3.2 | 3.2 | 55 | 32 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ * | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 | * + +-----------+-------+-------+---------+-------------+----------+ @@ -54,37 +61,49 @@ static const struct vr_lookup vr_config_ll[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, }; static const struct vr_lookup vr_config_icc[] = { - { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 50) }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 50) }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(111, 50) }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 50) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, }; static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, }; static const struct vr_lookup vr_config_tdc_currentlimit[] = { - { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, }; void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/60322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755 Gerrit-Change-Number: 60322 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Rename ADL_P_482_CORE to ADL_P_482_28W_CORE
by Curtis Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Kane Chen, Patrick Rudolph. Hello V Sowmya, build bot (Jenkins), Tim Wawrzynczak, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60267 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Rename ADL_P_482_CORE to ADL_P_482_28W_CORE ...................................................................... soc/intel/alderlake: Rename ADL_P_482_CORE to ADL_P_482_28W_CORE Every VR config items are not the same between ADL-P 4+8+2 28 & 45W. Now the exist setting is only for ADL-P 4+8+2 28W, so we rename it. BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: I863023eba5fda3b6d45059383d6030427913ca9a --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/60267/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I863023eba5fda3b6d45059383d6030427913ca9a Gerrit-Change-Number: 60267 Gerrit-PatchSet: 3 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021