coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

1 participants
5525 discussions

Change in coreboot[master]: sb/intel: Use `bool` for PCIe coalescing option
by Angel Pons (Code Review) 28 Dec '21

28 Dec '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60416 ) Change subject: sb/intel: Use `bool` for PCIe coalescing option ...................................................................... sb/intel: Use `bool` for PCIe coalescing option Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/optiplex_9010/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb M src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pch/pcie.c M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/pcie.c 42 files changed, 50 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60416/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 8f7573a..6ea033e 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -32,7 +32,7 @@ register "gen4_dec" = "0x00fc0701" register "gpi7_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1" device pci 16.0 on # Management Engine Interface 1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 93d37dc..0f7d0a8 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -38,7 +38,7 @@ register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index 9dcf2b7..0162547 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -6,7 +6,7 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" register "gen4_dec" = "0x0000ff29" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 device pci 1c.1 on end # PCIe Port 2 RTL8111F diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index b3b1a1c..6979615 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -37,7 +37,7 @@ register "gen3_dec" = "0x000406f1" register "gen4_dec" = "0x000c06a1" register "gpi7_routing" = "2" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" # Intense PC SATA portmap: # Port 0: internal 2.5" bay diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb index fd95081..ef0a0e3 100644 --- a/src/mainboard/dell/optiplex_9010/devicetree.cb +++ b/src/mainboard/dell/optiplex_9010/devicetree.cb @@ -28,7 +28,7 @@ register "gen2_dec" = "0x007c0901" register "gen3_dec" = "0x003c07e1" register "gen4_dec" = "0x001c0901" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x7" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 0570cdc..ad8e50c 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -33,7 +33,7 @@ register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 0a92efe..cfb4812 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -36,7 +36,7 @@ # Force enable ASPM for PCIe Port 3 register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013b0000" diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8c54f6a..8eada25 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -44,7 +44,7 @@ register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 725cbd1..c79526e 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -58,7 +58,7 @@ register "gen2_dec" = "0x00040381" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 08b2c95..e972baa 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -38,7 +38,7 @@ register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index fda74da..49c3476 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -56,7 +56,7 @@ register "gen2_dec" = "0x00fc0901" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index d748277..6850cf2 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -54,7 +54,7 @@ register "gen2_dec" = "0x00040069" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index ad700ce..b38adaf 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -61,7 +61,7 @@ register "gen3_dec" = "0x0001C1611" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 76d04d6..98e48ef 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -28,7 +28,7 @@ register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 3dd8825..2bfbacd 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -29,7 +29,7 @@ device pci 00.0 on end # Host bridge chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 5204e60..0de9cfa 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -28,7 +28,7 @@ register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index a878019..31bee5d 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -32,7 +32,7 @@ #register "gen4_dec" = "0x00000000" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 86205f8..6c2dabe 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -38,7 +38,7 @@ register "gpi13_routing" = "2" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3b" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 3c1fc9e..14d849d 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -36,7 +36,7 @@ register "gpi13_routing" = "2" register "gpi7_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x5" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 457ccbe..c934f5f 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -55,7 +55,7 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 32736a8..1d6adaf 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -57,7 +57,7 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 112dfe7..141faa9 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -35,7 +35,7 @@ register "gpi13_routing" = "2" register "gpi1_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x17" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 75a65f9..942f029 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -58,7 +58,7 @@ register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "docking_supported" = "1" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index a1e24d5..9c75231 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -55,7 +55,7 @@ register "gen4_dec" = "0x0c06a1" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index ffa0b93..5cfa207 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -52,7 +52,7 @@ register "gen4_dec" = "0x0c06a1" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index abe40b1..ee8a2e0 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -55,7 +55,7 @@ register "xhci_overcurrent_mapping" = "0x00000c03" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 30260b0..cbf1141 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -57,7 +57,7 @@ register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index b239d64..923c88b 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -55,7 +55,7 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 1f81311..30a7916 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -58,7 +58,7 @@ register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 6c97e1f..8e5df58 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -19,7 +19,7 @@ register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 8ba2697..6cb77e3 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -46,7 +46,7 @@ register "gpe0_en" = "0x00800040" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 7e5555b..2291f61 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -51,7 +51,7 @@ register "gpe0_en" = "0x00800040" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 876f920..d5f6fda 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -14,7 +14,7 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi.opprefixes" = "{ 0x50, 0x06 }" diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 49fcff5..284d8f3 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -20,7 +20,7 @@ register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h index 2164a31..84ad8fe 100644 --- a/src/soc/intel/broadwell/pch/chip.h +++ b/src/soc/intel/broadwell/pch/chip.h @@ -3,7 +3,7 @@ #ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_ #define _SOC_INTEL_BROADWELL_PCH_CHIP_H_ -#include <stdint.h> +#include <types.h> struct soc_intel_broadwell_pch_config { /* GPE configuration */ @@ -47,7 +47,7 @@ uint32_t gen4_dec; /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; + bool pcie_port_coalesce; /* Force root port ASPM configuration with port bitmap */ uint8_t pcie_port_force_aspm; diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 29915d6..5997768 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <cpu/intel/haswell/haswell.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> @@ -15,7 +16,7 @@ #include <soc/intel/broadwell/pch/chip.h> #include <southbridge/intel/lynxpoint/iobp.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <delay.h> +#include <types.h> /* Low Power variant has 6 root ports. */ #define MAX_NUM_ROOT_PORTS 6 @@ -31,7 +32,7 @@ u32 b0d28f0_32c; u32 b0d28f4_32c; u32 b0d28f5_32c; - int coalesce; + bool coalesce; int gbe_port; int num_ports; struct device *ports[MAX_NUM_ROOT_PORTS]; @@ -274,7 +275,7 @@ /* If the first root port is disabled the coalesce ports. */ if (!rpc.ports[0]->enabled) - rpc.coalesce = 1; + rpc.coalesce = true; /* Perform clock gating configuration. */ pcie_enable_clock_gating(); diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 797c93f..30c2675 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -4,7 +4,7 @@ #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #include <southbridge/intel/common/spi.h> -#include <stdint.h> +#include <types.h> struct southbridge_intel_bd82x6x_config { /** @@ -58,7 +58,7 @@ uint32_t gen4_dec; /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; + bool pcie_port_coalesce; /* Override PCIe ASPM */ uint8_t pcie_aspm[8]; diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 82b95f6..d24604c 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -319,7 +319,7 @@ * or the other devices will not be enumerated by the OS. */ if (!dev->enabled) - config->pcie_port_coalesce = 1; + config->pcie_port_coalesce = true; if (config->pcie_port_coalesce) printk(BIOS_INFO, diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 303536f..09a7126 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -3,7 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H -#include <stdint.h> +#include <types.h> enum sata_mode { SATA_MODE_AHCI = 0, @@ -61,7 +61,7 @@ uint32_t sata_ports_implemented; /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; + bool pcie_port_coalesce; int c4onc3_enable:1; int docking_supported:1; diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 8650673..b8918e8 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -137,7 +137,7 @@ static void root_port_commit_config(struct device *dev) { int i; - int coalesce = 0; + bool coalesce = false; if (dev->chip_info != NULL) { const struct southbridge_intel_i82801gx_config *config = dev->chip_info; @@ -145,7 +145,7 @@ } if (!rpc.ports[0]->enabled) - coalesce = 1; + coalesce = true; for (i = 0; i < rpc.num_ports; i++) { struct device *pcie_dev; diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 89bbb1c..12bb401 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -65,7 +65,7 @@ uint32_t gen4_dec; /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; + bool pcie_port_coalesce; /* Force root port ASPM configuration with port bitmap */ uint8_t pcie_port_force_aspm; diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 5f21e61..30773e6 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -28,7 +28,7 @@ u32 b0d28f0_32c; u32 b0d28f4_32c; u32 b0d28f5_32c; - int coalesce; + bool coalesce; int gbe_port; int num_ports; struct device *ports[MAX_NUM_ROOT_PORTS]; @@ -304,7 +304,7 @@ /* If the first root port is disabled the coalesce ports. */ if (!is_rp_enabled(1)) - rpc.coalesce = 1; + rpc.coalesce = true; /* Perform clock gating configuration. */ pcie_enable_clock_gating(); -- To view, visit https://review.coreboot.org/c/coreboot/+/60416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Gerrit-Change-Number: 60416 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Simon Yang (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Jamie Chen, Henry Sun, Paul Menzel, Tim Wawrzynczak, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph. Hello build bot (Jenkins), Jamie Chen, Subrata Banik, Henry Sun, Tim Wawrzynczak, Angel Pons, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60009 to look at the new patch set (#26). Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... soc/intel/jasperlake: Add CdClock frequency config Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Also update the comment describing the FSP UPD in the header file FspsUpd.h to match the correct CdClock definition. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 3 files changed, 30 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 26 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Check clkreq overlap
by Subrata Banik (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Kane Chen, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60401 ) Change subject: soc/intel/alderlake: Check clkreq overlap ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/60401/comment/c9fd7f36_fc1b0c78 PS3, Line 63: printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" : , cfg[i].clk_req); > I didn't find any protection actually, so there is a chance 2 root port can use one clkreq. […] On RVP there is a case where its same clksrc getting assign for multiple RPs using external clk buffer circuit. -- To view, visit https://review.coreboot.org/c/coreboot/+/60401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344 Gerrit-Change-Number: 60401 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 28 Dec 2021 11:58:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/quanta/ene_kb3940q: Use Printf() for debug prints
by Angel Pons (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60390 ) Change subject: ec/quanta/ene_kb3940q: Use Printf() for debug prints ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b829a54bbbb8e7442e59feaf2e7dbf8556b590d Gerrit-Change-Number: 60390 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Tue, 28 Dec 2021 11:56:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/purism/librem-ec: Use Printf() for debug prints
by Angel Pons (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60382 ) Change subject: ec/purism/librem-ec: Use Printf() for debug prints ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic26c24d1246f8a40191e02229e66f6a893e488fa Gerrit-Change-Number: 60382 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Tue, 28 Dec 2021 11:56:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/chromeec/ec: Use Printf() for debug prints
by Angel Pons (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60381 ) Change subject: ec/chromeec/ec: Use Printf() for debug prints ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b06f74be155e0c4053a38a1c5fd30ff6715111e Gerrit-Change-Number: 60381 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 28 Dec 2021 11:54:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/starlabs/merlin: Use Printf() for debug prints
by Angel Pons (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer, Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60380 ) Change subject: ec/starlabs/merlin: Use Printf() for debug prints ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59cba7bf553e8323c20fd9aa3474f3ecccf465a Gerrit-Change-Number: 60380 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Tue, 28 Dec 2021 11:52:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/hp/kbc1126: Use Printf() for debug prints
by Angel Pons (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer, Michael Niewöhner, Iru Cai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60383 ) Change subject: ec/hp/kbc1126: Use Printf() for debug prints ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Do you know if this is reproducible? -- To view, visit https://review.coreboot.org/c/coreboot/+/60383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id343bde61706d4d1de2102c3567141e427d8126d Gerrit-Change-Number: 60383 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Dec 2021 11:51:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Check clkreq overlap
by Kane Chen (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Patrick Rudolph. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60401 ) Change subject: soc/intel/alderlake: Check clkreq overlap ...................................................................... Patch Set 4: (3 comments) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/60401/comment/a58826bd_1603847a PS3, Line 51: 32 bit > nit: 32-bit done https://review.coreboot.org/c/coreboot/+/60401/comment/1548c391_e6346a3a PS3, Line 55: u32 > nit: uint32_t […] Done https://review.coreboot.org/c/coreboot/+/60401/comment/ed35126c_0b397d5b PS3, Line 63: printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" : , cfg[i].clk_req); > how are we protecting the overlap now? just serial msg is enough or you would like to skip the overl […] I didn't find any protection actually, so there is a chance 2 root port can use one clkreq. I don't want to skip programming since i'm not pretty sure if there is really a design need this, so printing a warning msg should be good enough. -- To view, visit https://review.coreboot.org/c/coreboot/+/60401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344 Gerrit-Change-Number: 60401 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 28 Dec 2021 11:49:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/auron: Select board-specific options per board
by Angel Pons (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60360 ) Change subject: mb/google/auron: Select board-specific options per board ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c437ee2d62415f9048a24ad4a517fc33eec3cf1 Gerrit-Change-Number: 60360 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Tue, 28 Dec 2021 11:48:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2021