coreboot-gerrit December 2021

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Change in coreboot[master]: ec/chromeec/ec: Use Printf() for debug prints
by Felix Singer (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60381 to look at the new patch set (#2). Change subject: ec/chromeec/ec: Use Printf() for debug prints ...................................................................... ec/chromeec/ec: Use Printf() for debug prints Built with BUILD_TIMELESS=1 and coreboot.rom remains identical. Change-Id: I2b06f74be155e0c4053a38a1c5fd30ff6715111e Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/60381/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b06f74be155e0c4053a38a1c5fd30ff6715111e Gerrit-Change-Number: 60381 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/starlabs/merlin: Use Printf() for debug prints
by Felix Singer (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer, Sean Rhodes. Hello build bot (Jenkins), Sean Rhodes, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60380 to look at the new patch set (#2). Change subject: ec/starlabs/merlin: Use Printf() for debug prints ...................................................................... ec/starlabs/merlin: Use Printf() for debug prints Built with BUILD_TIMELESS=1 and coreboot.rom remains identical. Change-Id: Ib59cba7bf553e8323c20fd9aa3474f3ecccf465a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/starlabs/merlin/acpi/keyboard.asl M src/ec/starlabs/merlin/variants/apl/events.asl M src/ec/starlabs/merlin/variants/cml/events.asl M src/ec/starlabs/merlin/variants/glk/events.asl M src/ec/starlabs/merlin/variants/kbl/events.asl M src/ec/starlabs/merlin/variants/merlin/events.asl M src/ec/starlabs/merlin/variants/tgl/events.asl 7 files changed, 135 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/60380/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59cba7bf553e8323c20fd9aa3474f3ecccf465a Gerrit-Change-Number: 60380 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by Subrata Banik (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/60405/comment/3e54b907_4d21c73c PS6, Line 283: /* : * Ideally, to give coreboot maximum flexibility, sending EOP would be done as : * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must : * be performed before the HECI bus is disabled, so these boards use : * BS_PAYLOAD_LOAD, which happens before the HECI_DISABLE_USING_SMM Kconfig takes : * effect (EOP is sent using the HECI bus). : * Otherwise, EOP can be pushed a little later, and can be performed in : * BS_PAYLOAD_BOOT instead. : */ : #if !CONFIG(HECI_DISABLE_USING_SMM) : BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_cse_end_of_post, NULL); : #else : BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, set_cse_end_of_post, NULL); : #endif > Move these below the function definition? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 28 Dec 2021 13:05:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by Subrata Banik (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer, Subrata Banik, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60405 to look at the new patch set (#7). Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... soc/intel/common/cse: Implement HECI notify This patch implements required heci operation to perform prior to booting to OS after platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. Additionally, creates helper function to set D0I3 for all HECI devices. SoC code to implement the function `soc_heci_set_d0i3` while putting the entire HECI device lists into D0i3. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY: BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 88 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by Arthur Heymans (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer, Subrata Banik, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/60405/comment/8a3ad88e_ea650321 PS6, Line 283: /* : * Ideally, to give coreboot maximum flexibility, sending EOP would be done as : * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must : * be performed before the HECI bus is disabled, so these boards use : * BS_PAYLOAD_LOAD, which happens before the HECI_DISABLE_USING_SMM Kconfig takes : * effect (EOP is sent using the HECI bus). : * Otherwise, EOP can be pushed a little later, and can be performed in : * BS_PAYLOAD_BOOT instead. : */ : #if !CONFIG(HECI_DISABLE_USING_SMM) : BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_cse_end_of_post, NULL); : #else : BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, set_cse_end_of_post, NULL); : #endif Move these below the function definition? -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 28 Dec 2021 12:48:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Reorder selects alphabetically
by Felix Singer (Code Review) 28 Dec '21

28 Dec '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60371 ) Change subject: mb/google/brya: Reorder selects alphabetically ...................................................................... mb/google/brya: Reorder selects alphabetically Change-Id: Ie03f7049b013648372b002ce9b731589b1fffabd Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60371 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name 2 files changed, 19 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 34e005d..13628dd 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -9,14 +9,13 @@ select DRIVERS_I2C_NAU8825 select DRIVERS_I2C_SX9324 select DRIVERS_INTEL_DPTF - select PMC_IPC_ACPI_INTERFACE select DRIVERS_INTEL_DPTF_SUPPORTS_TPCH select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_INTEL_USB4_RETIMER - select DRIVERS_SPI_ACPI select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_MAX98373 + select DRIVERS_SPI_ACPI select DRIVERS_WIFI_GENERIC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP @@ -32,6 +31,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 + select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU @@ -46,12 +46,12 @@ config BOARD_GOOGLE_BASEBOARD_BRASK def_bool n select BOARD_GOOGLE_BRYA_COMMON - select SPD_CACHE_IN_FMAP select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP + select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE - select RT8168_GEN_ACPI_POWER_RESOURCE select SOC_INTEL_ALDERLAKE_PCH_P + select SPD_CACHE_IN_FMAP if BOARD_GOOGLE_BRYA_COMMON diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index bf1f5f9..794bfe7 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -7,8 +7,8 @@ select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_COMMON_BLOCK_IPU - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_CRASHLOG + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_BRYA4ES bool "-> Brya4ES" @@ -17,8 +17,8 @@ select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_COMMON_BLOCK_IPU - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_CRASHLOG + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_BRASK bool "-> Brask" @@ -31,15 +31,15 @@ bool "-> Primus" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9755 - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_PRIMUS4ES bool "-> Primus4ES" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9755 - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_GIMBLE bool "-> Gimble" @@ -62,43 +62,43 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_DSM_CALIB if CHROMEOS select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVERS_GFX_GENERIC select DRIVERS_I2C_MAX98390 select DRIVERS_INTEL_MIPI_CAMERA select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG - select SOC_INTEL_COMMON_BLOCK_IPU - select DRIVERS_GENESYSLOGIC_GL9755 - select DRIVERS_GFX_GENERIC - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_REDRIX4ES bool "-> Redrix4ES" select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_DSM_CALIB if CHROMEOS select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVERS_GFX_GENERIC select DRIVERS_I2C_MAX98390 select DRIVERS_INTEL_MIPI_CAMERA select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG - select SOC_INTEL_COMMON_BLOCK_IPU - select DRIVERS_GENESYSLOGIC_GL9755 - select DRIVERS_GFX_GENERIC - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_KANO bool "-> Kano" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_NAU8825 - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_TAEKO bool "-> Taeko" select BOARD_GOOGLE_BASEBOARD_BRYA - select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENESYSLOGIC_GL9763E config BOARD_GOOGLE_TAEKO4ES bool "-> Taeko4ES" @@ -108,8 +108,8 @@ config BOARD_GOOGLE_FELWINTER bool "-> Felwinter" select BOARD_GOOGLE_BASEBOARD_BRYA - select DRIVERS_GENERIC_GPIO_KEYS select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_GPIO_KEYS config BOARD_GOOGLE_ANAHERA bool "-> Anahera" -- To view, visit https://review.coreboot.org/c/coreboot/+/60371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie03f7049b013648372b002ce9b731589b1fffabd Gerrit-Change-Number: 60371 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel: Use `bool` for PCIe coalescing option
by Felix Singer (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Angel Pons, Arthur Heymans, Michael Niewöhner, Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60416 ) Change subject: sb/intel: Use `bool` for PCIe coalescing option ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: LGTM. Waiting for Jenkins to approve. -- To view, visit https://review.coreboot.org/c/coreboot/+/60416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Gerrit-Change-Number: 60416 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 28 Dec 2021 12:24:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Simon Yang (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Paul Menzel, Tim Wawrzynczak, Ren Kuo, Angel Pons, Kane Chen, Patrick Rudolph. Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... Patch Set 27: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60009/comment/5355b02e_96ae9247 PS17, Line 14: > I don't know what that means exactly and have doubts that I'm authorized […] Hi Nico, I have add more comment in chip.h, do you think is it enough to explain what's the upd CdClock did? File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/60009/comment/fcd2148f_c0590e35 PS21, Line 212: params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff; > Still missing a comment about 0xff here. sorry for missed the comment and thank you for your kindly remind. I added the 0xff to point out the maximum value. -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 27 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 28 Dec 2021 12:24:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Simon Yang <simon1.yang(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Simon Yang (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Jamie Chen, Henry Sun, Paul Menzel, Tim Wawrzynczak, Ren Kuo, Kane Chen, Patrick Rudolph. Hello build bot (Jenkins), Jamie Chen, Subrata Banik, Henry Sun, Tim Wawrzynczak, Angel Pons, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60009 to look at the new patch set (#27). Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... soc/intel/jasperlake: Add CdClock frequency config Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Also update the comment describing the FSP UPD in the header file FspsUpd.h to match the correct CdClock definition. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 3 files changed, 31 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 27 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER
by Casper Chang (Code Review) 28 Dec '21

28 Dec '21

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60417 ) Change subject: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER ...................................................................... mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER Config USE_PM_ACPI_TIMER to y for primus4es only as commit:59790 breaks suspend stress test on ES CPU SKU. BUG=b:211377699 TEST=USE="project_primus emerge-brya coreboot" and verified the suspend stress test works on primus4es. Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/60417/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 34e005d..ee04d36 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -172,6 +172,7 @@ between RST and FCPO). config USE_PM_ACPI_TIMER + default y if BOARD_GOOGLE_PRIMUS4ES default n choice -- To view, visit https://review.coreboot.org/c/coreboot/+/60417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac Gerrit-Change-Number: 60417 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021