coreboot-gerrit December 2021

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Change in coreboot[master]: configs: Add build test configs for CBFS verification
by Julius Werner (Code Review) 29 Dec '21

29 Dec '21

Attention is currently required from: Jakub Czapiga. Hello Jakub Czapiga, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60467 to look at the new patch set (#2). Change subject: configs: Add build test configs for CBFS verification ...................................................................... configs: Add build test configs for CBFS verification Now that CBFS verification is available as an optional feature in menuconfig (CB:59982), we should add build test configs to ensure it doesn't break without notice. One Arm and one x86 board should be good enough for now. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I530dfd37472e63b80a67badd22a13d54d2c4621b --- A configs/config.google_trogdor.build_test M configs/config.google_volteer.build_test_purposes 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/60467/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I530dfd37472e63b80a67badd22a13d54d2c4621b Gerrit-Change-Number: 60467 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake/acpi: Replace LAnd() with ACPI 2.0 syntax
by Felix Singer (Code Review) 29 Dec '21

29 Dec '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60468 ) Change subject: soc/intel/cannonlake/acpi: Replace LAnd() with ACPI 2.0 syntax ...................................................................... soc/intel/cannonlake/acpi: Replace LAnd() with ACPI 2.0 syntax Replace `LAnd (a, b)` with `a && b`. Change-Id: I259bd218ac3f786cef6e05386f6dc55ccaf6b911 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/acpi/pch_hda.asl 3 files changed, 10 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/60468/1 diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 7776acc..6b15f80 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -61,31 +61,31 @@ Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, SPI0_CLK_LOOPBK))) + If (LGreaterEqual (Arg0, GPP_A0) && LLessEqual (Arg0, SPI0_CLK_LOOPBK)) { Store (PID_GPIOCOM0, Local0) Subtract (Arg0, GPP_A0, Local1) } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, vSD3_CD_B))) + If (LGreaterEqual (Arg0, GPP_D0) && LLessEqual (Arg0, vSD3_CD_B)) { Store (PID_GPIOCOM1, Local0) Subtract (Arg0, GPP_D0, Local1) } /* GPIO Community 2 */ - If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, DRAM_RESET_B))) + If (LGreaterEqual (Arg0, GPD0) && LLessEqual (Arg0, DRAM_RESET_B)) { Store (PID_GPIOCOM2, Local0) Subtract (Arg0, GPD0, Local1) } /* GPIO Community 3 */ - If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, TRIGGER_OUT))) + If (LGreaterEqual (Arg0, HDA_BCLK) && LLessEqual (Arg0, TRIGGER_OUT)) { Store (PID_GPIOCOM3, Local0) Subtract (Arg0, HDA_BCLK, Local1) } /* GPIO Community 4*/ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, CL_RST_B))) + If (LGreaterEqual (Arg0, GPP_C0) && LLessEqual (Arg0, CL_RST_B)) { Store (PID_GPIOCOM4, Local0) Subtract (Arg0, GPP_C0, Local1) diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl index 5b3123d..db2b22c 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -67,25 +67,25 @@ Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GSPI1_CLK_LOOPBK))) + If (LGreaterEqual (Arg0, GPP_A0) && LLessEqual (Arg0, GSPI1_CLK_LOOPBK)) { Store (PID_GPIOCOM0, Local0) Subtract (Arg0, GPP_A0, Local1) } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, vSSP2_RXD))) + If (LGreaterEqual (Arg0, GPP_C0) && LLessEqual (Arg0, vSSP2_RXD)) { Store (PID_GPIOCOM1, Local0) Subtract (Arg0, GPP_C0, Local1) } /* GPIO Community 3*/ - If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, SPI0_CLK_LOOPBK))) + If (LGreaterEqual (Arg0, GPP_K0) && LLessEqual (Arg0, SPI0_CLK_LOOPBK)) { Store (PID_GPIOCOM3, Local0) Subtract (Arg0, GPP_K0, Local1) } /* GPIO Community 4*/ - If (LAnd (LGreaterEqual (Arg0, HDACPU_SDI), LLessEqual (Arg0, GPP_J11))) + If (LGreaterEqual (Arg0, HDACPU_SDI) && LLessEqual (Arg0, GPP_J11)) { Store (PID_GPIOCOM4, Local0) Subtract (Arg0, GPP_I0, Local1) diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl index f292901..db2d664 100644 --- a/src/soc/intel/cannonlake/acpi/pch_hda.asl +++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl @@ -36,9 +36,7 @@ * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If (LEqual (Arg1, One) && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) -- To view, visit https://review.coreboot.org/c/coreboot/+/60468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I259bd218ac3f786cef6e05386f6dc55ccaf6b911 Gerrit-Change-Number: 60468 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: configs: Add build test configs for CBFS verification
by Julius Werner (Code Review) 29 Dec '21

29 Dec '21

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60467 ) Change subject: configs: Add build test configs for CBFS verification ...................................................................... configs: Add build test configs for CBFS verification Now that CBFS verification is available as an optional feature in menuconfig (CB:59982), we should add build test configs to ensure it doesn't break without notice. One Arm and one x86 board should be good enough for now. Reshuffle SC7180 memlayout a bit to make things fit (ever since QcLib was switched to LZ4 compression, we haven't needed that much CBFS cache anyway). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I530dfd37472e63b80a67badd22a13d54d2c4621b --- A configs/config.google_trogdor.build_test M configs/config.google_volteer.build_test_purposes M src/soc/qualcomm/sc7180/memlayout.ld 3 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/60467/1 diff --git a/configs/config.google_trogdor.build_test b/configs/config.google_trogdor.build_test new file mode 100644 index 0000000..88c0dd0 --- /dev/null +++ b/configs/config.google_trogdor.build_test @@ -0,0 +1,8 @@ +# Config to build test some optional Kconfigs on an Arm platform +CONFIG_USE_BLOBS=y +CONFIG_USE_QC_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_TROGDOR=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_PAYLOAD_NONE=y diff --git a/configs/config.google_volteer.build_test_purposes b/configs/config.google_volteer.build_test_purposes index 8531b79..6843aeb 100644 --- a/configs/config.google_volteer.build_test_purposes +++ b/configs/config.google_volteer.build_test_purposes @@ -30,3 +30,4 @@ CONFIG_DEBUG_CONSOLE_INIT=y CONFIG_DEBUG_SPI_FLASH=y CONFIG_DEBUG_BOOT_STATE=y +CONFIG_CBFS_VERIFICATION=y diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 1b9044f..2f4b4e1 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -31,8 +31,8 @@ BSRAM_START(0x14800000) REGION(pbl_timestamps, 0x14800000, 83K, 4K) WATCHDOG_TOMBSTONE(0x14814FFC, 4) - BOOTBLOCK(0x14815000, 40K) - PRERAM_CBFS_CACHE(0x1481F000, 70K) + BOOTBLOCK(0x14815000, 48K) + PRERAM_CBFS_CACHE(0x14821000, 62K) PRERAM_CBMEM_CONSOLE(0x14830800, 32K) TIMESTAMP(0x14838800, 1K) TTB(0x14839000, 56K) -- To view, visit https://review.coreboot.org/c/coreboot/+/60467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I530dfd37472e63b80a67badd22a13d54d2c4621b Gerrit-Change-Number: 60467 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add option to make MRC log silent
by Subrata Banik (Code Review) 29 Dec '21

29 Dec '21

Attention is currently required from: Felix Singer, Nico Huber, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Andrey Petrov, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60441 ) Change subject: soc/intel/alderlake: Add option to make MRC log silent ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > > This is what my understanding is: > > > > 1. coreboot and FSP MRC log level are different for example: typical log level for coreboot is 8 where else for MRC the most verbose level is 5. > > > > Hence, the UPD assignment like below will set the wrong value to UPD. Isn't it? > > m_cfg->SerialDebugMrcLevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; > > > > Yes, that's why I said "map". > > > 2. Most of the time, we want to see FSP debug logs but not that verbose MRC debug log which takes several minutes to boot the platform hence, we might still prefer to have different log levels between coreboot and FSP. And for that matter inside FSP even there are 2 different log level (there is one more UPD PcdSerialDebugLevel which controls overall FSP entire debug log level). But the intention is to just make FSP-M silent without additional MRC training prints. > > Why disable error messages then? > > Anyway, for verbose training output there is config > DEBUG_RAM_SETUP. > > > > > > May be we can drop `SOC_INTEL_ALDERLAKE_MRC_DEBUG_CONSENT` config and assign the UPD like this ? > > > > if (CONFIG(SILENT_FSP_M_DEBUG_MESSAGE)) > > m_cfg->SerialDebugMrcLevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0; > > else > > m_cfg->SerialDebugMrcLevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3; > > This would only set it to 1 in odd cases? I don't follow. Did > you mean constant 0 / 3? Also, the console log level is a runtime > setting. It's not easy to query right now, but the API could be > changed. > > Maybe something like this (with to-be-written get_max_console_log_level()): > > int fspm_debug_level; > switch (get_max_console_log_level(CONSOLE_LOG_ALL)) { > case BIOS_EMERG: case BIOS_ALERT: case BIOS_CRIT: case BIOS_ERR: > fspm_debug_level = 1; > break; > case BIOS_WARNING: > fspm_debug_level = 2; > break; > case BIOS_NOTICE: > fspm_debug_level = 3; > break; > case BIOS_INFO: > fspm_debug_level = 4; > break; > case BIOS_DEBUG: case BIOS_SPEW: > fspm_debug_level = 5; > break; > default: > fspm_debug_level = 0; > break; > } > if (!CONFIG(DEBUG_RAM_SETUP)) > fspm_debug_level = MIN(fspm_debug_level, 2); > m_cfg->SerialDebugMrcLevel = fspm_debug_level; This is good idea, let me see if I can come up with this `map` like changes. Thanks for the suggestion. > > > > > in that way, we can reduce to only 1 new Kconfig rather SoC wise Kconfig. WDYT? > > I think this isn't FSP specific. It doesn't matter if one chose > to use a blob instead of writing native code. coreboot already > provides all the needed options. -- To view, visit https://review.coreboot.org/c/coreboot/+/60441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 Gerrit-Change-Number: 60441 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 29 Dec 2021 16:01:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
by Simon Yang (Code Review) 29 Dec '21

29 Dec '21

Attention is currently required from: Nico Huber, Henry Sun, Paul Menzel, Ren Kuo, Angel Pons, Kane Chen, Karthik Ramasubramanian. Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60301 ) Change subject: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60301/comment/01716a66_204af197 PS9, Line 12: per Intel recommendation > > This is a short term WA and will be fixed in newer version of FSP in long term. […] Thank you for your advice and really sorry for waste a lot of time for review. My initial thought just want to provide a easy way to modify it via overridetree.cb. If Ren choice to change it by function mainboard_silicon_init_params() in ramstage.c, maybe I can drop my change first, and once FSP updated, I can go back here to update related header file, what do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/60301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Gerrit-Change-Number: 60301 Gerrit-PatchSet: 9 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 29 Dec 2021 15:14:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Simon Yang <simon1.yang(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec/acpi: Replace LAnd() with ACPI 2.0 syntax
by Felix Singer (Code Review) 29 Dec '21

29 Dec '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60465 to look at the new patch set (#3). Change subject: ec/google/chromeec/acpi: Replace LAnd() with ACPI 2.0 syntax ...................................................................... ec/google/chromeec/acpi: Replace LAnd() with ACPI 2.0 syntax Replace `LAnd (a, b)` with `a && b`. Change-Id: I7d74e6a2ce4ee98c1c0f5b412e20661c5196735e Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/google/chromeec/acpi/battery.asl 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/60465/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d74e6a2ce4ee98c1c0f5b412e20661c5196735e Gerrit-Change-Number: 60465 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/apollolake/acpi: Replace LAnd() with ACPI 2.0 syntax
by Felix Singer (Code Review) 29 Dec '21

29 Dec '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60466 to look at the new patch set (#2). Change subject: soc/intel/apollolake/acpi: Replace LAnd() with ACPI 2.0 syntax ...................................................................... soc/intel/apollolake/acpi: Replace LAnd() with ACPI 2.0 syntax Replace `LAnd (a, b)` with `a && b`. Change-Id: I4bbbc4888fc134b3862bb956b2ee17a72f282584 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/apollolake/acpi/pch_hda.asl M src/soc/intel/apollolake/acpi/pcie_port.asl M src/soc/intel/apollolake/acpi/scs.asl 3 files changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/60466/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bbbc4888fc134b3862bb956b2ee17a72f282584 Gerrit-Change-Number: 60466 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/google/chromeec/acpi: Replace LAnd() with ACPI 2.0 syntax
by Felix Singer (Code Review) 29 Dec '21

29 Dec '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60465 to look at the new patch set (#2). Change subject: ec/google/chromeec/acpi: Replace LAnd() with ACPI 2.0 syntax ...................................................................... ec/google/chromeec/acpi: Replace LAnd() with ACPI 2.0 syntax Replace `LAnd (a, b)` with `a && b`. Change-Id: I7d74e6a2ce4ee98c1c0f5b412e20661c5196735e Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/google/chromeec/acpi/battery.asl 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/60465/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d74e6a2ce4ee98c1c0f5b412e20661c5196735e Gerrit-Change-Number: 60465 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/quanta/it8518/acpi: Replace LAnd() with ACPI 2.0 syntax
by Felix Singer (Code Review) 29 Dec '21

29 Dec '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60464 to look at the new patch set (#2). Change subject: ec/quanta/it8518/acpi: Replace LAnd() with ACPI 2.0 syntax ...................................................................... ec/quanta/it8518/acpi: Replace LAnd() with ACPI 2.0 syntax Replace `LAnd (a, b)` with `a && b`. Change-Id: I72604a0efa2d8fcdf39cf5a8b70082aeb32dddab Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/quanta/it8518/acpi/battery.asl 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/60464/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72604a0efa2d8fcdf39cf5a8b70082aeb32dddab Gerrit-Change-Number: 60464 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/smsc/mec1308/acpi: Replace LAnd() with ACPI 2.0 syntax
by Felix Singer (Code Review) 29 Dec '21

29 Dec '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60463 to look at the new patch set (#2). Change subject: ec/smsc/mec1308/acpi: Replace LAnd() with ACPI 2.0 syntax ...................................................................... ec/smsc/mec1308/acpi: Replace LAnd() with ACPI 2.0 syntax Replace `LAnd (a, b)` with `a && b`. Change-Id: I8c3323e1d367872e9f2a134eaf4ebd9e35f74313 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/smsc/mec1308/acpi/battery.asl 1 file changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/60463/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c3323e1d367872e9f2a134eaf4ebd9e35f74313 Gerrit-Change-Number: 60463 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021