coreboot-gerrit November 2021

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Change in coreboot[master]: configs/config.facebook_fbg1701: Remove CONFIG_ONBOARD_SAMSUNG_MEM
by Frans Hendriks (Code Review) 30 Nov '21

30 Nov '21

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59755 ) Change subject: configs/config.facebook_fbg1701: Remove CONFIG_ONBOARD_SAMSUNG_MEM ...................................................................... configs/config.facebook_fbg1701: Remove CONFIG_ONBOARD_SAMSUNG_MEM CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory. CPLD is used to determine the memory type leaving CONFIG_ONBOARD_SAMSUNG_MEM unused. Remove this config. BUG = N/A TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4 Change-Id: I60626552f2e2338cf5cbaaf4dca1b1eb2756d8df Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M configs/config.facebook_fbg1701.mboot_vboot 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/59755/1 diff --git a/configs/config.facebook_fbg1701.mboot_vboot b/configs/config.facebook_fbg1701.mboot_vboot index 08f0c70..49354a8 100644 --- a/configs/config.facebook_fbg1701.mboot_vboot +++ b/configs/config.facebook_fbg1701.mboot_vboot @@ -1,6 +1,5 @@ CONFIG_VENDOR_FACEBOOK=y CONFIG_BOARD_FACEBOOK_FBG1701=y -CONFIG_ONBOARD_SAMSUNG_MEM=y CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-4c-04" -- To view, visit https://review.coreboot.org/c/coreboot/+/59755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60626552f2e2338cf5cbaaf4dca1b1eb2756d8df Gerrit-Change-Number: 59755 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: complete devapc settings
by Yu-Ping Wu (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59746 ) Change subject: soc/mediatek/mt8195: complete devapc settings ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 10:14:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: complete devapc settings
by Rex-BC Chen (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59746 ) Change subject: soc/mediatek/mt8195: complete devapc settings ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59746/comment/1f5cbf7e_9174beff PS4, Line 7: update > complete Done https://review.coreboot.org/c/coreboot/+/59746/comment/9c359da5_1d53dfd0 PS4, Line 9: patch(chromium:2972318) > patch (CB:56764) Done https://review.coreboot.org/c/coreboot/+/59746/comment/5f54a53b_5b59fd26 PS4, Line 9: we only add basic drivers and : settings, so we add this patch to set devapc final settings on MT8195. > only basic settings were added. Now complete devapc settings on MT8195. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 10:12:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: complete devapc settings
by Rex-BC Chen (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59746 to look at the new patch set (#5). Change subject: soc/mediatek/mt8195: complete devapc settings ...................................................................... soc/mediatek/mt8195: complete devapc settings In previous patch (CB:56764), only basic settings were added. Now complete devapc settings on MT8195. 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=build pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> --- M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/include/soc/devapc.h 3 files changed, 274 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/59746/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM
by Frans Hendriks (Code Review) 30 Nov '21

30 Nov '21

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59754 ) Change subject: mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM ...................................................................... mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory. CPLD returns different values for every board revision. Use this value to determine the memory type. BUG = N/A TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4 Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/facebook/fbg1701/romstage.c 2 files changed, 15 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59754/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index e6e2e47..0efb7e8 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -47,12 +47,6 @@ endif # VBOOT -config ONBOARD_SAMSUNG_MEM - bool "Onboard memory manufacturer Samsung" - default n - help - Samsung K4B8G1646D memory - config MAINBOARD_DIR default "facebook/fbg1701" diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index fd005a6..650d526 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -20,11 +20,21 @@ { u8 spd_index = 0; - if (!CONFIG(ONBOARD_SAMSUNG_MEM)) { - if (cpld_read_pcb_version() <= 7) - spd_index = 1; - else - spd_index = 2; + switch (cpld_read_pcb_version()) { + case 0: /* intentional fallthrough */ + case 1: /* intentional fallthrough */ + case 2: /* intentional fallthrough */ + case 3: /* intentional fallthrough */ + case 4: /* intentional fallthrough */ + case 5: + break; + case 6: /* intentional fallthrough */ + case 7: + spd_index = 1; + break; + default: + spd_index = 2; + break; } memory_params->PcdMemoryTypeEnable = MEM_DDR3; -- To view, visit https://review.coreboot.org/c/coreboot/+/59754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47 Gerrit-Change-Number: 59754 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: update devapc settings
by Yu-Ping Wu (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59746 ) Change subject: soc/mediatek/mt8195: update devapc settings ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59746/comment/089c6749_0afb417b PS4, Line 7: update complete -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 10:05:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: update devapc settings
by Yu-Ping Wu (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59746 ) Change subject: soc/mediatek/mt8195: update devapc settings ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59746/comment/a5b990d1_8cc16032 PS4, Line 9: patch(chromium:2972318) patch (CB:56764) https://review.coreboot.org/c/coreboot/+/59746/comment/e293a3f6_947a717a PS4, Line 9: we only add basic drivers and : settings, so we add this patch to set devapc final settings on MT8195. only basic settings were added. Now complete devapc settings on MT8195. -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 10:04:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/*/Kconfig: Enable x86_64 Kconfig option
by Patrick Rudolph (Code Review) 30 Nov '21

30 Nov '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48244 ) Change subject: soc/intel/*/Kconfig: Enable x86_64 Kconfig option ...................................................................... soc/intel/*/Kconfig: Enable x86_64 Kconfig option Tested on Intel Skylake. Compiles and boots without issues. Used tianocore as payload and could boot into Ubuntu 20. Other platforms might not compile due to drivers not being ported to x86_64 or might not boot due to a yet unsupported boot flow. Untested: * FSP MPinit * FSP-T * SMM loader v2 * libgfxinit * FSP graphics init Change-Id: Id2919766acc2e11d81c279c23380a9e6fd50f0bb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 10 files changed, 24 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48244/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index d6db6a0..61d8ee4 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 29e133c..0df396d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -22,7 +22,8 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NO_PCAT_8259 - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options select CPU_INTEL_COMMON diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f256405..07cdeb5 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -74,7 +74,8 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9023b58..6a95b4d 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -1,3 +1,9 @@ +config EXP_ARCH_X86_64 + bool "Experimental x86_64 support" + default n + help + This option will compile and run coreboot in x86_64 long mode. + config SOC_INTEL_COMMON_BLOCK_CPU bool default n diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 98c61ce..9ad2a70 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -13,7 +13,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO select SOC_INTEL_COMMON diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 64680e8..4cfee7e 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 5fdfa2f..4dedbe7 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index c23e3ce..683865a 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index c61304b..bb39571 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -19,7 +19,8 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index b95b2f0..e4cd466 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/48244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2919766acc2e11d81c279c23380a9e6fd50f0bb Gerrit-Change-Number: 48244 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/cpu/x86/mp.h: Remove indirect include
by Angel Pons (Code Review) 30 Nov '21

30 Nov '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59691 ) Change subject: include/cpu/x86/mp.h: Remove indirect include ...................................................................... include/cpu/x86/mp.h: Remove indirect include This one might conflict with '#include <smp/atomic.h>'. Change-Id: I7413406ca69e78e5a6e539a01e05033243107272 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59691 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/cpu/x86/mp.h 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 7ed82dd..934d217 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -3,7 +3,6 @@ #ifndef _X86_MP_H_ #define _X86_MP_H_ -#include <arch/smp/atomic.h> #include <cpu/x86/smm.h> #include <types.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/59691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7413406ca69e78e5a6e539a01e05033243107272 Gerrit-Change-Number: 59691 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/i440bx: Use PARALLEL_MP
by Angel Pons (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Keith Hui, Branden Waldner, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59693 ) Change subject: nb/intel/i440bx: Use PARALLEL_MP ...................................................................... Patch Set 4: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59693/comment/602de902_beaf0b79 PS4, Line 10: always This is not true, see `src/mainboard/asus/p2b/Kconfig`. Although the CPUs only have one core, there are mainboards with two CPU sockets. https://review.coreboot.org/c/coreboot/+/59693/comment/50f8c7ed_53351fa3 PS4, Line 13: increase is increased File src/northbridge/intel/i440bx/northbridge.c: https://review.coreboot.org/c/coreboot/+/59693/comment/8f56c3f2_cc9baaf8 PS4, Line 6: #include <device/device.h> I wouldn't remove this, `struct device` is used https://review.coreboot.org/c/coreboot/+/59693/comment/1cfb49f9_4b469fb6 PS4, Line 76: 1 Not true for mainboards with two CPU sockets, see comment in commit message. I'm not sure if there's a generic procedure to detect which CPU sockets are populated. In any case, returning `CONFIG_MAX_CPUS` would at least be slightly more correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/59693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b Gerrit-Change-Number: 59693 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 10:01:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021