coreboot-gerrit November 2021

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59086 ) Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... Patch Set 14: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59086/comment/2e1a8fde_64d07c75 PS13, Line 13: TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC is : RT8125. Check if the default MAC is written into the NIC. > 72 characters wide please Done Patchset: PS5: > Yes. We are now working on LED part in commit https://review.coreboot.org/c/coreboot/+/59531. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 14 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 11:15:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02
by Ronak Kanabar (Code Review) 30 Nov '21

30 Nov '21

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59757 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02 ...................................................................... vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02 The headers added are generated as per FSP v2471_02. Previous FSP version was v2422_01. Changes Include: - UPDs description update in FspsUpd.h - Adjust UPD Offset in FspmUpd.h and FspsUpd.h BUG=b:208336249 BRANCH=None TEST=Build and boot brya Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/59757/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 271e01c..191ef27 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -3164,7 +3164,7 @@ /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved45[104]; + UINT8 Reserved45[136]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3183,11 +3183,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0B10 +/** Offset 0x0B30 **/ - UINT8 UnusedUpdSpace31[6]; + UINT8 UnusedUpdSpace34[6]; -/** Offset 0x0B16 +/** Offset 0x0B36 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index ddf6ca8..a73fe59 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -3380,8 +3380,7 @@ UINT8 ProcHotLock; /** Offset 0x0CF3 - Configuration for boot TDP selection - Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate + Deprecated. Move to premem. **/ UINT8 ConfigTdpLevel; @@ -3869,7 +3868,7 @@ /** Offset 0x0FD5 - Reserved **/ - UINT8 Reserved56[19]; + UINT8 Reserved56[123]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3888,11 +3887,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0FE8 +/** Offset 0x1050 **/ UINT8 UnusedUpdSpace42[6]; -/** Offset 0x0FEE +/** Offset 0x1056 **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/59757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c Gerrit-Change-Number: 59757 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: David Wu, Paul Menzel, Zhuohao Lee, Alan Huang. Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59086 to look at the new patch set (#14). Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... drivers/net/r8168: Add support for Realtek RT8125 The Realtek RT8168 and RT8125 have a similar programming interface, therefore add the PCI device ID for the RT8125 into driver for support. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC is RT8125. Check if the default MAC is written into the NIC. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 --- M src/drivers/net/r8168.c M src/include/device/pci_ids.h 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 14 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/brask: Set PL and PsysPL
by Alan Huang (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: David Wu, Hou-hsun Lee, Paul Menzel. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59576 ) Change subject: mb/google/brya/var/brask: Set PL and PsysPL ...................................................................... Patch Set 4: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59576/comment/6b611a5b_fc3c420c PS3, Line 9: defalut > default Done https://review.coreboot.org/c/coreboot/+/59576/comment/adc3770d_c5043fdb PS3, Line 9: Intel's spec > Please mention the document name and revision, and even document the values in the commit message so […] Done https://review.coreboot.org/c/coreboot/+/59576/comment/23b41abb_fa9f890f PS3, Line 9: Set the defalut PL1, PL2 and PL4 according to Intel's spec. : Set PsysPL2 and PsysPmax according to Brask's spec. > Please mark it up as a list, or reflow it for 75 characters per line. Done https://review.coreboot.org/c/coreboot/+/59576/comment/ef8d9e17_5fe22758 PS3, Line 10: Brask's spec > Ditto. Done File src/mainboard/google/brya/variants/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/59576/comment/6e4d0b4d_57d2a2d4 PS3, Line 13: { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, > Sort it the other way around? It's better to sort it in the same way with code here https://review.coreboot.org/c/coreboot/+/59483/6/src/soc/intel/alderlake/ch… https://review.coreboot.org/c/coreboot/+/59576/comment/d60d35bd_8f11bd5a PS3, Line 23: { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230 }, > Ditto. It's better to sort it in the same way with code here https://review.coreboot.org/c/coreboot/+/59483/6/src/soc/intel/alderlake/ch… -- To view, visit https://review.coreboot.org/c/coreboot/+/59576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Gerrit-Change-Number: 59576 Gerrit-PatchSet: 4 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 11:12:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/baseboard/brask: Add power limits functions
by Alan Huang (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Paul Menzel, Nick Vaccaro, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58241 ) Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions ...................................................................... Patch Set 16: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58241/comment/2db338f9_16de6dc3 PS15, Line 13: config > configure Done https://review.coreboot.org/c/coreboot/+/58241/comment/d812e652_e23df8d0 PS15, Line 17: Pass > pass Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 16 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 10:55:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: Set PL and PsysPL
by Alan Huang (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: David Wu, Hou-hsun Lee. Hello build bot (Jenkins), David Wu, Hou-hsun Lee, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59576 to look at the new patch set (#4). Change subject: mb/google/brya/var/brask: Set PL and PsysPL ...................................................................... mb/google/brya/var/brask: Set PL and PsysPL 1. Set the PL1, PL2 and PL4 according to issue b:193864533 comment#55 and Intel's doc #626774. 2. Set PsysPL2 and PsysPmax according to the conclusion in issue b:193864533 comment#23 and comment#29. BUG=b:193864533 BRANCH=none TEST=Compare the measured power from adapter with the value of 'psys' from the command 'dump_intel_rapl_consumption'. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 --- M src/mainboard/google/brya/variants/brask/Makefile.inc A src/mainboard/google/brya/variants/brask/ramstage.c 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59576/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Gerrit-Change-Number: 59576 Gerrit-PatchSet: 4 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/baseboard/brask: Add power limits functions
by Alan Huang (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee, Alan Huang. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58241 to look at the new patch set (#16). Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions ...................................................................... mb/google/brya/var/baseboard/brask: Add power limits functions Copy function variant_update_power_limits from brya to set power limits. Add function variant_update_psys_power_limits and copy the algorithm from puff. Add structure system_power_limits and psys_config to define and configure the psys power limits. BUG=b:193864533 BRANCH=none TEST=Build pass Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 --- M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc A src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h 3 files changed, 175 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/58241/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 16 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: complete devapc settings
by Rex-BC Chen (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59746 ) Change subject: soc/mediatek/mt8195: complete devapc settings ...................................................................... Patch Set 5: Code-Review-1 (1 comment) Patchset: PS5: wait QA fully test -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 10:41:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentatiion/mb/facebook/fbg1701.md: Update memory information
by Frans Hendriks (Code Review) 30 Nov '21

30 Nov '21

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59756 ) Change subject: Documentatiion/mb/facebook/fbg1701.md: Update memory information ...................................................................... Documentatiion/mb/facebook/fbg1701.md: Update memory information CPLD can be used for board revision determinition. Remove info about selecting memory type and add Rev 1.4 info BUG = N/A TEST = NA Change-Id: I4bc851f72ae03e98ab1b2e0e04b07ccf6135ebeb Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M Documentation/mainboard/facebook/fbg1701.md 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/59756/1 diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md index e711ef3..1c72d6c 100644 --- a/Documentation/mainboard/facebook/fbg1701.md +++ b/Documentation/mainboard/facebook/fbg1701.md @@ -5,10 +5,7 @@ FBG1701 are assembled with different onboard memory modules: Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory - Rev 1.3 Onboard Kingston B5116ECMDXGGB memory - -Use make menuconfig to configure `onboard memory manufacturer Samsung` in -Mainboard menu. + Rev 1.3 and 1.4 Onboard Kingston B5116ECMDXGGB memory ## Required blobs -- To view, visit https://review.coreboot.org/c/coreboot/+/59756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc851f72ae03e98ab1b2e0e04b07ccf6135ebeb Gerrit-Change-Number: 59756 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM
by Frans Hendriks (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Michał Żygowski, Angel Pons, Arthur Heymans, Wim Vervoorn. Hello build bot (Jenkins), Michał Żygowski, Angel Pons, Arthur Heymans, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59754 to look at the new patch set (#2). Change subject: mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM ...................................................................... mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory. CPLD returns different values for every board revision. Use this value to determine the memory type. BUG = N/A TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4 Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/facebook/fbg1701/romstage.c 2 files changed, 15 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59754/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47 Gerrit-Change-Number: 59754 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021