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Change subject: src/soc/intel/skylake/Kconfig: Enable x86_64 support
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Patch Set 2: Code-Review+2
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Change subject: src/soc/intel/skylake/Kconfig: Enable x86_64 support
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Patch Set 2: Code-Review+1
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Change subject: src/security/intel: Use defines for segment registers
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Patch Set 1: Code-Review+2
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Change subject: oprom/realmode/x86.c: Fix building for ENV_X86_64
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Patch Set 3: Verified+1
(2 comments)
File src/device/oprom/realmode/x86.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134674):
https://review.coreboot.org/c/coreboot/+/59660/comment/7238f025_e7fce986
PS3, Line 94: .rip=X86_EIP,
spaces required around that '=' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134674):
https://review.coreboot.org/c/coreboot/+/59660/comment/e32904ea_3bfa8095
PS3, Line 100: .rflags=X86_EFLAGS
spaces required around that '=' (ctx:VxV)
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Change subject: oprom/realmode/x86.c: Fix building for ENV_X86_64
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Patch Set 2:
(1 comment)
File src/device/oprom/realmode/x86.c:
https://review.coreboot.org/c/coreboot/+/59660/comment/1aa6ff44_6b39fa54
PS2, Line 100: X86_EFLAGS
I have posted a note for discussion
https://review.coreboot.org/c/coreboot/+/59753/comment/1c83789d_6d2801da/
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Change subject: soc/intel/alderlake: Based on power map data to add ADL-P 682(28W) VR config
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Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59736/comment/53c6206f_a3abc6ea
PS1, Line 7: soc/intel/alderlake: Based on power map data to add ADL-P 682(28W) VR config
Please make it a statement with a verb (in imperative mood) [1].
[1]: https://chris.beams.io/posts/git-commit/https://review.coreboot.org/c/coreboot/+/59736/comment/09fe8d64_a307d30f
PS1, Line 9: ADL-P 682(28W)
Please add a space before the (.
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Change subject: soc/intel/alderlake: Adding Kconfig for ADL_N PCH
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Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59751/comment/c0790e60_f3ff3d95
PS1, Line 7: Adding
Add
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/59751/comment/d665f1ca_25664ab9
PS1, Line 14: Choose this option if you have PCH-N chipset.
Can’t this be auto-detected at runtime?
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Change subject: soc/intel/alderlake: Select number of I/O for ADL-N
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59752/comment/4629b7c7_68fb0bf8
PS1, Line 7: soc/intel/alderlake: Select number of I/O for ADL-N
Please be specific and include the number:
> Configure 9 I/O for ADL-N
https://review.coreboot.org/c/coreboot/+/59752/comment/7743ade4_40fd04ca
PS1, Line 9: Select number of I/O based on PCH for Alder Lake-N
Where is the number 9 documented in?
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