coreboot-gerrit November 2021

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Change in coreboot[master]: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STOR...
by Anil Kumar K (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Anil Kumar K, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59638 to look at the new patch set (#5). Change subject: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STORAGE_HOB2 HOB introduced in FSP 2.3 ...................................................................... [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STORAGE_HOB2 HOB introduced in FSP 2.3 Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e --- M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/include/fsp/util.h 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59638/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 5 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [RFC]cpu/x86/mp.h: Guard mfence on pre SSE2 platforms
by build bot (Jenkins) (Code Review) 30 Nov '21

30 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59766 ) Change subject: [RFC]cpu/x86/mp.h: Guard mfence on pre SSE2 platforms ...................................................................... Patch Set 1: (2 comments) File src/include/cpu/x86/mp.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134682): https://review.coreboot.org/c/coreboot/+/59766/comment/5fdb0b9a_543e6ce0 PS1, Line 18: __asm__ __volatile__("mfence\t\n": : :"memory"); spaces required around that ':' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134682): https://review.coreboot.org/c/coreboot/+/59766/comment/b42e2136_1aac2a4e PS1, Line 18: __asm__ __volatile__("mfence\t\n": : :"memory"); spaces required around that ':' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/59766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I376f86f4d7992344dd68374ba67ad3580070f4d8 Gerrit-Change-Number: 59766 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 20:14:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]cpu/x86/mp.h: Guard mfence on pre SSE2 platforms
by Arthur Heymans (Code Review) 30 Nov '21

30 Nov '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59766 ) Change subject: [RFC]cpu/x86/mp.h: Guard mfence on pre SSE2 platforms ...................................................................... [RFC]cpu/x86/mp.h: Guard mfence on pre SSE2 platforms Is this a good idea?? Change-Id: I376f86f4d7992344dd68374ba67ad3580070f4d8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cpu/x86/mp.h 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59766/1 diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 934d217..f318277 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -13,7 +13,9 @@ static inline void mfence(void) { - __asm__ __volatile__("mfence\t\n": : :"memory"); + /* mfence came with the introduction of SSE2. */ + if (CONFIG(SSE2)) + __asm__ __volatile__("mfence\t\n": : :"memory"); } /* The sequence of the callbacks are in calling order. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I376f86f4d7992344dd68374ba67ad3580070f4d8 Gerrit-Change-Number: 59766 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: configs/i440fx: Buildtest PARALLEL_MP
by Arthur Heymans (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59695 to look at the new patch set (#2). Change subject: configs/i440fx: Buildtest PARALLEL_MP ...................................................................... configs/i440fx: Buildtest PARALLEL_MP Change-Id: If30d715c5a3b44be2832c96316003dc9d139b53f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M configs/config.emulation_qemu_x86_i440fx_debug 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59695/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If30d715c5a3b44be2832c96316003dc9d139b53f Gerrit-Change-Number: 59695 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs i...
by Michał Żygowski (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Michał Żygowski, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59519 to look at the new patch set (#14). Change subject: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs in CBFS ...................................................................... security/intel/txt: Fix HEAP_ACM format depending on number of ACMs in CBFS Since we may have either BIOS ACM or both BIOS and SINIT ACMs in CBFS, the size of txt_heap_acm_element will be different. We cannot always hardcode the size of ACM addresses array for two ACMs. If only the BIOS ACM was included, the BDR parsing failed in TBoot due to invalid size of HEAP_ACM element. Check if SINIT ACM is present in CBFS and push properly formatted BDR region onto the TXT heap. Use two separate txt_heap_acm_element structures with different lengths. TEST=Boot QubesOS 4.0 with TBoot 1.8.2 on Dell OptiPlex 9010 with and without SINIT ACM in CBFS and see that TBoot no longer complains on the wrong size of HEAP_ACM element Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e --- M src/security/intel/txt/ramstage.c M src/security/intel/txt/txt_register.h 2 files changed, 114 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59519/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/59519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e Gerrit-Change-Number: 59519 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth
by Tim Wawrzynczak (Code Review) 30 Nov '21

30 Nov '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59658 ) Change subject: mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth ...................................................................... mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth BlueTooth disappeared after disabled USB2 port 9, so we need to re-enable it. BUG=none TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I7971509d7428562c80e781339ead059a189cea13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59658 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index e0ac351..a908a7b 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -20,7 +20,6 @@ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable M.2 Bluetooth register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN -- To view, visit https://review.coreboot.org/c/coreboot/+/59658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7971509d7428562c80e781339ead059a189cea13 Gerrit-Change-Number: 59658 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brask: Set PL and PsysPL
by Tim Wawrzynczak (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: David Wu, Hou-hsun Lee, Paul Menzel, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59576 ) Change subject: mb/google/brya/var/brask: Set PL and PsysPL ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/mainboard/google/brya/variants/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/59576/comment/e5526dd7_c750dc0c PS3, Line 13: { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, > It's better to sort it in the same way with code here https://review.coreboot. […] this matches others already in the tree too, see https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… -- To view, visit https://review.coreboot.org/c/coreboot/+/59576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Gerrit-Change-Number: 59576 Gerrit-PatchSet: 4 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 19:43:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/baseboard/brask: Add power limits functions
by Tim Wawrzynczak (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Paul Menzel, Nick Vaccaro, Zhuohao Lee, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58241 ) Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions ...................................................................... Patch Set 16: (2 comments) File src/mainboard/google/brya/variants/baseboard/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/58241/comment/b0abe7ae_91ee7c3b PS16, Line 92: if (!num_entries) : return; : : const struct device *policy_dev = DEV_PTR(dptf_policy); : if (!policy_dev) : return; : : size_t intel_idx, brask_idx; : if (!get_sku_index(limits, num_entries, &intel_idx, &brask_idx)) : return; : : config_t *conf = config_of_soc(); : struct soc_power_limits_config *soc_config = &conf->power_limits_config[intel_idx]; : : enum usb_chg_type type; : u32 watts; : u16 volts_mv, current_ma; : u32 psyspl2, pl2; : soc_config->tdp_pl4 = 0; : u32 pl2_default = DIV_ROUND_UP(limits[brask_idx].pl2_max_power, MILLIWATTS_TO_WATTS); : int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); suggestion, slighly reorganize this for readability: ``` struct soc_power_limits_config *soc_config; const struct device *policy_dev; size_t intel_idx, brask_idx; u16 volts_mv, current_ma; enum usb_chg_type type; u32 psyspl2, pl2; u32 pl2_default; config_t *conf; u32 watts; int rv; if (!num_entries) return; policy_dev = DEV_PTR(dptf_policy); if (!policy_dev) return; if (!get_sku_index(limits, num_entries, &intel_idx, &brask_idx)) return; conf = config_of_soc(); soc_config = &conf->power_limits_config[intel_idx]; soc_config->tdp_pl4 = 0; pl2_default = DIV_ROUND_UP(limits[brask_idx].pl2_max_power, MILLIWATTS_TO_WATTS); rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); ``` https://review.coreboot.org/c/coreboot/+/58241/comment/e114f623_64704475 PS16, Line 131: /* voltage unit is milliVolts and current is in milliAmps */ nit: blank line after `}` -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 16 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 19:41:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add the CnviDdrRfim configuration
by Tim Wawrzynczak (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58132 ) Change subject: soc/intel/alderlake: Add the CnviDdrRfim configuration ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Gerrit-Change-Number: 58132 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 19:35:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Based on power map data to add ADL-P 682(28W) VR...
by Tim Wawrzynczak (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Curtis Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59736 ) Change subject: soc/intel/alderlake: Based on power map data to add ADL-P 682(28W) VR config ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Gerrit-Change-Number: 59736 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 19:35:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021