coreboot-gerrit November 2021

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Change in coreboot[master]: drivers/gfx/generic: Add optional _HID for gfx devices
by Tim Wawrzynczak (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Felix Held, Rajat Jain. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59730 ) Change subject: drivers/gfx/generic: Add optional _HID for gfx devices ...................................................................... Patch Set 1: (1 comment) File src/drivers/gfx/generic/generic.c: https://review.coreboot.org/c/coreboot/+/59730/comment/f18bb37e_386c2266 PS1, Line 125: acpigen_write_name_integer("_STA", 0xF); > is it intended that the device status information gets removed? Nope, that was a mistake, good eye Felix! -- To view, visit https://review.coreboot.org/c/coreboot/+/59730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32be4abf5c60be1f94aabaa2e9c734215c4e291e Gerrit-Change-Number: 59730 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Rajat Jain <rajatja(a)google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 22:40:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/gfx/generic: Add optional _HID for gfx devices
by Tim Wawrzynczak (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Tim Wawrzynczak, Rajat Jain. Hello build bot (Jenkins), Nick Vaccaro, Rajat Jain, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59730 to look at the new patch set (#2). Change subject: drivers/gfx/generic: Add optional _HID for gfx devices ...................................................................... drivers/gfx/generic: Add optional _HID for gfx devices Some boards may want to use a _HID instead of an _ADR to locate a graphics device. This patch provides that option in the devicetree. BUG=b:206850071 TEST=Add `hid` entry in devicetree, dump SSDT and see _HID instead of _ADR Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I32be4abf5c60be1f94aabaa2e9c734215c4e291e --- M src/drivers/gfx/generic/chip.h M src/drivers/gfx/generic/generic.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/59730/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32be4abf5c60be1f94aabaa2e9c734215c4e291e Gerrit-Change-Number: 59730 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi: Convert ACPI_DEVICE_SLEEP_* values to an enum
by Felix Held (Code Review) 30 Nov '21

30 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59634 ) Change subject: acpi: Convert ACPI_DEVICE_SLEEP_* values to an enum ...................................................................... acpi: Convert ACPI_DEVICE_SLEEP_* values to an enum These values make more sense as an enum, and are currently unused in ASL files, therefore they can be moved to the appropriate part of the header file and converted there. Change-Id: I8b8586b46823b5da3614a0b2a2f2f16802e96962 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59634 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/acpi/acpi.h 1 file changed, 9 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 4a95855..dade92d 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -31,14 +31,6 @@ #define SLP_TYP_S5 5 #endif -/* ACPI Device Sleep States */ -#define ACPI_DEVICE_SLEEP_D0 0 -#define ACPI_DEVICE_SLEEP_D1 1 -#define ACPI_DEVICE_SLEEP_D2 2 -#define ACPI_DEVICE_SLEEP_D3 3 -#define ACPI_DEVICE_SLEEP_D3_HOT ACPI_DEVICE_SLEEP_D3 -#define ACPI_DEVICE_SLEEP_D3_COLD 4 - #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ #define ACPI_DSDT_REV_1 0x01 /* DSDT revision: ACPI v1 */ @@ -52,6 +44,15 @@ #include <romstage_handoff.h> #include <types.h> +enum acpi_device_sleep_states { + ACPI_DEVICE_SLEEP_D0 = 0, + ACPI_DEVICE_SLEEP_D1 = 1, + ACPI_DEVICE_SLEEP_D2 = 2, + ACPI_DEVICE_SLEEP_D3 = 3, + ACPI_DEVICE_SLEEP_D3_HOT = ACPI_DEVICE_SLEEP_D3, + ACPI_DEVICE_SLEEP_D3_COLD = 4, +}; + #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ASLC "CORE" /* Must be exactly 4 bytes long! */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b8586b46823b5da3614a0b2a2f2f16802e96962 Gerrit-Change-Number: 59634 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/gfx/generic: Add optional _HID for gfx devices
by Felix Held (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Tim Wawrzynczak, Rajat Jain. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59730 ) Change subject: drivers/gfx/generic: Add optional _HID for gfx devices ...................................................................... Patch Set 1: (1 comment) File src/drivers/gfx/generic/generic.c: https://review.coreboot.org/c/coreboot/+/59730/comment/389502d5_e10e5550 PS1, Line 125: acpigen_write_name_integer("_STA", 0xF); is it intended that the device status information gets removed? -- To view, visit https://review.coreboot.org/c/coreboot/+/59730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32be4abf5c60be1f94aabaa2e9c734215c4e291e Gerrit-Change-Number: 59730 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rajat Jain <rajatja(a)google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 22:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/drivers/intel/fsp2_0: Add FSP 2.3 support
by Anil Kumar K (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Paul Menzel, Subrata Banik, Andrey Petrov, Patrick Rudolph. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59324 ) Change subject: [WIP] src/drivers/intel/fsp2_0: Add FSP 2.3 support ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: > A message to the mailing list would be great, what changed between FSP 2.2 and 2.3. Sure. here are the details. I have added these in Kconfig as well Features added into FSP 2.3 specification that impact coreboot are: 1. FSP_INFO_HEADER changes Updated SpecVersion from 0x22 to 0x23 Updated HeaderRevision from 5 to 6 Added ExtendedImageRevision FSP_INFO_HEADER length changed to 0x50 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 New HOB introduced to take care of data size limitation in previous HOB -- To view, visit https://review.coreboot.org/c/coreboot/+/59324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1 Gerrit-Change-Number: 59324 Gerrit-PatchSet: 11 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 22:06:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
by Felix Held (Code Review) 30 Nov '21

30 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59701 ) Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ...................................................................... soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 Despite Stoneyridge being one only SoC in soc/amd that uses the first generation of the PSP mailblox interface, this code is common for all SoCs that use the first PSP mailbox interface generation, so move it to the common PSP generation 1 code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/psp.c 5 files changed, 36 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 2aa000e..e749d75 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -5,9 +5,6 @@ #include <stdint.h> -/* Get the mailbox base address - specific to family of device. */ -void *soc_get_mbox_address(void); - #define SMM_TRIGGER_IO 0 #define SMM_TRIGGER_MEM 1 diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 076d354..55070f2 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/amd/msr.h> +#include <cpu/x86/msr.h> #include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> #include <cbfs.h> #include <region_file.h> #include <timer.h> @@ -8,8 +12,39 @@ #include <amdblocks/psp.h> #include <soc/iomap.h> #include <soc/northbridge.h> +#include <soc/pci_devs.h> +#include <soc/southbridge.h> #include "psp_def.h" +#define PSP_MAILBOX_OFFSET 0x70 + +static void *soc_get_mbox_address(void) +{ + uintptr_t psp_mmio; + + /* Check for presence of the PSP */ + if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { + printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", + PSP_DEV, PSP_FUNC); + return 0; + } + + /* Determine if Bar3Hide has been set, and if hidden get the base from + * the MSR instead. */ + if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { + psp_mmio = rdmsr(PSP_ADDR_MSR).lo; + if (!psp_mmio) { + printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); + return 0; + } + } else { + psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } + + return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); +} + static u32 rd_mbox_sts(struct pspv1_mbox *mbox) { return read32(&mbox->mbox_status); diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index e2f51d8..aef7dad 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -19,7 +19,7 @@ return psp_mmio; } -void *soc_get_mbox_address(void) +static void *soc_get_mbox_address(void) { uintptr_t psp_mmio = soc_get_psp_base_address(); if (!psp_mmio) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 97eb806..74e9498 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -181,7 +181,6 @@ void soc_enable_psp_early(void); #define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ -#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */ #define PSP_BAR_ENABLES 0x48 #define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index b001d5f..e2a74bd 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -3,8 +3,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/msr.h> #include <soc/pci_devs.h> #include <soc/northbridge.h> #include <soc/southbridge.h> @@ -30,30 +28,3 @@ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); }; - -void *soc_get_mbox_address(void) -{ - uintptr_t psp_mmio; - - /* Check for presence of the PSP */ - if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { - printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", - PSP_DEV, PSP_FUNC); - return 0; - } - - /* Determine if Bar3Hide has been set, and if hidden get the base from - * the MSR instead. */ - if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { - psp_mmio = rdmsr(PSP_ADDR_MSR).lo; - if (!psp_mmio) { - printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); - return 0; - } - } else { - psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) & - ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - } - - return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/59701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Gerrit-Change-Number: 59701 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
by Reka Norman (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Kangheui Won, Isaac Lee, Kane Chen, chris wang, Felix Held. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59558 ) Change subject: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/zork/variants/shuboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59558/comment/3d233d6f_66cd5455 PS5, Line 2: fw_config > Hi Kangheui, […] Hi Kane, I will look into why using probe doesn't work. Could you please share the original version of your change which gave the results in http://b/198689479#comment17. -- To view, visit https://review.coreboot.org/c/coreboot/+/59558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749 Gerrit-Change-Number: 59558 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Randy Wang <ifanw(a)google.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Nov 2021 21:50:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [Untested]cpu/x86/mp.h: Implement a pre-SSE2 mfence
by build bot (Jenkins) (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Keith Hui, Branden Waldner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59766 ) Change subject: [Untested]cpu/x86/mp.h: Implement a pre-SSE2 mfence ...................................................................... Patch Set 2: (3 comments) File src/include/cpu/x86/mp.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134688): https://review.coreboot.org/c/coreboot/+/59766/comment/b450ede3_e7660063 PS2, Line 18: __asm__ __volatile__("mfence\t\n": : :"memory"); spaces required around that ':' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134688): https://review.coreboot.org/c/coreboot/+/59766/comment/ea263b2d_2b11590e PS2, Line 18: __asm__ __volatile__("mfence\t\n": : :"memory"); spaces required around that ':' (ctx:WxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134688): https://review.coreboot.org/c/coreboot/+/59766/comment/eecb7d07_1540b319 PS2, Line 20: __asm__ __volatile__("lock; addl $0,0(%%esp)": : : "memory"); spaces required around that ':' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/59766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I376f86f4d7992344dd68374ba67ad3580070f4d8 Gerrit-Change-Number: 59766 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 21:11:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [Untested]cpu/x86/mp.h: Implement a pre-SSE2 mfence
by Arthur Heymans (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Keith Hui, Branden Waldner. Hello Keith Hui, build bot (Jenkins), Branden Waldner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59766 to look at the new patch set (#2). Change subject: [Untested]cpu/x86/mp.h: Implement a pre-SSE2 mfence ...................................................................... [Untested]cpu/x86/mp.h: Implement a pre-SSE2 mfence Taken from the Linux Kernel. Untested Change-Id: I376f86f4d7992344dd68374ba67ad3580070f4d8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cpu/x86/mp.h 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59766/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I376f86f4d7992344dd68374ba67ad3580070f4d8 Gerrit-Change-Number: 59766 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Tim Wawrzynczak (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: David Wu, Paul Menzel, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59086 ) Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 14 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 21:05:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021