coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STOR...
by Anil Kumar K (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Patrick Rudolph. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STORAGE_HOB2 HOB introduced in FSP 2.3 ...................................................................... Patch Set 9: (3 comments) File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/59638/comment/0a825b71_05055b99 PS8, Line 25: #if CONFIG(PLATFORM_USES_FSP2_3) > suggestion: don't guard the definition of this, I will explain more below Done https://review.coreboot.org/c/coreboot/+/59638/comment/1765f593_53b88ac0 PS8, Line 318: #if CONFIG(PLATFORM_USES_FSP2_3) : : void *hob_ptr = NULL; : hob_ptr = fsp_find_extension_hob_by_guid(fsp_nv_storage_guid_2, size); : if (hob_ptr != NULL) { : size = (fsp_nvs_hob2_data_region_header *) hob_ptr->nvs_data_length; : return (fsp_nvs_hob2_data_region_header *) hob_ptr->nvs_data_ptr; : } : #endif : return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size); > suggestion: we don't need the preprocessor, we can just do something like […] Done File src/drivers/intel/fsp2_0/include/fsp/util.h: https://review.coreboot.org/c/coreboot/+/59638/comment/8cb47c2e_e5e7b595 PS8, Line 30: #if CONFIG(PLATFORM_USES_FSP2_3) : struct fsp_nvs_hob2_data_region_header { : uint64_t nvs_data_ptr; : uint64_t nvs_data_length; : } __packed; : #endif : > no need to guard this Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 9 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 23:38:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/herobrine: Initialize USB by calling SOC method
by Shelley Chen (Code Review) 01 Dec '21

01 Dec '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56093 ) Change subject: mb/google/herobrine: Initialize USB by calling SOC method ...................................................................... mb/google/herobrine: Initialize USB by calling SOC method Initialize by calling `setup_usb_host0()` from SOC code BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56093 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/mainboard.c M src/mainboard/google/herobrine/romstage.c 2 files changed, 26 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index 82c5fa9..e64fb15 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -12,6 +12,20 @@ #include <soc/qupv3_config_common.h> #include <soc/qup_se_handlers_common.h> #include <soc/qcom_qup_se.h> +#include <soc/usb/usb_common.h> +#include <soc/usb/snps_usb_phy.h> + +static struct usb_board_data usb0_board_data = { + .parameter_override_x0 = 0xe6, + .parameter_override_x1 = 0x8b, + .parameter_override_x2 = 0x16, + .parameter_override_x3 = 0x03, +}; + +static void setup_usb(void) +{ + setup_usb_host0(&usb0_board_data); +} static void configure_sdhci(void) { @@ -65,6 +79,7 @@ if (CONFIG(HEROBRINE_HAS_FINGERPRINT)) gpio_output(GPIO_FP_RST_L, 1); + setup_usb(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index ad2d2a0..2ea78b8 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -1,16 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <soc/usb/usb_common.h> #include <soc/qclib_common.h> #include "board.h" #include <soc/shrm.h> +static void prepare_usb(void) +{ + /* + * Do DWC3 core and phy reset. Kick these resets + * off early so they get at least 1ms to settle. + */ + reset_usb0(); +} + void platform_romstage_main(void) { shrm_fw_load_reset(); /* QCLib: DDR init & train */ qclib_load_and_run(); - + prepare_usb(); /* This rail needs to be stable by the time we take the FPMCU out of reset in ramstage, so already turn it on here. This needs to happen at least 200ms after this pin was first driven low in the bootblock. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Gerrit-Change-Number: 56093 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/cse: Add support to get CSME timestamps
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Bora Guvendik, Selma Bensaid, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58993 ) Change subject: soc/intel/common/cse: Add support to get CSME timestamps ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58993/comment/f747e847_313ccc37 PS3, Line 10: while `during` File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/58993/comment/3383347b_29c1436e PS3, Line 126: nit: extra line File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/58993/comment/da47504d_47084486 PS3, Line 153: /* Early boot performance data */ : /* 0: CSME ROM start execution */ : /* 1: EC Boot Load Done (CSME ROM starts main execution) */ : /* 2: CSME ROM completed execution / CSME RBE started */ : /* 3: CSME got ESE Init Done indication from ESE */ : /* 4: CSME RBE start PMC patch/es loading */ : /* 5: CSME RBE completed PMC patch/es loading */ : /* 6: CSME RBE set "Boot Stall Done" indication to PMC */ : /* 7: CSME start poll for PMC PPS register */ : /* 8: PMC set PPS */ : /* 9: CSME BUP start running */ : /* 10: CSME set "Host Boot Prep Done" indication to PMC */ : /* 11: CSME starts PHYs loading */ : /* 12: CSME completed PHYs loading */ : /* 13: PMC indicated CSME that xxPWRGOOD was asserted */ : /* 14: PMC indicated CSME that SYS_PWROK was asserted */ : /* 15: PMC sent "CPU_BOOT_CONFIG" start message to CSME */ : /* 16: CSME sent "CPU_BOOT_CONFIG" done message to PMC */ : /* 17: PMC indicated CSME that xxPLTRST was de-asserted */ : /* 18: PMC indicated CSME that TCO_S0 was asserted */ : /* 19: PMC sent "Core Reset Done Ack - Sent" message to CSME */ : /* 20: ACM Active indication - ACM started its execution */ : /* 21: ACM Done indication - ACM completed execution */ : /* 22: BIOS sent DRAM Init Done message */ : /* 23: CSME sent DRAM Init Done message back to BIOS */ : /* 24: CSME completed loading TCSS */ : /* 25: CSME started loading ISH Bringup module */ : /* 26: CSME completed loading ISH Bringup module */ : /* 27: CSME started loading ISH Main module */ : /* 28: CSME completed loading Main module */ : /* 29: BIOS sent "End Of Post" message to CSME */ : /* 30: CSME sent "End Of Post" ack message back to BIOS */ : /* 31: BIOS sent "Core BIOS Done" message to CSME */ : /* 32: CSME sent "Core BIOS Done" ack message back to BIOS */ : /* 33: CSME reached Firmware Init Done */ : /* 34 - 63 Reserved */ Should we make these an enum ? -- To view, visit https://review.coreboot.org/c/coreboot/+/58993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66 Gerrit-Change-Number: 58993 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 23:28:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STOR...
by build bot (Jenkins) (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Subrata Banik, Andrey Petrov, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STORAGE_HOB2 HOB introduced in FSP 2.3 ...................................................................... Patch Set 9: (2 comments) File src/drivers/intel/fsp2_0/hand_off_block.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134695): https://review.coreboot.org/c/coreboot/+/59638/comment/efbc183e_4ac8fdb6 PS9, Line 325: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134695): https://review.coreboot.org/c/coreboot/+/59638/comment/3fee4c22_05bac945 PS9, Line 325: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 9 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 23:27:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Remove deprecated APIs
by Julius Werner (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Christian Walter, Werner Zeh, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59682 ) Change subject: cbfs: Remove deprecated APIs ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59682/comment/cc6f004c_95120a40 PS2, Line 10: new > Sorry I was not following this closely. What is the new API? Providing a CL link would be nice. I just mean the whole CBFS stack rewrite I've been doing (on and off) for the last two years, replacing the commonlib/cbfs.c code with commonlib/bsd/cbfs_private.c, and replacing all the top-level CBFS APIs with cbfs_load()/cbfs_map() and their variations. Added a few CL links here to clarify. Patchset: PS2: > I did one additional comparison. Same code base but now with TPM_MEASURED_BOOT disabled. […] Thanks for testing Werner! These results are indeed very strange, and I get the feeling that there might be something fundamentally wrong on your platform that is only exacerbated by subtle changes in behavior here. Loading a payload should probably not take over two seconds, unless it is ridiculously huge... how big is the payload you use? And do you happen to know the SPI bus speed for your platform? The only guess I have what can cause this is that the tpm_measure_region() code would load data in 1KB chunks onto the stack before hashing, while the new flow here runs the hash algorithm directly on the memory-mapped buffer (ironically, I asked Philipp to do that to make it work on Arm platforms back when he added that code, originally he was also just mapping the whole thing and hashing that directly because he was only testing on x86). My (very limited) understanding of the whole x86 flash-mapping thing is that all of this gets magically cached to the point where the access pattern differences shouldn't matter and the memory-mapped regions can basically be treated like (read-only) RAM. I guess that may not be true on your platform. Is it possible that something (e.g. some MTRR thing) is misconfigured to disable this caching? Anyway, it should be pretty simple to figure out if this is it: I've uploaded a test CL CB:59767 which just loads the whole payload into RAM before doing anything else with it. Can you try that out and see what difference it makes for your boot times? (If that's not it, could you try narrowing down a bit further where exactly all this time is spent for you? E.g. just sprinkle some timestamp_add_now(1234) with increasing ID numbers throughout the code to see where the big delay comes from.) File src/security/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/59682/comment/93ced10c_3c77abe7 PS2, Line 254: CBFS will look for a file in the RO : (COREBOOT) region > This reads a little bit weird to me, as the filesystem doesn't do it by itself. How about […] Changed to "the CBFS code". -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 23:26:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST-ONLY / HACK] Mirror payload in RAM before hashing/decompression
by Julius Werner (Code Review) 01 Dec '21

01 Dec '21

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59767 ) Change subject: [TEST-ONLY / HACK] Mirror payload in RAM before hashing/decompression ...................................................................... [TEST-ONLY / HACK] Mirror payload in RAM before hashing/decompression I don't know if this does anything... let's find out. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ia9550ad35653f1c949fe1dd83f76142ed3dbad4c --- M src/lib/cbfs.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59767/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index dfb7a69..5906814 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -470,6 +470,16 @@ if (!force_ro && get_preload_rdev(&rdev, name) == CB_SUCCESS) preload_successful = true; + if (ENV_RAMSTAGE && !strcmp(name, CONFIG_CBFS_PREFIX "/payload")) { + size_t size = region_device_sz(&rdev); + void *buffer = bootmem_allocate_buffer(size); + if (!buffer || + rdev_readat_full(&rdev, buffer) != size || + rdev_chain_mem(&rdev, buffer, size) != 0) + die("splat!"); + printk(BIOS_DEBUG, "HACK: mirrored payload rdev into RAM at %p\n", buffer); + } + void *ret = do_alloc(&mdata, &rdev, allocator, arg, size_out, false); /* When using cbfs_preload we need to free the preload buffer after populating the -- To view, visit https://review.coreboot.org/c/coreboot/+/59767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9550ad35653f1c949fe1dd83f76142ed3dbad4c Gerrit-Change-Number: 59767 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfs: Remove deprecated APIs
by Julius Werner (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Christian Walter. Hello build bot (Jenkins), Jakub Czapiga, Christian Walter, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59682 to look at the new patch set (#3). Change subject: cbfs: Remove deprecated APIs ...................................................................... cbfs: Remove deprecated APIs This patch removes all remaining pieces of the old CBFS API, now that the last straggling use cases of it have been ported to the new one (meaning cbfs_map()/cbfs_load()/etc... see CB:39304 and CB:38421). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c --- M src/commonlib/Makefile.inc D src/commonlib/cbfs.c D src/commonlib/include/commonlib/cbfs.h M src/include/cbfs.h M src/lib/cbfs.c M src/security/tpm/tspi/crtm.h M src/security/vboot/Kconfig 7 files changed, 3 insertions(+), 483 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59682/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbfs | tspi: Join hash calculation for verification and measurement
by Julius Werner (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Jakub Czapiga, Christian Walter, Julius Werner, Arthur Heymans, Werner Zeh. Hello build bot (Jenkins), Raul Rangel, Jakub Czapiga, Christian Walter, Arthur Heymans, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59681 to look at the new patch set (#3). Change subject: cbfs | tspi: Join hash calculation for verification and measurement ...................................................................... cbfs | tspi: Join hash calculation for verification and measurement This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT is enabled from the lookup step into the code where a file is actually loaded or mapped from flash. This has the advantage that CBFS routines which just look up a file to inspect its metadata (e.g. cbfs_get_size()) do not cause the file to be measured twice. It also removes the existing inefficiency that files are loaded twice when measurement is enabled (once to measure and then again when they are used). When CBFS verification is enabled and uses the same hash algorithm as the TPM, we are even able to only hash the file a single time and use the result for both purposes. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I70d7066c6768195077f083c7ffdfa30d9182b2b7 --- M src/lib/cbfs.c M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/crtm.h M src/security/tpm/tspi/tspi.c 5 files changed, 59 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/59681/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70d7066c6768195077f083c7ffdfa30d9182b2b7 Gerrit-Change-Number: 59681 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/usb4/retimer: Add function to correct EC port mapping
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Maulik V Vaghela, Sugnan Prabhu S, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59665 ) Change subject: drivers/intel/usb4/retimer: Add function to correct EC port mapping ...................................................................... Patch Set 6: (2 comments) File src/drivers/intel/usb4/retimer/retimer.h: https://review.coreboot.org/c/coreboot/+/59665/comment/f1a2c2c9_aa75a14b PS5, Line 42: map_physical_port_to_ec_port I think keeping `retimer` in the name here is probably a good idea, just for context. I know it's already long... but WDYT about `retimer_get_index_for_type_c(uint8_t typec_port)`; https://review.coreboot.org/c/coreboot/+/59665/comment/e624124d_a8aea3e5 PS5, Line 42: usb_port since this really represents the Type-C ports, would naming this `typec_port` be more descriptive? -- To view, visit https://review.coreboot.org/c/coreboot/+/59665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Gerrit-Change-Number: 59665 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 23:21:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STOR...
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Anil Kumar K, Subrata Banik, Andrey Petrov, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STORAGE_HOB2 HOB introduced in FSP 2.3 ...................................................................... Patch Set 8: (3 comments) File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/59638/comment/efa6cc5d_3833edd5 PS8, Line 25: #if CONFIG(PLATFORM_USES_FSP2_3) suggestion: don't guard the definition of this, I will explain more below https://review.coreboot.org/c/coreboot/+/59638/comment/e051127d_51bb27cf PS8, Line 318: #if CONFIG(PLATFORM_USES_FSP2_3) : : void *hob_ptr = NULL; : hob_ptr = fsp_find_extension_hob_by_guid(fsp_nv_storage_guid_2, size); : if (hob_ptr != NULL) { : size = (fsp_nvs_hob2_data_region_header *) hob_ptr->nvs_data_length; : return (fsp_nvs_hob2_data_region_header *) hob_ptr->nvs_data_ptr; : } : #endif : return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size); suggestion: we don't need the preprocessor, we can just do something like ``` if (CONFIG(PLATFORM_USES_FSP2_3)) { void *hob_ptr = NULL; hob_ptr = fsp_find_extension_hob_by_guid(fsp_nv_storage_guid_2, size); if (hob_ptr != NULL) { size = (fsp_nvs_hob2_data_region_header *) hob_ptr->nvs_data_length; return (fsp_nvs_hob2_data_region_header *) hob_ptr->nvs_data_ptr; } } else { return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size); } ``` File src/drivers/intel/fsp2_0/include/fsp/util.h: https://review.coreboot.org/c/coreboot/+/59638/comment/efdc3b0c_51e538db PS8, Line 30: #if CONFIG(PLATFORM_USES_FSP2_3) : struct fsp_nvs_hob2_data_region_header { : uint64_t nvs_data_ptr; : uint64_t nvs_data_length; : } __packed; : #endif : no need to guard this -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 8 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 23:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021