coreboot-gerrit November 2021

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Change in coreboot[master]: mb/siemens/mc_ehl: Set MAC address for all enabled TSN GbE
by Mario Scheithauer (Code Review) 02 Nov '21

02 Nov '21

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58849 ) Change subject: mb/siemens/mc_ehl: Set MAC address for all enabled TSN GbE ...................................................................... mb/siemens/mc_ehl: Set MAC address for all enabled TSN GbE This mainboard uses all available TSE GbE controllers. Therefore we need a function to set the MAC address by using of Siemens hwilib. Change-Id: I77e1dbbb3d0a791f33f63626663f6f65a8626d0f Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/mainboard.c 1 file changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/58849/1 diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index e64dbda..8641428 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -89,6 +89,31 @@ return CB_ERR; } +static enum cb_err set_tsn_mac_address(struct device *dev) +{ + uint8_t adr_to_set[6]; + enum cb_err status; + + /* Check first whether there is a valid MAC address available */ + status = mainboard_get_mac_address(dev, adr_to_set); + if (status != CB_SUCCESS) { + printk(BIOS_ERR, "TSN (0x%2x): No valid MAC address found\n", + dev->path.pci.devfn); + return status; + } + + uint32_t bar = (pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xFFFFF000); + if (bar) { + uint32_t *mac_p; + mac_p = (uint32_t *)(bar + 0x300); + *mac_p = (*mac_p & 0xFFFF0000) | (adr_to_set[5] << 8) | adr_to_set[4]; + mac_p++; + *mac_p = (adr_to_set[3] << 24) | (adr_to_set[2] << 16) | + (adr_to_set[1] << 8) | adr_to_set[0]; + } + return CB_SUCCESS; +} + static void wait_for_legacy_dev(void *unused) { uint32_t legacy_delay, us_since_boot; @@ -140,6 +165,34 @@ if (dev) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } + + // set mac address for 1e.4 tsn + dev = dev_find_device(PCI_VENDOR_ID_INTEL, 0x4b32, 0); + if (dev) { + enum cb_err status; + status = set_tsn_mac_address(dev); + if (!status) + printk(BIOS_INFO, "TSN (1e.4 - SGMII - X127): Update MAC " + "address successful\n"); + } + // set mac address for 1d.1 tsn + dev = dev_find_device(PCI_VENDOR_ID_INTEL, 0x4ba0, 0); + if (dev) { + enum cb_err status; + status = set_tsn_mac_address(dev); + if (!status) + printk(BIOS_INFO, "TSN (1d.1 - RGMII P0 - X120/X170): " + "Update MAC address successful\n"); + } + // set mac address for 1d.2 tsn + dev = dev_find_device(PCI_VENDOR_ID_INTEL, 0x4bb0, 0); + if (dev) { + enum cb_err status; + status = set_tsn_mac_address(dev); + if (!status) + printk(BIOS_INFO, "TSN (1d.2 - RGMII P1 - X130/X160): " + "Update MAC address successful\n"); + } } /* The following function performs board specific things. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77e1dbbb3d0a791f33f63626663f6f65a8626d0f Gerrit-Change-Number: 58849 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Mario Scheithauer (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, Felix Held. Mario Scheithauer has uploaded a new patch set (#45) to the change originally created by Lean Sheng Tan. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... soc/intel/elkhartlake: Introduce Intel PSE The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and it's peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enables the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 156 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/45 -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 45 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge
by Casper Chang (Code Review) 02 Nov '21

02 Nov '21

Casper Chang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58831 ) Change subject: mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/58831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7236fc7f3318d07f0d9e9d9da7cd463ef3dde1a0 Gerrit-Change-Number: 58831 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO drivers
by build bot (Jenkins) (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58836 ) Change subject: soc/mediatek/mt8186: Add GPIO drivers ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8186/include/soc/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132005): https://review.coreboot.org/c/coreboot/+/58836/comment/453b6ddf_9cb5f7d6 PS3, Line 21: #define PIN(id, name, flag, bit, base, offset, \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/58836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Gerrit-Change-Number: 58836 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 10:05:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree
by Mario Scheithauer (Code Review) 02 Nov '21

02 Nov '21

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58848 ) Change subject: mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree ...................................................................... mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree On mc_ehl2 there are currently four of the six PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device. Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I81419887b7f463a937917b971465245c1cb46b94 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/58848/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 451c5dd..8b9e9e2 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -55,19 +55,19 @@ register "PcieRpEnable[5]" = "1" register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "0x00" - register "PcieClkSrcUsage[1]" = "0x01" - register "PcieClkSrcUsage[2]" = "0x02" - register "PcieClkSrcUsage[3]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcClkReq[0]" = "0xFF" - register "PcieClkSrcClkReq[1]" = "0xFF" - register "PcieClkSrcClkReq[2]" = "0xFF" - register "PcieClkSrcClkReq[3]" = "0xFF" - register "PcieClkSrcClkReq[4]" = "0xFF" - register "PcieClkSrcClkReq[5]" = "0xFF" + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Disable all L1 substates for PCIe root ports register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" -- To view, visit https://review.coreboot.org/c/coreboot/+/58848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81419887b7f463a937917b971465245c1cb46b94 Gerrit-Change-Number: 58848 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/mc_ehl: Invert PHY to MAC Interrupt Polarity for TSN GbE
by Mario Scheithauer (Code Review) 02 Nov '21

02 Nov '21

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58847 ) Change subject: mb/siemens/mc_ehl: Invert PHY to MAC Interrupt Polarity for TSN GbE ...................................................................... mb/siemens/mc_ehl: Invert PHY to MAC Interrupt Polarity for TSN GbE Invert PHY to MAC Interrupt Polarity for enabled TSN GbE controller. Change-Id: I440ed5b61b2704af36ee7b1e7dd59435720763c0 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/mainboard.c 1 file changed, 115 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/58847/1 diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index 8641428..242b5d6 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <bootstate.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -17,6 +18,26 @@ #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 +#define B_TSN_MEM_MAC_MDIO_ADDRESS_MASK 0x03FF7F0E +#define R_TSN_MEM_MAC_MDIO_ADDRESS 0x200 +#define R_TSN_MEM_MAC_MDIO_DATA 0x204 +#define N_TSN_MEM_MAC_MDIO_REGAD 0x10 +#define V_TSN_MEM_MAC_MDIO_GCR 0x0 +#define N_TSN_MEM_MAC_MDIO_PHYAD 0x15 +#define V_TSN_MEM_MAC_MDIO_ADHOC_GCR_ADD 0x15 +#define N_TSN_MEM_MAC_MDIO_CLK_TRAIL 0xC +#define V_TSN_MEM_MAC_MDIO_CLK_TRAIL 0x4 +#define N_TSN_MEM_MAC_MDIO_CLK_CSR 0x8 +#define V_TSN_MEM_MAC_MDIO_CLK_CSR_DIV_10 0xB +#define V_TSN_MEM_MAC_MDIO_GMII_22_PHY_READ 0x0C +#define V_TSN_MEM_MAC_MDIO_GMII_22_PHY_WRITE 0x04 +#define B_TSN_MEM_MAC_MDIO_GMII_BUSY (1 << 0) + +#define B_TSN_MEM_MAC_ADHOC_PHY2MAC_INTR_POL (1 << 6) + +#define TSN_MAX_LOOP_TIME 4000 +#define TSN_GMII_DELAY 50 + /** \brief This function can decide if a given MAC address is valid or not. * Currently, addresses filled with 0xff or 0x00 are not valid. * @param mac Buffer to the MAC address to check @@ -114,6 +135,67 @@ return CB_SUCCESS; } +static int32_t PhyGmiiBusyStatus(uint32_t TsnBar0) +{ + uint32_t Count; + + for (Count = 0; Count < TSN_MAX_LOOP_TIME; ++Count) { + if (read32((void *)(TsnBar0 + R_TSN_MEM_MAC_MDIO_ADDRESS)) & + B_TSN_MEM_MAC_MDIO_GMII_BUSY) + udelay(TSN_GMII_DELAY); + else + return CB_SUCCESS; + } + printk(BIOS_INFO, "PhyGMIIBusyStatus Timeout in %d micro seconds\n", + TSN_MAX_LOOP_TIME * TSN_GMII_DELAY); + return CB_ERR; +} + +static uint16_t TsnMdioRead(uint32_t TsnBar0, uint8_t PhyAdd, uint8_t RegAdd) +{ + uint32_t MacMdioAddressValue; + uint16_t Data16; + enum cb_err Status; + + Data16 = 0; + MacMdioAddressValue = read32((void *)(TsnBar0 + R_TSN_MEM_MAC_MDIO_ADDRESS)); + MacMdioAddressValue &= (uint32_t)~(B_TSN_MEM_MAC_MDIO_ADDRESS_MASK); + MacMdioAddressValue |= (PhyAdd << N_TSN_MEM_MAC_MDIO_PHYAD) + | (RegAdd << N_TSN_MEM_MAC_MDIO_REGAD) + | (V_TSN_MEM_MAC_MDIO_CLK_TRAIL << N_TSN_MEM_MAC_MDIO_CLK_TRAIL) + | (V_TSN_MEM_MAC_MDIO_CLK_CSR_DIV_10 << N_TSN_MEM_MAC_MDIO_CLK_CSR) + | V_TSN_MEM_MAC_MDIO_GMII_22_PHY_READ | B_TSN_MEM_MAC_MDIO_GMII_BUSY; + write32((void *)(TsnBar0 + R_TSN_MEM_MAC_MDIO_ADDRESS), MacMdioAddressValue); + + // Wait for MDIO frame transfer complete before reading MDIO DATA register + Status = PhyGmiiBusyStatus(TsnBar0); + if (Status == CB_ERR) + printk(BIOS_INFO, "TSN GMII Busy. MIDO PhyAdd: 0x%x, Register 0x%x read " + "invalid\n", PhyAdd, RegAdd); + Data16 = read16((void *)(TsnBar0 + R_TSN_MEM_MAC_MDIO_DATA)); + printk(BIOS_INFO, "TSN MDIO Read PhyAdd: 0x%x, RegAdd: 0x%x , Value: 0x%x, " + "Raw: 0x%x\n", PhyAdd, RegAdd, Data16, MacMdioAddressValue); + return Data16; +} + +static void TsnMdioWrite(uint32_t TsnBar0, uint8_t PhyAdd, uint8_t RegAdd, + uint16_t DataValue) +{ + uint32_t MacMdioAddressValue; + + write16((void *)(TsnBar0 + R_TSN_MEM_MAC_MDIO_DATA), DataValue); + MacMdioAddressValue = read32((void *)(TsnBar0 + R_TSN_MEM_MAC_MDIO_ADDRESS)); + MacMdioAddressValue &= (uint32_t)~(B_TSN_MEM_MAC_MDIO_ADDRESS_MASK); + MacMdioAddressValue |= (PhyAdd << N_TSN_MEM_MAC_MDIO_PHYAD) + | (RegAdd << N_TSN_MEM_MAC_MDIO_REGAD) + | (V_TSN_MEM_MAC_MDIO_CLK_TRAIL << N_TSN_MEM_MAC_MDIO_CLK_TRAIL) + | (V_TSN_MEM_MAC_MDIO_CLK_CSR_DIV_10 << N_TSN_MEM_MAC_MDIO_CLK_CSR) + | V_TSN_MEM_MAC_MDIO_GMII_22_PHY_WRITE | B_TSN_MEM_MAC_MDIO_GMII_BUSY; + write32((void *)(TsnBar0 + R_TSN_MEM_MAC_MDIO_ADDRESS), MacMdioAddressValue); + printk(BIOS_INFO, "TSN MDIO Write PhyAdd: 0x%x, RegAdd: 0x%x, Value : 0x%x, " + "Raw: 0x%x\n", PhyAdd, RegAdd, DataValue, MacMdioAddressValue); +} + static void wait_for_legacy_dev(void *unused) { uint32_t legacy_delay, us_since_boot; @@ -174,6 +256,17 @@ if (!status) printk(BIOS_INFO, "TSN (1e.4 - SGMII - X127): Update MAC " "address successful\n"); + uint32_t bar = (pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xFFFFF000); + if (bar) { + uint16_t GcrValue; + + // Reading Tsn Adhoc Register GCR mgbe_mdio + GcrValue = TsnMdioRead(bar, V_TSN_MEM_MAC_MDIO_ADHOC_GCR_ADD, + V_TSN_MEM_MAC_MDIO_GCR); + GcrValue |= B_TSN_MEM_MAC_ADHOC_PHY2MAC_INTR_POL; + TsnMdioWrite(bar, V_TSN_MEM_MAC_MDIO_ADHOC_GCR_ADD, + V_TSN_MEM_MAC_MDIO_GCR, GcrValue); + } } // set mac address for 1d.1 tsn dev = dev_find_device(PCI_VENDOR_ID_INTEL, 0x4ba0, 0); @@ -183,6 +276,17 @@ if (!status) printk(BIOS_INFO, "TSN (1d.1 - RGMII P0 - X120/X170): " "Update MAC address successful\n"); + uint32_t bar = (pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xFFFFF000); + if (bar) { + uint16_t GcrValue; + + // Reading Tsn Adhoc Register GCR mgbe_mdio + GcrValue = TsnMdioRead(bar, V_TSN_MEM_MAC_MDIO_ADHOC_GCR_ADD, + V_TSN_MEM_MAC_MDIO_GCR); + GcrValue |= B_TSN_MEM_MAC_ADHOC_PHY2MAC_INTR_POL; + TsnMdioWrite(bar, V_TSN_MEM_MAC_MDIO_ADHOC_GCR_ADD, + V_TSN_MEM_MAC_MDIO_GCR, GcrValue); + } } // set mac address for 1d.2 tsn dev = dev_find_device(PCI_VENDOR_ID_INTEL, 0x4bb0, 0); @@ -192,6 +296,17 @@ if (!status) printk(BIOS_INFO, "TSN (1d.2 - RGMII P1 - X130/X160): " "Update MAC address successful\n"); + uint32_t bar = (pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xFFFFF000); + if (bar) { + uint16_t GcrValue; + + // Reading Tsn Adhoc Register GCR mgbe_mdio + GcrValue = TsnMdioRead(bar, V_TSN_MEM_MAC_MDIO_ADHOC_GCR_ADD, + V_TSN_MEM_MAC_MDIO_GCR); + GcrValue |= B_TSN_MEM_MAC_ADHOC_PHY2MAC_INTR_POL; + TsnMdioWrite(bar, V_TSN_MEM_MAC_MDIO_ADHOC_GCR_ADD, + V_TSN_MEM_MAC_MDIO_GCR, GcrValue); + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/58847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I440ed5b61b2704af36ee7b1e7dd59435720763c0 Gerrit-Change-Number: 58847 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/mc_ehl: Set MAC address for all enabled TSN GbE
by Mario Scheithauer (Code Review) 02 Nov '21

02 Nov '21

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58846 ) Change subject: mb/siemens/mc_ehl: Set MAC address for all enabled TSN GbE ...................................................................... mb/siemens/mc_ehl: Set MAC address for all enabled TSN GbE This mainboard uses all available TSE GbE controllers. Therefore we need a function to set the MAC address by using of Siemens hwilib. Change-Id: I77e1dbbb3d0a791f33f63626663f6f65a8626d0f Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/mainboard.c 1 file changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/58846/1 diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index e64dbda..8641428 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -89,6 +89,31 @@ return CB_ERR; } +static enum cb_err set_tsn_mac_address(struct device *dev) +{ + uint8_t adr_to_set[6]; + enum cb_err status; + + /* Check first whether there is a valid MAC address available */ + status = mainboard_get_mac_address(dev, adr_to_set); + if (status != CB_SUCCESS) { + printk(BIOS_ERR, "TSN (0x%2x): No valid MAC address found\n", + dev->path.pci.devfn); + return status; + } + + uint32_t bar = (pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xFFFFF000); + if (bar) { + uint32_t *mac_p; + mac_p = (uint32_t *)(bar + 0x300); + *mac_p = (*mac_p & 0xFFFF0000) | (adr_to_set[5] << 8) | adr_to_set[4]; + mac_p++; + *mac_p = (adr_to_set[3] << 24) | (adr_to_set[2] << 16) | + (adr_to_set[1] << 8) | adr_to_set[0]; + } + return CB_SUCCESS; +} + static void wait_for_legacy_dev(void *unused) { uint32_t legacy_delay, us_since_boot; @@ -140,6 +165,34 @@ if (dev) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } + + // set mac address for 1e.4 tsn + dev = dev_find_device(PCI_VENDOR_ID_INTEL, 0x4b32, 0); + if (dev) { + enum cb_err status; + status = set_tsn_mac_address(dev); + if (!status) + printk(BIOS_INFO, "TSN (1e.4 - SGMII - X127): Update MAC " + "address successful\n"); + } + // set mac address for 1d.1 tsn + dev = dev_find_device(PCI_VENDOR_ID_INTEL, 0x4ba0, 0); + if (dev) { + enum cb_err status; + status = set_tsn_mac_address(dev); + if (!status) + printk(BIOS_INFO, "TSN (1d.1 - RGMII P0 - X120/X170): " + "Update MAC address successful\n"); + } + // set mac address for 1d.2 tsn + dev = dev_find_device(PCI_VENDOR_ID_INTEL, 0x4bb0, 0); + if (dev) { + enum cb_err status; + status = set_tsn_mac_address(dev); + if (!status) + printk(BIOS_INFO, "TSN (1d.2 - RGMII P1 - X130/X160): " + "Update MAC address successful\n"); + } } /* The following function performs board specific things. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77e1dbbb3d0a791f33f63626663f6f65a8626d0f Gerrit-Change-Number: 58846 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Mario Scheithauer (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Mario Scheithauer has uploaded a new patch set (#44) to the change originally created by Lean Sheng Tan. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... soc/intel/elkhartlake: Introduce Intel PSE The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite, and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and it's peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings, and many of the integrated peripherals can be assigned either to the PSE or to the x86 subsystem. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (HW overview) and #614110 (PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 156 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 44 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amd/lpc: Remove weak function
by Bao Zheng (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58843 to look at the new patch set (#4). Change subject: amd/lpc: Remove weak function ...................................................................... amd/lpc: Remove weak function Change-Id: I39ae6405589d645eaa3e05759b1ffbd36e688d8f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/58843/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39ae6405589d645eaa3e05759b1ffbd36e688d8f Gerrit-Change-Number: 58843 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add an overridable function for WDT clear status
by Rex-BC Chen (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58834 ) Change subject: soc/mediatek: Add an overridable function for WDT clear status ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58834/comment/791002b0_29fbf709 PS2, Line 7: soc define > an overridable Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Gerrit-Change-Number: 58834 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 09:38:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021