coreboot-gerrit November 2021

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Change in coreboot[master]: treewide: Remove unused spinlock functions
by Tim Wawrzynczak (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59020 ) Change subject: treewide: Remove unused spinlock functions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e9a742e6b311d972a260039401bfd8f8766dd36 Gerrit-Change-Number: 59020 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 23:39:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Use LZ4 for FSP-S
by Karthik Ramasubramanian (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59026 ) Change subject: soc/amd/cezanne: Use LZ4 for FSP-S ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59026/comment/d8c4a5eb_1164e3fa PS1, Line 9: This change increases the fsps.bin by 20 KiB What is the impact to verstage verifying the increased FW body size? -- To view, visit https://review.coreboot.org/c/coreboot/+/59026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Gerrit-Change-Number: 59026 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 23:38:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne,picasso/include/southbridge: fix typo in define
by Raul Rangel (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59028 ) Change subject: soc/amd/cezanne,picasso/include/southbridge: fix typo in define ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a Gerrit-Change-Number: 59028 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 23:30:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Preload FSP-S
by Karthik Ramasubramanian (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59025 ) Change subject: soc/amd/cezanne: Preload FSP-S ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/preload.c: https://review.coreboot.org/c/coreboot/+/59025/comment/94658999_f5b69096 PS1, Line 6: static void start_fspm_preload(void *unused) fsps_preload? -- To view, visit https://review.coreboot.org/c/coreboot/+/59025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95 Gerrit-Change-Number: 59025 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 23:21:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne,picasso/include/southbridge: fix typo in define
by Felix Held (Code Review) 09 Nov '21

09 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59028 ) Change subject: soc/amd/cezanne,picasso/include/southbridge: fix typo in define ...................................................................... soc/amd/cezanne,picasso/include/southbridge: fix typo in define In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16 of the misc I2C pad control registers is defined as BiasCrtEn, so rename I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a --- M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/picasso/include/soc/southbridge.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/59028/1 diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index addb850..1e3697b 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -118,7 +118,7 @@ #define I2C_PAD_CTRL_CAP_UP BIT(13) #define I2C_PAD_CTRL_RES_DOWN BIT(14) #define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index f547f86..300f458 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -115,7 +115,7 @@ #define I2C_PAD_CTRL_CAP_UP BIT(13) #define I2C_PAD_CTRL_RES_DOWN BIT(14) #define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) -- To view, visit https://review.coreboot.org/c/coreboot/+/59028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a Gerrit-Change-Number: 59028 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google,samsung: Refactor init_bootmode_straps()
by Julius Werner (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59008 ) Change subject: mb/google,samsung: Refactor init_bootmode_straps() ...................................................................... Patch Set 2: (1 comment) File src/include/bootmode.h: https://review.coreboot.org/c/coreboot/+/59008/comment/15581748_290e740a PS2, Line 19: void stash_bootmode(int flag_spi_wp, int flag_rec_mode); This is an old ugly hack on ancient devices that I'd prefer not to propagate to a top level API if possible. I don't even know why they needed to do that anyway (normally, on all the devices I've worked on, re-reading a GPIO in a later stage is not a big deal that requires caching). I don't think we'll ever need this again. If you think we need to deduplicate the code from the old boards, please hide it away in some Intel southbridge header. -- To view, visit https://review.coreboot.org/c/coreboot/+/59008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Gerrit-Change-Number: 59008 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 22:59:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Rename ECAM-specific MMCONF Kconfigs
by Shelley Chen (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Stefan Reinauer, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Morgan Jang, Michal Motyl, Alexander Couzens, Felix Held, Furquan Shaikh, Angel Pons, Lance Zhao, Jason Glenesk, Martin Roth, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57333 ) Change subject: Rename ECAM-specific MMCONF Kconfigs ...................................................................... Patch Set 10: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/57333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Gerrit-Change-Number: 57333 Gerrit-PatchSet: 10 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 22:54:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs
by Julius Werner (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Kyösti Mälkki, Andrey Petrov, Alexander Couzens, Patrick Rudolph, Yu-Ping Wu, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58968 ) Change subject: [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58968/comment/eb10a215_99027297 PS3, Line 11: from soc/. I think MRC_SETTINGS_PROTECT is supposed to be a capability Kconfig (i.e. "this platform supports MRC settings protection"), not a choice Kconfig ("I want to protect MRC settings"). Not sure why it is menuconfig visible, that might be a mistake. You can't just remove it from the SoC and turn it on by default for CONFIG_CHROMEOS, because some platforms that use the MRC cache driver (e.g. recent Arm devices) don't support flash-controller-based protection. I think we just don't have a user choice Kconfig for this because nobody ever needed one. Why do you think it's necessary? There should never really be a reason for the OS to touch the MRC cache anyway so I think the idea was just that nobody would ever have a reason not to want it protected. File src/security/vboot/bootmode.c: https://review.coreboot.org/c/coreboot/+/58968/comment/6df03d27_08547714 PS3, Line 65: int __weak get_write_protect_state(void) Moving this out of VBOOT_NO_BOARD_SUPPORT makes me uneasy because that makes it easier to accidentally forget to override this function and not notice. There is no other way that would be visible other than the MRC cache being unprotected. Honestly, I'm not sure there's a reason to explicitly check the hardware WP# line for this anyway. If the flash is unprotected, the status register SRP0 would also be disabled anyway. We used to do that because we had that GPIO available for vboot anyway (in fact I believe it started like that and the extra SRP0 check was added later), but now vboot doesn't need this pin anymore and having to define it for every board just for the MRC cache protection behavior seems a bit cumbersome. Maybe we can just take that part out and decide this based on SRP0 alone? -- To view, visit https://review.coreboot.org/c/coreboot/+/58968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8db0394645df1917b686339fa79432ccfc6960a2 Gerrit-Change-Number: 58968 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 22:51:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] chromeos.fmd for nissa
by Reka Norman (Code Review) 08 Nov '21

08 Nov '21

Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59027 ) Change subject: [WIP] chromeos.fmd for nissa ...................................................................... [WIP] chromeos.fmd for nissa This is my current estimate of the sizes required for each region on nissa. Change-Id: I3024f08a646f026c7d3d6652bcce645cd4932920 Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M src/mainboard/google/brya/chromeos.fmd 1 file changed, 14 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/59027/1 diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd index 72c6429..d2706d4 100644 --- a/src/mainboard/google/brya/chromeos.fmd +++ b/src/mainboard/google/brya/chromeos.fmd @@ -1,4 +1,4 @@ -FLASH 32M { +FLASH 22044K { SI_ALL 5M { SI_DESC 4K SI_ME { @@ -9,50 +9,40 @@ CSE_RW 3008K } } - SI_BIOS 27M { - RW_SECTION_A 8M { - VBLOCK_A 64K + SI_BIOS 16924K { + RW_SECTION_A 5826K { + VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 ME_RW_A(CBFS) 3008K } - RW_LEGACY(CBFS) 2M - RW_MISC 1M { + RW_LEGACY(CBFS) 1M + RW_MISC 152K { UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K RW_MRC_CACHE 64K } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K } - # The RW_SPD_CACHE region is only used for brya variants that use DDRx memory. - # It is placed in the common `chromeos.fmd` file because it is only 4K and there - # is free space in the RW_MISC region that cannot be easily reclaimed because - # the RW_SECTION_B must start on the 16M boundary. - RW_SPD_CACHE(PRESERVE) 4K RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K + RW_NVRAM(PRESERVE) 8K } - # This section starts at the 16M boundary in SPI flash. - # ADL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 8M { - VBLOCK_B 64K + RW_SECTION_B 5826K { + VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 ME_RW_B(CBFS) 3008K } # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO 8M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K RO_FRID 64 - GBB@4K 448K + GBB@4K 12K COREBOOT(CBFS) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/59027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3024f08a646f026c7d3d6652bcce645cd4932920 Gerrit-Change-Number: 59027 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Use LZ4 for FSP-S
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59026 ) Change subject: soc/amd/cezanne: Use LZ4 for FSP-S ...................................................................... soc/amd/cezanne: Use LZ4 for FSP-S This change increases the fsps.bin by 20 KiB, but it decreases decompression time. When not using preloading we save about 6 ms, when using preloading we save about 8. BUG=b:179699789 TEST=Boot nipperkin to OS Using FSP-S preload: | 30 - device enumeration | 2.073 | 2.312 Δ( 0.24, 0.02%) | | 971 - loading FSP-S | 6.628 | 7.227 Δ( 0.60, 0.04%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.01 | 0.01 Δ( 0.00, 0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 8.316 | 0.241 Δ( -8.08, -0.55%) | | 954 - calling FspSiliconInit | 0.09 | 0.089 Δ( -0.00, -0.00%) | Not using prealod: | 30 - device enumeration | 2.092 | 2.527 Δ( 0.44, 0.03%) | | 971 - loading FSP-S | 6.567 | 6.565 Δ( -0.00, -0.00%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.008 | 0.008 Δ( 0.00, 0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 15.165 | 8.998 Δ( -6.17, -0.40%) | | 954 - calling FspSiliconInit | 0.037 | 0.038 Δ( 0.00, 0.00%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/59026/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 6af0abb..fc0173a 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -21,7 +21,7 @@ select DRIVERS_I2C_DESIGNWARE select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA - select FSP_COMPRESS_FSP_S_LZMA + select FSP_COMPRESS_FSP_S_LZ4 select GENERIC_GPIO_LIB select HAVE_ACPI_TABLES select HAVE_CF9_RESET -- To view, visit https://review.coreboot.org/c/coreboot/+/59026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Gerrit-Change-Number: 59026 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021