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Change subject: [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58968/comment/57de5b7c_c2ec0c51
PS3, Line 11: from soc/.
> I think MRC_SETTINGS_PROTECT is supposed to be a capability Kconfig (i.e. […]
I think there may be some cases where developers will want to overwrite the entire SPI flash image in a running system, from OS with flashrom.
File src/security/vboot/bootmode.c:
https://review.coreboot.org/c/coreboot/+/58968/comment/c48102e4_82e6e56b
PS3, Line 65: int __weak get_write_protect_state(void)
> Moving this out of VBOOT_NO_BOARD_SUPPORT makes me uneasy because that makes it easier to accidental […]
Yeah, I thought checking write_protect_state() might be dropped entirely.
Should we keep it at all, I have some plans to avoid the accident of hitting the __weak functions unintentionaly.
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Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58734 )
Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
......................................................................
Patch Set 6:
(4 comments)
File src/mainboard/google/dedede/variants/galtic/variant.c:
https://review.coreboot.org/c/coreboot/+/58734/comment/c25eb494_cd7800a0
PS6, Line 23: return "wifi_sar-galtic.hex";
> sorry, could I know why default sar file recommend to use galtic sar file? […]
Oh, just because in original code, galtic was returned so I think the default one would be galtic. But it should be fine if you set galith is the default one in CL:3267913
https://review.coreboot.org/c/coreboot/+/58734/comment/cdbc8b21_f1ace713
PS6, Line 27: galith
> According to the result of RF measurement, both of galith/gallop wifi sar table is the same
As you mentioned, if galith is the default SAR table defined in CL:3267913 then you can just have line 32 to return WIFI_SAR_CBFS_DEFAULT_FILENAME and remove line 24 ~ 27?
https://review.coreboot.org/c/coreboot/+/58734/comment/aa54f675_4782a657
PS6, Line 31: return "wifi_sar-galith360.hex";
nit: a new line before line 32 please.
https://review.coreboot.org/c/coreboot/+/58734/comment/b7c32c24_b7589e41
PS6, Line 32: return "WIFI_SAR_CBFS_DEFAULT_FILENAME";
> https://chromium-review.googlesource. […]
By the way, WIFI_SAR_CBFS_DEFAULT_FILENAME should be returned instead of "WIFI_SAR_CBFS_DEFAULT_FILENAME"?
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Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/google/dedede/variants/galtic/variant.c:
https://review.coreboot.org/c/coreboot/+/58734/comment/c3519775_fb9789b9
PS6, Line 23: return "wifi_sar-galtic.hex";
> +1
sorry, could I know why default sar file recommend to use galtic sar file?
I am used to galith sar file for default, because galith is in PVT stage
https://review.coreboot.org/c/coreboot/+/58734/comment/72caf1ac_f3d797d5
PS6, Line 27: galith
> I dont see a specific SAR file for Gallop.
According to the result of RF measurement, both of galith/gallop wifi sar table is the same
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Change subject: sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA
......................................................................
Patch Set 2: Code-Review+2
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Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: add generic gpio lock mechanism
......................................................................
soc/intel/common: add generic gpio lock mechanism
For added security, there are some gpios that an SoC will want to lock
once initially configured, such as gpios attached to non-host (x86)
controllers, so that they can't be recofigured at a later point in
time by rogue code.
Likewise, a mainboard may have some gpios connected to secure busses
and/or devices that they want to protect from being changed post
initial configuration.
This change adds a generic gpio locking mechanism that allows the SoC
to export a list of GPIOs to be locked down and allows the mainboard
to export a list of GPIOs that it wants locked down once
initialization is complete.
Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to
enable this feature.
BUG=b:201430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify
brya0 boots successfully to kernel.
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14
---
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/common/block/smm/Kconfig
M src/soc/intel/common/block/smm/smihandler.c
4 files changed, 171 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58351/7
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Change subject: mb/google/brya/var/felwinter: Update typeC EC mux port
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
We may need consider if EC mux port skip one like use port 0 and port 2.
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Change subject: sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59029/comment/b8b4d627_0005d3a2
PS1, Line 10: second
> ms? Same comment in the next line.
Done
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Hello Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59029
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Change subject: sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA
......................................................................
sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA
This change adds about 30 KiB to FSP-M. When not using the SPI DMA
controller, this change actually has a ~7 ms boot time penalty. When
we use the DMA engine, we end up with about a 5 ms decrease. Once we
switch to 100 MHz SPI this will help even more since we have effectively
eliminated the decompression time.
BUG=b:179699789
TEST=Boot nipperkin to OS and take boot time measurements
fspm.bin 0x2efc0 fsp 90953 LZMA (233472 decompressed)
fspm.bin 0x2cfc0 fsp 121156 LZ4 (233472 decompressed)
- FSP-M / no async -
| 508 - finished loading body | 177.019 | 179.384 Δ( 2.36, 0.16%) |
...
| 970 - loading FSP-M | 0.346 | 0.346 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.01 Δ( 0.00, 0.00%) |
| 18 - finished LZ4 decompress (ignore for x86) | 53.916 | 59.475 Δ( 5.56, 0.37%) |
- FSP-M / async -
| 508 - finished loading body | 177.185 | 179.689 Δ( 2.50, 0.18%) |
...
| 970 - loading FSP-M | 0.989 | 0.99 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 9.483 | 12.877 Δ( 3.39, 0.24%) |
| 18 - finished LZ4 decompress (ignore for x86) | 10.833 | 0.312 Δ(-10.52, -0.75%) |
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59029/2
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