coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build ...
by Bill XIE (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Bill XIE, Patrick Rudolph, Angel Pons, Julius Werner, Arthur Heymans, Michael Niewöhner, Kyösti Mälkki, Aaron Durbin. Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Patrick Rudolph, Angel Pons, Julius Werner, Arthur Heymans, Michael Niewöhner, Kyösti Mälkki, Aaron Durbin, Iru Cai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51671 to look at the new patch set (#23). Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time ...................................................................... arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time According to util/kbc1126/README.md, for these ECs to work, the address and size of their two firmware should be written to $s-0x100` (`$s` means the image size, done with kbc1126_ec_insert), which means that every existing section (especially those used to store code) should not overlap this address, otherwise the bootblock will get damaged when inserting firmwares of the EC. In this commit, ecfw_ptr is a structure initialized at build time according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET (to do so, they should be redefined as hex), and linked to CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not needed at build time any more. Test passed on Elitebook Folio 9470m. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e --- M src/arch/x86/Kconfig M src/arch/x86/bootblock.ld M src/ec/hp/kbc1126/Kconfig M src/ec/hp/kbc1126/Makefile.inc A src/ec/hp/kbc1126/ecfw_ptr.c A src/ec/hp/kbc1126/ecfw_ptr.h 6 files changed, 75 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/51671/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/51671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e Gerrit-Change-Number: 51671 Gerrit-PatchSet: 23 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google,intel: Split chromeos.c files
by build bot (Jenkins) (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 ) Change subject: mb/google,intel: Split chromeos.c files ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/stout/bootmode.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132664): https://review.coreboot.org/c/coreboot/+/59011/comment/08a992e6_9953fe0b PS6, Line 44: printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", space required after that ',' (ctx:VxV) File src/mainboard/intel/kblrvp/bootmode.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132664): https://review.coreboot.org/c/coreboot/+/59011/comment/f5802284_b4bffe29 PS6, Line 21: if (google_chromeec_get_switches() & suspect code indent for conditional statements (16, 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Nov 2021 08:00:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/google,intel: Split chromeos.c files
by Kyösti Mälkki (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59018 to look at the new patch set (#6). Change subject: [WIP] mb/google,intel: Split chromeos.c files ...................................................................... [WIP] mb/google,intel: Split chromeos.c files Move all the low-level GPIO support in bootmode.c files and build them for all stages. Keep ChromeOS related ACPI and lbtable support in chromeos.c files and build them only for ramstage. Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc A src/mainboard/google/brya/variants/baseboard/brask/chromeos.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc A src/mainboard/google/brya/variants/baseboard/brya/chromeos.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/dedede/variants/baseboard/Makefile.inc A src/mainboard/google/dedede/variants/baseboard/chromeos.c M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/fizz/variants/baseboard/Makefile.inc A src/mainboard/google/fizz/variants/baseboard/chromeos.c M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/guybrush/Makefile.inc M src/mainboard/google/hatch/variants/baseboard/Makefile.inc A src/mainboard/google/hatch/variants/baseboard/chromeos.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/herobrine/Makefile.inc M src/mainboard/google/herobrine/chromeos.c M src/mainboard/google/octopus/variants/baseboard/Makefile.inc A src/mainboard/google/octopus/variants/baseboard/chromeos.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/Makefile.inc A src/mainboard/google/poppy/variants/baseboard/chromeos.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/baseboard/Makefile.inc A src/mainboard/google/reef/variants/baseboard/chromeos.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/coral/Makefile.inc A src/mainboard/google/reef/variants/coral/chromeos.c M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/google/volteer/variants/baseboard/Makefile.inc A src/mainboard/google/volteer/variants/baseboard/chromeos.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/adlrvp/gpio_m.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/Makefile.inc A src/mainboard/intel/coffeelake_rvp/variants/baseboard/chromeos.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc A src/mainboard/intel/glkrvp/variants/baseboard/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc A src/mainboard/intel/icelake_rvp/variants/icl_u/chromeos.c M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc A src/mainboard/intel/icelake_rvp/variants/icl_y/chromeos.c M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c M src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc A src/mainboard/intel/shadowmountain/variants/baseboard/chromeos.c M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/chromeos.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up4/chromeos.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 59 files changed, 260 insertions(+), 155 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59018/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/59018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7 Gerrit-Change-Number: 59018 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google,intel: Split chromeos.c files
by Kyösti Mälkki (Code Review) 09 Nov '21

09 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59011 to look at the new patch set (#6). Change subject: mb/google,intel: Split chromeos.c files ...................................................................... mb/google,intel: Split chromeos.c files Move all the low-level GPIO support in bootmode.c files and build them for all stages. Keep ChromeOS related ACPI and lbtable support in chromeos.c files and build them only for ramstage. Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/bootmode.c M src/mainboard/google/asurada/chromeos.c M src/mainboard/google/auron/Makefile.inc A src/mainboard/google/auron/bootmode.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/Makefile.inc A src/mainboard/google/beltino/bootmode.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/bootmode.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/butterfly/Makefile.inc A src/mainboard/google/butterfly/bootmode.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/bootmode.c M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/corsola/Makefile.inc R src/mainboard/google/corsola/bootmode.c M src/mainboard/google/daisy/Makefile.inc A src/mainboard/google/daisy/bootmode.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dedede/Makefile.inc A src/mainboard/google/dedede/bootmode.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/eve/Makefile.inc A src/mainboard/google/eve/bootmode.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/Makefile.inc A src/mainboard/google/fizz/bootmode.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/foster/Makefile.inc A src/mainboard/google/foster/bootmode.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/Makefile.inc A src/mainboard/google/gale/bootmode.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/Makefile.inc A src/mainboard/google/glados/bootmode.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/gru/Makefile.inc A src/mainboard/google/gru/bootmode.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/hatch/Makefile.inc A src/mainboard/google/hatch/bootmode.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/jecht/Makefile.inc A src/mainboard/google/jecht/bootmode.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/Makefile.inc A src/mainboard/google/kahlee/bootmode.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/bootmode.c M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/link/Makefile.inc A src/mainboard/google/link/bootmode.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/nyan/Makefile.inc A src/mainboard/google/nyan/bootmode.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/Makefile.inc A src/mainboard/google/nyan_big/bootmode.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/Makefile.inc A src/mainboard/google/nyan_blaze/bootmode.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/Makefile.inc A src/mainboard/google/oak/bootmode.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/octopus/Makefile.inc A src/mainboard/google/octopus/bootmode.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/parrot/Makefile.inc A src/mainboard/google/parrot/bootmode.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/Makefile.inc A src/mainboard/google/peach_pit/bootmode.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/Makefile.inc A src/mainboard/google/poppy/bootmode.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/rambi/Makefile.inc A src/mainboard/google/rambi/bootmode.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/Makefile.inc A src/mainboard/google/reef/bootmode.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/slippy/Makefile.inc A src/mainboard/google/slippy/bootmode.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/Makefile.inc A src/mainboard/google/smaug/bootmode.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/Makefile.inc A src/mainboard/google/storm/bootmode.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/stout/Makefile.inc A src/mainboard/google/stout/bootmode.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/trogdor/Makefile.inc A src/mainboard/google/trogdor/bootmode.c M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/veyron/Makefile.inc A src/mainboard/google/veyron/bootmode.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/Makefile.inc M src/mainboard/google/veyron_mickey/board.h A src/mainboard/google/veyron_mickey/bootmode.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/Makefile.inc A src/mainboard/google/veyron_rialto/bootmode.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/volteer/Makefile.inc A src/mainboard/google/volteer/bootmode.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/zork/Makefile.inc A src/mainboard/google/zork/bootmode.c M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/bootmode.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/baskingridge/Makefile.inc A src/mainboard/intel/baskingridge/bootmode.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/coffeelake_rvp/Makefile.inc A src/mainboard/intel/coffeelake_rvp/bootmode.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/emeraldlake2/Makefile.inc A src/mainboard/intel/emeraldlake2/bootmode.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/glkrvp/Makefile.inc A src/mainboard/intel/glkrvp/bootmode.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/icelake_rvp/Makefile.inc A src/mainboard/intel/icelake_rvp/bootmode.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/bootmode.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/kblrvp/Makefile.inc A src/mainboard/intel/kblrvp/bootmode.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/Makefile.inc A src/mainboard/intel/kunimitsu/bootmode.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/Makefile.inc A src/mainboard/intel/shadowmountain/bootmode.c M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/strago/Makefile.inc A src/mainboard/intel/strago/bootmode.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/bootmode.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/wtm2/Makefile.inc A src/mainboard/intel/wtm2/bootmode.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/Makefile.inc A src/mainboard/samsung/lumpy/bootmode.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/Makefile.inc A src/mainboard/samsung/stumpy/bootmode.c M src/mainboard/samsung/stumpy/chromeos.c 165 files changed, 1,359 insertions(+), 1,125 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59011/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Spell Intel Cooper Lake-SP with a space
by Paul Menzel (Code Review) 09 Nov '21

09 Nov '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59036 ) Change subject: Spell Intel Cooper Lake-SP with a space ...................................................................... Spell Intel Cooper Lake-SP with a space Use the official spelling. [1] [1]: https://ark.intel.com/content/www/us/en/ark/products/codename/189143/produc… Change-Id: I7dbd332600caa7c04fc4f6bac53880e832e97bda Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Documentation/releases/coreboot-4.14-relnotes.md M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/chip.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/59036/1 diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index 40589a1..4f2b00e 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -142,7 +142,7 @@ coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory. This release has support for SkyLake-SP (SKX-SP) which is the 2nd -generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation +generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation or the latest generation [2] on market. With this release, the codebase for multiple generations of Xeon-SP diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index fa8403a..965d5da 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -20,7 +20,7 @@ select PLATFORM_USES_FSP2_2 select CACHE_MRC_SETTINGS help - Intel Cooperlake-SP support + Intel Cooper Lake-SP support if XEON_SP_COMMON_BASE diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 19bf2af..a4da344 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -186,7 +186,7 @@ } struct chip_operations soc_intel_xeon_sp_cpx_ops = { - CHIP_NAME("Intel Cooperlake-SP") + CHIP_NAME("Intel Cooper Lake-SP") .enable_dev = chip_enable_dev, .init = chip_init, .final = chip_final, -- To view, visit https://review.coreboot.org/c/coreboot/+/59036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dbd332600caa7c04fc4f6bac53880e832e97bda Gerrit-Change-Number: 59036 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Define ACPI Power Resources for FPMCU
by Karthik Ramasubramanian (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Raul Rangel, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58705 ) Change subject: mb/google/guybrush: Define ACPI Power Resources for FPMCU ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58705/comment/8eef6bad_23a622b2 PS4, Line 18: TEST > Only other test I think we need is to update the FPMCU FW. […] _OFF method is not called. The FPMCU is enabled(EN_PWR_FP is 1) and is not in reset (SOC_FP_RST_L is 1) after the flash_fp_mcu script is run. The script instructs the use to reboot the device after updating the FP firmware. After rebooting, FP is functional. -- To view, visit https://review.coreboot.org/c/coreboot/+/58705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f Gerrit-Change-Number: 58705 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-CC: Craig Hesling <hesling(a)chromium.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Nov 2021 06:40:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/smp/spinlock: Fix threading when !STAGE_HAS_SPINLOCKS
by Kyösti Mälkki (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Raul Rangel, Julius Werner, Rob Barnes, Karthik Ramasubramanian. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59021 ) Change subject: arch/x86/smp/spinlock: Fix threading when !STAGE_HAS_SPINLOCKS ...................................................................... Patch Set 2: (2 comments) File src/arch/x86/include/arch/smp/spinlock.h: https://review.coreboot.org/c/coreboot/+/59021/comment/6ac8980e_73b853c3 PS2, Line 21: static spinlock_t x = SPIN_LOCK_UNLOCKED; STAGE_HAS_DATA_SECTION could be used as guard, .data is needed. AFAICs CAR does not work for spinlock variables always. At least old AMD fam14 would fail such spinlock even if it did get .data for romstage. CB:30830 CB:37074 -- do not put CMOS access on parallel execution paths CB:34929 -- console printk locks removed from ENV_ROMSTAGE_OR_BEFORE https://review.coreboot.org/c/coreboot/+/59021/comment/80215659_b5b1b214 PS2, Line 50: thread_coop_disable(); For a sequence like below, thread_coop_disable() is not desired? I think our spin_lock() does more than it traditionally means. spin_lock() outb(0x70, index) outb(0x71, data) spin_unlock() Should we have these separately: spin_lock_disable_coop() spin_unlock_enable_coop() -- To view, visit https://review.coreboot.org/c/coreboot/+/59021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea621fcdad8f0367acce4f70be42a4e9a68da938 Gerrit-Change-Number: 59021 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 06:33:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/trogdor: Modify BOE panel_id for mrbland
by zanxi chen (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Julius Werner. zanxi chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58995 ) Change subject: mb/google/trogdor: Modify BOE panel_id for mrbland ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Hi Julius, Please help review this CL, since this code is very critical to the schedule of the project, please help to check. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/58995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65fecd854c4e3443edc07a44a1d43572d5030e4c Gerrit-Change-Number: 58995 Gerrit-PatchSet: 4 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Nov 2021 06:01:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
by Yu-Ping Wu (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Andrey Petrov, Patrick Rudolph, Felix Held. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58253 ) Change subject: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Gerrit-Change-Number: 58253 Gerrit-PatchSet: 5 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Nov 2021 05:55:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: treewide: Remove unused spinlock functions
by Kyösti Mälkki (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Nico Huber, Marshall Dawson, Julius Werner, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59020 ) Change subject: treewide: Remove unused spinlock functions ...................................................................... Patch Set 2: (4 comments) File src/arch/x86/include/arch/smp/spinlock.h: https://review.coreboot.org/c/coreboot/+/59020/comment/5928aef0_3caab82b PS2, Line 31: #define barrier() __asm__ __volatile__("" : : : "memory") static void phys_memory_barrier(void) in lib/ramtest.c static inline void barrier(void) in pineview/raminit.c So this should probably stay and get cleaned up a bit. CB:43810 was related File src/include/smp/spinlock.h: https://review.coreboot.org/c/coreboot/+/59020/comment/b1689fd3_65f68b3a PS2, Line 5: #include <arch/smp/spinlock.h> IMHO this file must provide valid spinlocks due the SMP guard. File src/soc/amd/common/psp_verstage/include/arch/smp/spinlock.h: https://review.coreboot.org/c/coreboot/+/59020/comment/786aad33_af8508ea PS2, Line 8: #define spin_unlock(lock) do {} while (0) We enter this file undef CONFIG(SMP) so these are not really acceptable. The trouble is CONFIG(SMP) and CONFIG_MAX_CPUS evaluate incorrectly for psp_verstage. CB:47650 and CB:43310 were related with criticism on fast-tracking this in in the shape you see it today. https://review.coreboot.org/c/coreboot/+/59020/comment/5f58c7d2_a5a3ca7f PS2, Line 11: #define boot_cpu() 1 Why does spinlock.h have #include <smp/node.h> at the end? Does the sequence below make sense? int boot_cpu(void); #define boot_cpu() 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e9a742e6b311d972a260039401bfd8f8766dd36 Gerrit-Change-Number: 59020 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Nov 2021 05:55:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021