coreboot-gerrit November 2021

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Change in coreboot[master]: amdfwtool: Put soc name setting to fw.cfg from command line
by Bao Zheng (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58552 to look at the new patch set (#10). Change subject: amdfwtool: Put soc name setting to fw.cfg from command line ...................................................................... amdfwtool: Put soc name setting to fw.cfg from command line Add a function to get parameter (currently only soc name) from config file. The function "process_config" also need to call this function for future COMBO feature. "process_config" will move downward to a loop body. process_config_get_parameter will keep where it is. Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/fw.cfg M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/fw.cfg M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/fw_cz.cfg M src/soc/amd/stoneyridge/fw_st.cfg M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 11 files changed, 63 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/58552/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/58552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52 Gerrit-Change-Number: 58552 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Fill PSP directory to ROMSIG based on the SOC ID
by Bao Zheng (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55454 to look at the new patch set (#15). Change subject: amdfwtool: Fill PSP directory to ROMSIG based on the SOC ID ...................................................................... amdfwtool: Fill PSP directory to ROMSIG based on the SOC ID New families used to use flag combo to decide whether use 0x14 or 0x10. It was not right. 0x14 is "pointer directly to PSP Directory table start from Family 17h Models 00h-0Fh, or point to PSP combo Directory header." For the old Family, the PSP Directory is at 0x10. Being combo or not is not the flag to decide where is psp_entry. Change-Id: I82efc3498bc831a45662a8628cc24fcdd502ec93 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M util/amdfwtool/amdfwtool.c 4 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/55454/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/55454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82efc3498bc831a45662a8628cc24fcdd502ec93 Gerrit-Change-Number: 55454 Gerrit-PatchSet: 15 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Set soc name for Stoneyridge
by Bao Zheng (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58555 to look at the new patch set (#9). Change subject: amdfwtool: Set soc name for Stoneyridge ...................................................................... amdfwtool: Set soc name for Stoneyridge For the stoneyridge, soc_name is not set in Makefile, so set_efs_table is not called. Keep it unchanged. Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/58555/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/58555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Gerrit-Change-Number: 58555 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: pci_mmio_cfg: Always use pci_s_* functions
by Nico Huber (Code Review) 09 Nov '21

09 Nov '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58333 ) Change subject: pci_mmio_cfg: Always use pci_s_* functions ...................................................................... pci_mmio_cfg: Always use pci_s_* functions When MMIO functions are available, the pci_s_* functions do exactly the same thing. Drop the redundant pci_mmio_* versions. Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/device/pci_mmio_cfg.h M src/mainboard/intel/cedarisland_crb/bootblock.c M src/mainboard/ocp/tiogapass/bootblock.c M src/soc/intel/xeon_sp/bootblock.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/soc_util.c 7 files changed, 30 insertions(+), 65 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Shelley Chen: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 557adcb..81faa9c 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -47,38 +47,44 @@ #endif +/* + * Avoid name collisions as different stages have different signature + * for these functions. The _s_ stands for simple, fundamental IO or + * MMIO variant. + */ + static __always_inline -uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) +uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg) { return pcicfg(dev)->reg8[reg]; } static __always_inline -uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg) +uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg) { return pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline -uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg) +uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg) { return pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; } static __always_inline -void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) +void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) { pcicfg(dev)->reg8[reg] = value; } static __always_inline -void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) +void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) { pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value; } static __always_inline -void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) +void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) { pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value; } @@ -107,45 +113,4 @@ return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; } -/* Avoid name collisions as different stages have different signature - * for these functions. The _s_ stands for simple, fundamental IO or - * MMIO variant. - */ - -static __always_inline -uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg) -{ - return pci_mmio_read_config8(dev, reg); -} - -static __always_inline -uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg) -{ - return pci_mmio_read_config16(dev, reg); -} - -static __always_inline -uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg) -{ - return pci_mmio_read_config32(dev, reg); -} - -static __always_inline -void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) -{ - pci_mmio_write_config8(dev, reg, value); -} - -static __always_inline -void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) -{ - pci_mmio_write_config16(dev, reg, value); -} - -static __always_inline -void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) -{ - pci_mmio_write_config32(dev, reg, value); -} - #endif /* _PCI_MMIO_CFG_H */ diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c index e51752b..ae8212a 100644 --- a/src/mainboard/intel/cedarisland_crb/bootblock.c +++ b/src/mainboard/intel/cedarisland_crb/bootblock.c @@ -21,7 +21,7 @@ pcr_write32(PID_DMI, 0x2774, 1); /* Decode for SuperIO (0x2e) and COM1 (0x3f8) */ - pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); + pci_s_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index b5c2aa1..6bcbfcc 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -30,7 +30,7 @@ pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ - pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + pci_s_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4)); } diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 1d706fe..5ea09ac 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -56,9 +56,9 @@ pch_enable_lpc(); /* Set up P2SB BAR. This is needed for PCR to work */ - uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND); - pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); - pci_mmio_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); + uint8_t p2sb_cmd = pci_s_read_config8(PCH_DEV_P2SB, PCI_COMMAND); + pci_s_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); + pci_s_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); } void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 0c1c5ab..9443966 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -160,7 +160,7 @@ const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device; const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function; - const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + const uint32_t id = pci_s_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); if (id == 0xffffffff) return 0; diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 01e86e1..4b46ec8 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -13,13 +13,13 @@ printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \ fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ ((uint32_t)dev >> 12) & 0x07, \ - #reg, reg, pci_mmio_read_config32(dev, reg)) + #reg, reg, pci_s_read_config32(dev, reg)) #define dump_csr64(fmt, dev, reg) \ printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \ fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ ((uint32_t)dev >> 12) & 0x07, #reg, reg, \ - pci_mmio_read_config32(dev, reg+4), pci_mmio_read_config32(dev, reg)) + pci_s_read_config32(dev, reg+4), pci_s_read_config32(dev, reg)) #define SAD_ALL_DEV 29 #define SAD_ALL_FUNC 0 diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index b903249..cc8db64 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -79,11 +79,11 @@ /* configure PCU_CR0_FUN csrs */ pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); - data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); + data = pci_s_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); data |= P_STATE_LIMITS_LOCK; - pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); + pci_s_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); - plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); + plat_info = pci_s_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); max_min_turbo_limit_ratio = (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> @@ -94,29 +94,29 @@ /* configure PCU_CR1_FUN csrs */ pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL); + data = pci_s_read_config32(cr1_dev, PCU_CR1_SAPMCTL); /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ data &= 0x0fffffff; data |= SAPMCTL_LOCK_MASK; - pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); + pci_s_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); /* configure PCU_CR1_FUN csrs */ pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); data = PCIE_IN_PKGCSTATE_L1_MASK; - pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); + pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); data = KTI_IN_PKGCSTATE_L1_MASK; - pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); + pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); data = PROCHOT_RATIO; printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); - pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); + pci_s_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); - data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); + data = pci_s_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; - pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); + pci_s_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); } } 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Gerrit-Change-Number: 58333 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: pci_mmio_cfg: Gather everything MMCONF (ECAM) related
by Nico Huber (Code Review) 09 Nov '21

09 Nov '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58332 ) Change subject: pci_mmio_cfg: Gather everything MMCONF (ECAM) related ...................................................................... pci_mmio_cfg: Gather everything MMCONF (ECAM) related To ease code sharing with other MMIO-based configuration mechanisms, move everything MMCONF (more specifically ECAM) related to one spot and guard it. Change-Id: Idda2320c331499dabbee7447f1ad3e81340f2a25 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58332 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/device/pci_mmio_cfg.h 1 file changed, 16 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Shelley Chen: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index e873abc..557adcb 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -7,10 +7,6 @@ #include <device/mmio.h> #include <device/pci_type.h> -/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we - * prevent some sub-optimal constant folding. */ -extern u8 *const pci_mmconf; - /* Using a unique datatype for MMIO writes makes the pointers to _not_ * qualify for pointer aliasing with any other objects in memory. * @@ -29,12 +25,28 @@ uint32_t reg32[4096 / sizeof(uint32_t)]; }; +#if CONFIG(MMCONF_SUPPORT) + +#if CONFIG_MMCONF_BASE_ADDRESS == 0 +#error "CONFIG_MMCONF_BASE_ADDRESS undefined!" +#endif + +#if CONFIG_MMCONF_BUS_NUMBER * MiB != CONFIG_MMCONF_LENGTH +#error "CONFIG_MMCONF_LENGTH does not correspond with CONFIG_MMCONF_BUS_NUMBER!" +#endif + +/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we + prevent some sub-optimal constant folding. */ +extern u8 *const pci_mmconf; + static __always_inline volatile union pci_bank *pcicfg(pci_devfn_t dev) { return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)]; } +#endif + static __always_inline uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) { @@ -95,18 +107,6 @@ return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; } -#if CONFIG(MMCONF_SUPPORT) - -#if CONFIG_MMCONF_BASE_ADDRESS == 0 -#error "CONFIG_MMCONF_BASE_ADDRESS undefined!" -#endif - -#if CONFIG_MMCONF_BUS_NUMBER * MiB != CONFIG_MMCONF_LENGTH -#error "CONFIG_MMCONF_LENGTH does not correspond with CONFIG_MMCONF_BUS_NUMBER!" -#endif - -#endif - /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or * MMIO variant. -- To view, visit https://review.coreboot.org/c/coreboot/+/58332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idda2320c331499dabbee7447f1ad3e81340f2a25 Gerrit-Change-Number: 58332 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: pci_mmio_cfg: Move guard around pci_s_* functions to x86
by Nico Huber (Code Review) 09 Nov '21

09 Nov '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58331 ) Change subject: pci_mmio_cfg: Move guard around pci_s_* functions to x86 ...................................................................... pci_mmio_cfg: Move guard around pci_s_* functions to x86 There is no platform in our tree that requires the PCI MMIO ops but doesn't want the pci_s_* definitions. The only case where we include the `pci_mmio_cfg.h` header but don't want the pci_s_* functions to use MMIO is on older x86 platforms, so move the guard there. Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58331 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/pci_ops.h M src/include/device/pci_mmio_cfg.h 2 files changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Shelley Chen: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 317e597..abbd35c 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -4,6 +4,8 @@ #define ARCH_I386_PCI_OPS_H #include <arch/pci_io_cfg.h> +#if CONFIG(MMCONF_SUPPORT) #include <device/pci_mmio_cfg.h> +#endif #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 8798405..e873abc 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -105,6 +105,8 @@ #error "CONFIG_MMCONF_LENGTH does not correspond with CONFIG_MMCONF_BUS_NUMBER!" #endif +#endif + /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or * MMIO variant. @@ -146,6 +148,4 @@ pci_mmio_write_config32(dev, reg, value); } -#endif - #endif /* _PCI_MMIO_CFG_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af Gerrit-Change-Number: 58331 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: pci_mmio_cfg: Always use pci_s_* functions
by Nico Huber (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Furquan Shaikh, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Morgan Jang, Patrick Rudolph, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58333 ) Change subject: pci_mmio_cfg: Always use pci_s_* functions ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58333/comment/46986c85_ed0f7f76 PS5, Line 10: the same > nit: `the same thing` ? Still learning the language I guess ;) is it uncommon or even completely wrong to leave it out? -- To view, visit https://review.coreboot.org/c/coreboot/+/58333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Gerrit-Change-Number: 58333 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 11:04:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: pci_mmio_cfg: Always use pci_s_* functions
by Nico Huber (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Nico Huber, Anjaneya "Reddy" Chagam, Furquan Shaikh, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Morgan Jang, Patrick Rudolph, Tim Chu. Hello Shelley Chen, build bot (Jenkins), Furquan Shaikh, Jonathan Zhang, Angel Pons, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Christian Walter, Morgan Jang, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58333 to look at the new patch set (#6). Change subject: pci_mmio_cfg: Always use pci_s_* functions ...................................................................... pci_mmio_cfg: Always use pci_s_* functions When MMIO functions are available, the pci_s_* functions do exactly the same thing. Drop the redundant pci_mmio_* versions. Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/include/device/pci_mmio_cfg.h M src/mainboard/intel/cedarisland_crb/bootblock.c M src/mainboard/ocp/tiogapass/bootblock.c M src/soc/intel/xeon_sp/bootblock.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/soc_util.c 7 files changed, 30 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/58333/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Gerrit-Change-Number: 58333 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Felix Held. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 52: (1 comment) Patchset: PS46: > Lean, yes, I got that, but I was talking about having a separate change to fix non-booting devices f […] Sure understood. I will upload a separate patch to disable PSE first before this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 52 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Nov 2021 10:10:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by flora.fu＠mediatek.com (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, flora.fu(a)mediatek.com. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58969 to look at the new patch set (#7). Change subject: soc/mediatek/mt8195: Add APU device apc driver ...................................................................... soc/mediatek/mt8195: Add APU device apc driver Add APU device apc driver and set up permissions. APU has its own device apc for control access by domains. For Domain 0, the access to the following slave are restricted to security read and write: apusys_ao-2, apusys_ao-4, apusys_ao-5, apu_sctrl_reviser, apu_iommu0_r1 apu_iommu0_r2, apu_iommu0_r3, apu_iommu0_r4 apu_iommu1_r1, apu_iommu1_r2, apu_iommu1_r3,apu_iommu1_r4 For VPU, D0/D5 are set as no protection, other domains are forbidden. For other slaves, the D0 is no protection, others domains are forbidden. BUG=b:203145462 BRANCH=cherry TEST=boot cherry, check dump log and test permissions Signed-off-by: Flora Fu <flora.fu(a)mediatek.com> Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc.h 5 files changed, 357 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58969/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Gerrit-Change-Number: 58969 Gerrit-PatchSet: 7 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021