Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59029 )
Change subject: sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA
......................................................................
sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA
This change adds about 30 KiB to FSP-M. When not using the SPI DMA
controller, this change actually has a ~7 second boot time penalty. When
we use the DMA engine, we end up with about a 5 second decrease. Once we
switch to 100 MHz SPI this will help even more since we have effectively
eliminated the decompression time.
BUG=b:179699789
TEST=Boot nipperkin to OS and take boot time measurements
fspm.bin 0x2efc0 fsp 90953 LZMA (233472 decompressed)
fspm.bin 0x2cfc0 fsp 121156 LZ4 (233472 decompressed)
- FSP-M / no async -
| 508 - finished loading body | 177.019 | 179.384 Δ( 2.36, 0.16%) |
...
| 970 - loading FSP-M | 0.346 | 0.346 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.01 Δ( 0.00, 0.00%) |
| 18 - finished LZ4 decompress (ignore for x86) | 53.916 | 59.475 Δ( 5.56, 0.37%) |
- FSP-M / async -
| 508 - finished loading body | 177.185 | 179.689 Δ( 2.50, 0.18%) |
...
| 970 - loading FSP-M | 0.989 | 0.99 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 9.483 | 12.877 Δ( 3.39, 0.24%) |
| 18 - finished LZ4 decompress (ignore for x86) | 10.833 | 0.312 Δ(-10.52, -0.75%) |
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59029/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index fc0173a..92f7e9d 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -20,7 +20,8 @@
select DRIVERS_USB_ACPI
select DRIVERS_I2C_DESIGNWARE
select DRIVERS_USB_PCI_XHCI
- select FSP_COMPRESS_FSP_M_LZMA
+ select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING
+ select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING
select FSP_COMPRESS_FSP_S_LZ4
select GENERIC_GPIO_LIB
select HAVE_ACPI_TABLES
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Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held.
Hello Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59025
to look at the new patch set (#2).
Change subject: soc/amd/cezanne: Preload FSP-S
......................................................................
soc/amd/cezanne: Preload FSP-S
FSP-S is normally memmapped and then decompressed. There are about 7 ms
between starting ramstage, and loading FSP-S. By preloading we can
ensure the fsps.bin is already in RAM by the time we need it. This
reduces boot time by about 7 ms.
BUG=b:
TEST=Boot nipperkin and see ~7ms reduction in boot time
| 10 - start of ramstage | 0.044 | 0.044 Δ( 0.00, 0.00%) |
| 30 - device enumeration | 1.899 | 2.073 Δ( 0.17, 0.01%) |
| 971 - loading FSP-S | 6.645 | 6.628 Δ( -0.02, -0.00%) |
| 15 - starting LZMA decompress (ignore for x86) | 0.016 | 0.01 Δ( -0.01, -0.00%) |
| 16 - finished LZMA decompress (ignore for x86) | 15.266 | 8.316 Δ( -6.95, -0.47%) |
| 954 - calling FspSiliconInit | 0.08 | 0.09 Δ( 0.01, 0.00%) |
CBFS DEBUG: _cbfs_alloc(name='fsps.bin', alloc=0xc9761e5c(0xc97a3f0c), force_ro=false, type=-1)
CBFS: Found 'fsps.bin' @0x1a1fc0 size 0x102cd in mcache @0xc97dd208
waiting for thread
took 1 us <-- fsps.bin was preloaded
CBFS DEBUG: get_preload_rdev(name='fsps.bin') preload successful
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95
---
M src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/preload.c
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/59025/2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58333 )
Change subject: pci_mmio_cfg: Always use pci_s_* functions
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58333/comment/e7ee527f_ffbe2497
PS5, Line 10: the same
nit: `the same thing` ?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )
Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 52:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55367/comment/eaffbd12_4ce249d6
PS52, Line 23: it's
its
https://review.coreboot.org/c/coreboot/+/55367/comment/c5fad13e_d33d63e9
PS52, Line 27: locate
locates the
https://review.coreboot.org/c/coreboot/+/55367/comment/68c6dfc2_b89de67a
PS52, Line 30: enables
enable
https://review.coreboot.org/c/coreboot/+/55367/comment/53dd3958_194341ee
PS52, Line 32: These assignments
Exactly one space please.
https://review.coreboot.org/c/coreboot/+/55367/comment/6e1cc1a6_b0e044f6
PS52, Line 9: The Intel® Programmable Services Engine (Intel® PSE) is a
: dedicated offload engine for IoT functions powered by an ARM
: Cortex-M7 microcontroller. It provides independent, low-DMIPS
: computing and low-speed I/Os for IoT applications, plus
: dedicated services for real-time computing and time-sensitive
: synchronization.
:
: The PSE hosts new functions, including remote out-of-band
: device management, network proxy, embedded controller lite
: and sensor hub.
:
: This CL enables the user to provide the base address of the
: PSE FW blob which will then be loaded by the FSP-S onto the
: ARM controller. PSE FW will do the initialization work of
: PSE controller and it's peripherals. The loading of PSE FW
: should have negligible impact on boot time unless PSE
: controller could not locate PSE FW and FSP will attempt to
: redo PSE FW loading and wait for PSE handshake until it times
: out. Once PSE controller locate PSE FW, it will do initialization
: concurrently by itself with coreboot booting.
:
: It also adds PSE related FSP-S UPD settings which enables the
: setup of peripheral ownership (assigned to the PSE or x86
: subsystem) and interrupts. These assignments need to take
: place at a given point in the boot process and cannot be
: changed later.
:
: To verify if PSE FW is loaded properly, the user could enable
: PchPseShellEnabled flag and the log will be printed at PSE UART 2.
:
: For further info please refer to doc #611825 (for HW overview)
: and #614110 (for PSE EDS).
Please reflow for 75 characters per line.
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