coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/guybrush/dewatt: update dewatt config
by Chris Wang (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Rob Barnes, Karthik Ramasubramanian. Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59092 ) Change subject: mb/google/guybrush/dewatt: update dewatt config ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Is there going to be followup CL to change the values? yes. the settings come from guybrush as default and will update once the SDLE and STT values are confirmed. -- To view, visit https://review.coreboot.org/c/coreboot/+/59092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993 Gerrit-Change-Number: 59092 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 14:51:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Call the set_efs_table for Stoneyridge
by Bao Zheng (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58871 ) Change subject: amdfwtool: Call the set_efs_table for Stoneyridge ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: I have not tested on Stoeyridge. But I assume it doesn't break the board. Many change depend on this. Please review it. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/58871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Gerrit-Change-Number: 58871 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 14:29:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Use command line option use-combo to decide if use combo
by Bao Zheng (Code Review) 10 Nov '21

10 Nov '21

Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55455 ) Change subject: amdfwtool: Use command line option use-combo to decide if use combo ...................................................................... Patch Set 20: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/55455/comment/1c757d77_3858daab PS20, Line 1567: if (comboable) : amd_romsig->new_psp_directory = BUFF_TO_RUN(ctx, pspdir); : else : amd_romsig->psp_directory = BUFF_TO_RUN(ctx, pspdir); : : if (cb_config.use_combo) { : psp_combo_directory *combo_dir = new_combo_dir(&ctx); : amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, combo_dir); : /* 0 -Compare PSP ID, 1 -Compare chip family ID */ : combo_dir->entries[0].id_sel = 0; : combo_dir->entries[0].id = get_psp_id(cb_config.soc_id); : combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir); : : combo_dir->header.lookup = 1; : fill_dir_header(combo_dir, 1, PSP2_COOKIE, &ctx); : } create a new function to set psp_directory. And bios table below. -- To view, visit https://review.coreboot.org/c/coreboot/+/55455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Gerrit-Change-Number: 55455 Gerrit-PatchSet: 20 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 14:23:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/dewatt: update dewatt config
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Chris Wang, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59092 ) Change subject: mb/google/guybrush/dewatt: update dewatt config ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Is there going to be followup CL to change the values? -- To view, visit https://review.coreboot.org/c/coreboot/+/59092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993 Gerrit-Change-Number: 59092 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 14:03:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Disable active policy under dptf
by Mark Hsieh (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Felix Held, Zhuohao Lee. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59102 ) Change subject: mb/google/brya/var/gimble: Disable active policy under dptf ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9899bf49dfaa63ee96532b5b90464d83e02daeee Gerrit-Change-Number: 59102 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 14:02:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Disable active policy under dptf
by Mark Hsieh (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Felix Held, Zhuohao Lee. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59102 ) Change subject: mb/google/brya/var/gimble: Disable active policy under dptf ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/59102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9899bf49dfaa63ee96532b5b90464d83e02daeee Gerrit-Change-Number: 59102 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 14:02:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/google,intel: Split chromeos.c files
by Kyösti Mälkki (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Nick Vaccaro, Kyösti Mälkki, Karthik Ramasubramanian. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59018 to look at the new patch set (#7). Change subject: [WIP] mb/google,intel: Split chromeos.c files ...................................................................... [WIP] mb/google,intel: Split chromeos.c files Move all the low-level GPIO support in bootmode.c files and build them for all stages. Keep ChromeOS related ACPI and lbtable support in chromeos.c files and build them only for ramstage. Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc A src/mainboard/google/brya/variants/baseboard/brask/chromeos.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc A src/mainboard/google/brya/variants/baseboard/brya/chromeos.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/dedede/variants/baseboard/Makefile.inc A src/mainboard/google/dedede/variants/baseboard/chromeos.c M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/fizz/variants/baseboard/Makefile.inc A src/mainboard/google/fizz/variants/baseboard/chromeos.c M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/guybrush/Makefile.inc M src/mainboard/google/hatch/variants/baseboard/Makefile.inc A src/mainboard/google/hatch/variants/baseboard/chromeos.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/herobrine/Makefile.inc M src/mainboard/google/herobrine/chromeos.c M src/mainboard/google/octopus/variants/baseboard/Makefile.inc A src/mainboard/google/octopus/variants/baseboard/chromeos.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/Makefile.inc A src/mainboard/google/poppy/variants/baseboard/chromeos.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/baseboard/Makefile.inc A src/mainboard/google/reef/variants/baseboard/chromeos.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/coral/Makefile.inc A src/mainboard/google/reef/variants/coral/chromeos.c M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/google/volteer/variants/baseboard/Makefile.inc A src/mainboard/google/volteer/variants/baseboard/chromeos.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/adlrvp/gpio_m.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/Makefile.inc A src/mainboard/intel/coffeelake_rvp/variants/baseboard/chromeos.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc A src/mainboard/intel/glkrvp/variants/baseboard/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc A src/mainboard/intel/icelake_rvp/variants/icl_u/chromeos.c M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc A src/mainboard/intel/icelake_rvp/variants/icl_y/chromeos.c M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c M src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc A src/mainboard/intel/shadowmountain/variants/baseboard/chromeos.c M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/chromeos.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up4/chromeos.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c M src/vendorcode/google/chromeos/chromeos.h 60 files changed, 261 insertions(+), 168 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59018/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/59018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7 Gerrit-Change-Number: 59018 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Angel Pons (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Sean Rhodes, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 ) Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... Patch Set 19: (29 comments) File src/ec/starlabs/merlin/acpi/battery.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/d9c33e0b_6d5a4dea PS19, Line 41: 0x0a 10 https://review.coreboot.org/c/coreboot/+/58343/comment/28a32d02_6e2bd84e PS19, Line 42: 0x64 100 https://review.coreboot.org/c/coreboot/+/58343/comment/ad601849_4ebf9ac3 PS19, Line 43: 0x64 100 File src/ec/starlabs/merlin/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/767f8750_41e75582 PS19, Line 56: \LIDS = 0x03 This seems weird https://review.coreboot.org/c/coreboot/+/58343/comment/57552d3f_1e16f81a PS19, Line 67: Embedded nit: `Embedded Controller`? https://review.coreboot.org/c/coreboot/+/58343/comment/536ca3d2_d21fae7f PS19, Line 101: Local1 Local1 is not always initialized https://review.coreboot.org/c/coreboot/+/58343/comment/5a2d005b_73e50010 PS19, Line 104: // ECWT (Embedded Write Method) What exactly does this method do? Is it used anywhere? https://review.coreboot.org/c/coreboot/+/58343/comment/d742ffea_0df58e1f PS19, Line 135: Embedded nit: `Embedded Controller`? https://review.coreboot.org/c/coreboot/+/58343/comment/060dcc71_377cc10d PS19, Line 170: Method (ECMD, 0, Serialized) : { : Return (0x00) : } : : Method (ECM1, 0, Serialized) : { : Return (0x00) : } : : Method (ECNT, 0, Serialized) : { : Return (0x00) : } Are these methods needed? File src/ec/starlabs/merlin/acpi/hid.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/ab866d13_4504c125 PS19, Line 109: 0xFA 250 https://review.coreboot.org/c/coreboot/+/58343/comment/2bf6337c_e93b68c3 PS19, Line 111: 0x04 4 https://review.coreboot.org/c/coreboot/+/58343/comment/5ca0e78d_c9794dc9 PS19, Line 244: Its It's https://review.coreboot.org/c/coreboot/+/58343/comment/40b4458a_7a076e0b PS19, Line 248: Its It's https://review.coreboot.org/c/coreboot/+/58343/comment/7ee4c6d2_4f2769b5 PS19, Line 255: Its It's File src/ec/starlabs/merlin/acpi/keyboard.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/bec4164d_b2418840 PS19, Line 23: _Q80 Copy-paste error File src/ec/starlabs/merlin/acpi/thermal.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/65036123_a1f98f75 PS19, Line 5: Notify (\_TZ.TZ01, 0x80 Syntax error. Looks like the file is unused, I'd remove it. File src/ec/starlabs/merlin/acpi/typec.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/8a6b0415_a593bc93 PS19, Line 5: 0x32 50 https://review.coreboot.org/c/coreboot/+/58343/comment/e6ab44d7_ee181678 PS19, Line 35: 0x32 50 https://review.coreboot.org/c/coreboot/+/58343/comment/c64af2fe_10d60683 PS19, Line 60: 0x32 50 File src/ec/starlabs/merlin/acpi/ubtc.asl: PS19: Is this generated via acpigen? File src/ec/starlabs/merlin/ec.h: https://review.coreboot.org/c/coreboot/+/58343/comment/0f2cfb72_59d267f9 PS19, Line 41: /* Keyboard Backlight Timeout */ : #define SEC_30 0x00 : #define MIN_1 0x01 : #define MIN_3 0x02 : #define MIN_5 0x03 : #define NEVER 0x04 : : /* Fn Ctrl Swap */ : #define FN_CTRL 0x00 : #define CTRL_FN 0x01 : : /* Max Charge Setting */ : #define CHARGE_100 0x00 : #define CHARGE_80 0xbb : #define CHARGE_60 0xaa : : /* Fan Mode Setting */ : #define FAN_NORMAL 0x00 : #define FAN_AGGRESSIVE 0xbb : #define FAN_QUIET 0xaa : : /* Fn Lock State */ : #define UNLOCKED 0x00 : #define LOCKED 0x01 : : /* Trackpad State */ : #define TRACKPAD_ENABLED 0x00 : #define TRACKPAD_DISABLED 0x22 : : /* Keyboard Brightness Levels */ : #define KBL_ON 0xdd : #define KBL_OFF 0xcc : #define KBL_LOW 0xbb : #define KBL_HIGH 0xaa : : /* Keyboard Backlight State */ : #define KBL_DISABLED 0x00 : #define KBL_ENABLED 0xaa I'd use actual enums for these instead of macros. File src/ec/starlabs/merlin/ec.c: https://review.coreboot.org/c/coreboot/+/58343/comment/d2d4d40b_65ef1ebd PS19, Line 68: 0 I'd use a named value here https://review.coreboot.org/c/coreboot/+/58343/comment/2b1cd191_cf7ef9ae PS19, Line 81: default: nit: for completeness, I'd explicitly handle `SEC_30`: case SEC_30: default: ec_write(ECRAM_KBL_TIMEOUT, SEC_30); break; https://review.coreboot.org/c/coreboot/+/58343/comment/254653f5_aa5a9436 PS19, Line 59: /* : * Keyboard Backlight Timeout : * : * Setting: kbl_timeout : * : * Values: 30 Seconds, 1 Minute, 3 Minutes, 5 Minutes, Never : * Default: 30 Seconds : * : */ : switch (get_uint_option("kbl_timeout", 0)) { : case MIN_1: : ec_write(ECRAM_KBL_TIMEOUT, MIN_1); : break; : case MIN_3: : ec_write(ECRAM_KBL_TIMEOUT, MIN_3); : break; : case MIN_5: : ec_write(ECRAM_KBL_TIMEOUT, MIN_5); : break; : case NEVER: : ec_write(ECRAM_KBL_TIMEOUT, NEVER); : break; : default: : ec_write(ECRAM_KBL_TIMEOUT, SEC_30); : break; : } Idea: Encapsulate these into helper functions? https://review.coreboot.org/c/coreboot/+/58343/comment/6103c8d4_44b50934 PS19, Line 113: switch (get_uint_option("max_charge", 0)) { : case CHARGE_80: : ec_write(ECRAM_MAX_CHARGE, CHARGE_80); : break; : case CHARGE_60: : ec_write(ECRAM_MAX_CHARGE, CHARGE_60); : break; : default: : ec_write(ECRAM_MAX_CHARGE, CHARGE_100); : break; : } cmos.layout of CB:56088 won't work with this, the default case will always be taken. The case values need to match cmos.layout enumeration values. Same issue applies to the other options, although some happen to work because CMOS and EC use the same enumeration values. Another idea: The current cmos.layout uses 0-based sequential values for enumerations. The switch statement can be replaced with an array as look-up table, using the CMOS value as index to obtain the corresponding value to write to the EC. https://review.coreboot.org/c/coreboot/+/58343/comment/db1c3918_4e5a3c16 PS19, Line 134: #if CONFIG(EC_STARLABS_FAN) : switch (get_uint_option("fan_mode", 0)) { : case FAN_AGGRESSIVE: : ec_write(ECRAM_FAN_MODE, FAN_AGGRESSIVE); : break; : case FAN_QUIET: : ec_write(ECRAM_FAN_MODE, FAN_QUIET); : break; : default: : ec_write(ECRAM_FAN_MODE, FAN_NORMAL); : break; : } : #endif Why not use a regular C check? https://review.coreboot.org/c/coreboot/+/58343/comment/7bbedbab_59c34cea PS19, Line 193: #if CONFIG(EC_STARLABS_KBL_LEVELS) : switch (get_uint_option("kbl_brightness", 0)) { : case KBL_OFF: : ec_write(ECRAM_KBL_BRIGHTNESS, KBL_OFF); : break; : case KBL_HIGH: : ec_write(ECRAM_KBL_BRIGHTNESS, KBL_HIGH); : break; : default: : ec_write(ECRAM_KBL_BRIGHTNESS, KBL_LOW); : break; : } : #else : switch (get_uint_option("kbl_brightness", 0)) { : case KBL_OFF: : ec_write(ECRAM_KBL_BRIGHTNESS, KBL_OFF); : break; : default: : ec_write(ECRAM_KBL_BRIGHTNESS, KBL_ON); : break; : } : #endif Same as before https://review.coreboot.org/c/coreboot/+/58343/comment/4b5cbfdb_f318d90c PS19, Line 237: .read_resources = noop_read_resources, : .set_resources = noop_set_resources, : }; ITE ECs have a Super I/O part, and the LDNs' resources should be reported. See the code for other ITE ECs and Super I/Os on how to do it. https://review.coreboot.org/c/coreboot/+/58343/comment/28811687_0170e90a PS19, Line 251: ITE ITE One "ITE" is enough? -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 19 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 13:45:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/mipi_camera: Add support for _DSC field
by Varshit B Pandya (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58767 to look at the new patch set (#9). Change subject: driver/intel/mipi_camera: Add support for _DSC field ...................................................................... driver/intel/mipi_camera: Add support for _DSC field The _DSC (Device State for Configuration) object evaluates to an integer may be used to tell Linux the highest allowed D state for a device during probe. The support for _DSC requires support from the kernel bus type if the bus driver normally sets the device in D0 state for probe. The D states and thus also the allowed values for _DSC are listed below. Number State Description 0 D0 Device fully powered on 1 D1 2 D2 3 D3hot 4 D3cold Off More details can be found here https://lkml.org/lkml/2021/10/25/397 BUG=none BRANCH=none TEST=Add corresponding field in brya, boot and dump SSDT to check if _DSC field is as per expectation. Name (_ADR, Zero) // _ADR: Address Name (_HID, "OVTI8856") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_DSC, 0, NotSerialized) { Return (0x04) } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/58767/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/58767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Gerrit-Change-Number: 58767 Gerrit-PatchSet: 9 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable CPU PCIE RP 1
by Joey Peng (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Tim Wawrzynczak, YH Lin. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59080 ) Change subject: mb/google/brya/var/taeko: Enable CPU PCIE RP 1 ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/59080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 Gerrit-Change-Number: 59080 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 13:31:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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