coreboot-gerrit November 2021

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Change in coreboot[master]: device/azalia_device: Export `codecs_init()`
by Angel Pons (Code Review) 10 Nov '21

10 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59108 ) Change subject: device/azalia_device: Export `codecs_init()` ...................................................................... device/azalia_device: Export `codecs_init()` Make the `codecs_init()` function non-static so that it can be used in other places. Rename it to `azalia_codecs_init()` to avoid name clashes with static definitions in southbridge code (which will be removed in subsequent commits). Change-Id: I080a73102b0c4f9f8a283cd93bba9b3b23169be0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c M src/include/device/azalia_device.h 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59108/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index a223e76..c3bb91b 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -267,7 +267,7 @@ mainboard_azalia_program_runtime_verbs(base, reg32); } -static void codecs_init(struct device *dev, u8 *base, u16 codec_mask) +void azalia_codecs_init(struct device *dev, u8 *base, u16 codec_mask) { int i; @@ -297,7 +297,7 @@ if (codec_mask) { printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask); - codecs_init(dev, base, codec_mask); + azalia_codecs_init(dev, base, codec_mask); } } diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 18481fe..8f0d212 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -23,6 +23,7 @@ int azalia_exit_reset(u8 *base); u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb); int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size); +void azalia_codecs_init(struct device *dev, u8 *base, u16 codec_mask); void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; -- To view, visit https://review.coreboot.org/c/coreboot/+/59108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I080a73102b0c4f9f8a283cd93bba9b3b23169be0 Gerrit-Change-Number: 59108 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Remove unused typedef
by Angel Pons (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59107 ) Change subject: sb/intel/bd82x6x: Remove unused typedef ...................................................................... sb/intel/bd82x6x: Remove unused typedef Change-Id: If725a369e7a12fbddd7b108e557d34a13bc78c09 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/azalia.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59107/1 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 7bcba02..974a390 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -12,8 +12,6 @@ #include "chip.h" #include "pch.h" -typedef struct southbridge_intel_bd82x6x_config config_t; - static int codec_detect(u8 *base) { u8 reg8; -- To view, visit https://review.coreboot.org/c/coreboot/+/59107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If725a369e7a12fbddd7b108e557d34a13bc78c09 Gerrit-Change-Number: 59107 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Program PC BEEP verbs
by Angel Pons (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59106 ) Change subject: sb/intel/i82801gx: Program PC BEEP verbs ...................................................................... sb/intel/i82801gx: Program PC BEEP verbs For consistency with other Intel southbridges, program PC BEEP verbs. None of the boards in the tree using this southbridge provide PC BEEP verbs, so this change makes no difference. Change-Id: I94d24999af819cf3951510586fd4864d1ed3f2f1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801gx/azalia.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/59106/1 diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 1f12650..7d4745e 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -129,6 +129,8 @@ if (codec_mask & (1 << i)) codec_init(dev, base, i); } + + azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); } static void azalia_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/59106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94d24999af819cf3951510586fd4864d1ed3f2f1 Gerrit-Change-Number: 59106 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel: Use `azalia_program_verb_table()` function
by Angel Pons (Code Review) 10 Nov '21

10 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59105 ) Change subject: sb/intel: Use `azalia_program_verb_table()` function ...................................................................... sb/intel: Use `azalia_program_verb_table()` function Use the `azalia_program_verb_table()` function in preparation to deduplicate Azalia init code. With this change, the "Azalia: verb loaded." message is now printed when programming the verbs failed. This will be addressed once `codec_init()` has been deduplicated. Change-Id: I5d9e0f19429620166f2a6ef48ec7c963ee64b59c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c 5 files changed, 9 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59105/1 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 1e58dfd..7bcba02 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -90,7 +90,6 @@ u32 reg32; const u32 *verb; u32 verb_size; - int i; printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); @@ -120,15 +119,7 @@ printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, verb, verb_size); printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } @@ -140,15 +131,7 @@ codec_init(dev, base, i); } - for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, pc_beep_verbs[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); } static void azalia_init(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index cc5d345..1f12650 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -88,7 +88,6 @@ u32 reg32; const u32 *verb; u32 verb_size; - int i; printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); @@ -118,15 +117,7 @@ printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, verb, verb_size); printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index 2646cbc..ca1b0b3 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -87,7 +87,6 @@ u32 reg32; const u32 *verb; u32 verb_size; - int i; printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); @@ -117,15 +116,7 @@ printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, verb, verb_size); printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } @@ -138,15 +129,7 @@ codec_init(dev, base, i); } - for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, pc_beep_verbs[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); } static void azalia_init(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 500c004..8862628 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -87,7 +87,6 @@ u32 reg32; const u32 *verb; u32 verb_size; - int i; printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); @@ -117,15 +116,7 @@ printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, verb, verb_size); printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } @@ -138,15 +129,7 @@ codec_init(dev, base, i); } - for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, pc_beep_verbs[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); } static void azalia_init(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 5eb1ac3..54fb3be 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -86,7 +86,6 @@ u32 reg32; const u32 *verb; u32 verb_size; - int i; printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); @@ -116,15 +115,7 @@ printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, verb, verb_size); printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } @@ -137,15 +128,7 @@ codec_init(dev, base, i); } - for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, pc_beep_verbs[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); } static void azalia_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/59105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d9e0f19429620166f2a6ef48ec7c963ee64b59c Gerrit-Change-Number: 59105 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L
by Karthik Ramasubramanian (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Kevin Chiu, Raul Rangel, Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59053 ) Change subject: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Gerrit-Change-Number: 59053 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 17:11:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: google/butterfly: Refactor get_recovery_mode_switch()
by Kyösti Mälkki (Code Review) 10 Nov '21

10 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59003 to look at the new patch set (#4). Change subject: google/butterfly: Refactor get_recovery_mode_switch() ...................................................................... google/butterfly: Refactor get_recovery_mode_switch() Do not place console output in low-level GPIO functions. The caller of get_recovery_mode_switch() is in vboot_logic.c that is linked in romstage. So presumably recovery mode is broken and is not fixed with this commit either. Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/butterfly/chromeos.c 1 file changed, 4 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/59003/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Gerrit-Change-Number: 59003 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google,intel: Add ChromeOS GPIOs to onboard.h
by Kyösti Mälkki (Code Review) 10 Nov '21

10 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59000 to look at the new patch set (#4). Change subject: mb/google,intel: Add ChromeOS GPIOs to onboard.h ...................................................................... mb/google,intel: Add ChromeOS GPIOs to onboard.h Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/chromeos.c A src/mainboard/google/auron/onboard.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/onboard.h M src/mainboard/google/link/chromeos.c M src/mainboard/google/link/onboard.h M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/onboard.h M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/slippy/onboard.h M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/onboard.h M src/mainboard/intel/baskingridge/chromeos.c A src/mainboard/intel/baskingridge/onboard.h M src/mainboard/intel/emeraldlake2/chromeos.c A src/mainboard/intel/emeraldlake2/onboard.h M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/strago/onboard.h 18 files changed, 94 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/59000/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Gerrit-Change-Number: 59000 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP,RFC] Clean up spinlocks
by Raul Rangel (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Julius Werner, Kyösti Mälkki, Karthikeyan Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59094 ) Change subject: [WIP,RFC] Clean up spinlocks ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59094/comment/94297803_d3583d28 PS2, Line 11: TBD: Breaks romstage co-operative threading, since those : need implementation of spin_lock() that is not a spinlock. It's already broken. https://review.coreboot.org/c/coreboot/+/59094/comment/2e04f4c1_1d88b875 PS2, Line 14: IMO commit a98d302fe9 x86/smp/spinlock: Disable thread coop when taking spinlock : is wrong and should be reverted too. I'm fine doing that if we can come up with another way of preventing udelay from calling `thread_yield_microseconds` while in a critical section. -- To view, visit https://review.coreboot.org/c/coreboot/+/59094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba52febdeee78294f916775ee9ce8a82d6203570 Gerrit-Change-Number: 59094 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 16:53:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Rename ECAM-specific MMCONF Kconfigs
by Shelley Chen (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Stefan Reinauer, Arthur Heymans, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Morgan Jang, Michal Motyl, Alexander Couzens, Tim Chu, Felix Held, Shelley Chen, Furquan Shaikh, Angel Pons, Lance Zhao, Jason Glenesk, Martin Roth, Damien Zammit, Lee Leahy, Marshall Dawson, Vanessa Eusebio, Huang Jin. Hello build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Stefan Reinauer, Arthur Heymans, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Morgan Jang, Alexander Couzens, Tim Chu, Felix Held, Furquan Shaikh, Angel Pons, Lance Zhao, Jason Glenesk, Damien Zammit, Martin Roth, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57333 to look at the new patch set (#13). Change subject: Rename ECAM-specific MMCONF Kconfigs ...................................................................... Rename ECAM-specific MMCONF Kconfigs Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M payloads/external/Makefile.inc M payloads/external/tianocore/Makefile M src/acpi/acpi.c M src/acpi/dsdt_top.asl M src/arch/x86/include/arch/pci_io_cfg.h M src/arch/x86/include/arch/pci_ops.h M src/device/Kconfig M src/device/device_util.c M src/device/pci_ops.c M src/drivers/intel/fsp1_1/romstage.c M src/include/device/pci_mmio_cfg.h M src/lib/Kconfig M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/emulation/qemu-q35/memmap.c M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/x220/early_init.c M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/early_init.c M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/acpi/x4x.asl M src/northbridge/intel/x4x/bootblock.c M src/security/intel/stm/StmPlatformResource.c M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/common/block/pci/amd_pci_mmconf.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/fsp_m_params.c M src/soc/amd/stoneyridge/Kconfig M src/soc/cavium/cn81xx/Kconfig M src/soc/example/min86/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/systemagent.c M src/soc/intel/apollolake/systemagent.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/systemagent.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/systemagent.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/systemagent.c M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/systemagent.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/uncore.c M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/cimx/sb800/OEM.h 104 files changed, 205 insertions(+), 194 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57333/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/57333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 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Change in coreboot[master]: soc/amd/psp_verstage: Init TPM on S0i3 resume
by Raul Rangel (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Andrey Pronin, Kangheui Won, Julius Werner, Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58870 ) Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... Patch Set 9: (3 comments) File src/soc/amd/common/psp_verstage/psp_verstage.c: https://review.coreboot.org/c/coreboot/+/58870/comment/6b010491_8dde32af PS9, Line 224: rv = verstage_soc_early_init(); : if (rv) { : printk(BIOS_DEBUG, "verstage_soc_early_init failed rv:%d\n", rv); : return POSTCODE_INIT_TPM_FAILED; : } Maybe we fork too early in Main. I think we can keep doing verstage_soc_early_init in Main so we have a common error path. https://review.coreboot.org/c/coreboot/+/58870/comment/b9413adb_b9f0dda5 PS9, Line 230: verstage_mainboard_espi_init(); : /* verstage_soc_init should init i2c and eSPI */ : verstage_soc_init(); : /* : * verstage_mainboard_tpm_init may check board_id which depends on eSPI, : * so it must come after verstage_mainboard_espi_init and verstage_soc_init. : */ : verstage_mainboard_tpm_init(); Can we just make this the default flow? We can remove the TPM and eSPI pin configs out of the early_gpio_table. This way we only have 1 way of doing things. I think we could move all this into `verstage_mainboard_early_init` Even the `svc_get_boot_mode` call. https://review.coreboot.org/c/coreboot/+/58870/comment/73acd090_8e6175b8 PS9, Line 280: nit: space -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 9 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 16:31:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021