coreboot-gerrit November 2021

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Change in coreboot[master]: Rename ECAM-specific MMCONF Kconfigs
by Shelley Chen (Code Review) 10 Nov '21

10 Nov '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57333 ) Change subject: Rename ECAM-specific MMCONF Kconfigs ...................................................................... Rename ECAM-specific MMCONF Kconfigs Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M payloads/external/Makefile.inc M payloads/external/tianocore/Makefile M src/acpi/acpi.c M src/acpi/dsdt_top.asl M src/arch/x86/include/arch/pci_io_cfg.h M src/arch/x86/include/arch/pci_ops.h M src/device/Kconfig M src/device/device_util.c M src/device/pci_ops.c M src/drivers/intel/fsp1_1/romstage.c M src/include/device/pci_mmio_cfg.h M src/lib/Kconfig M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/emulation/qemu-q35/memmap.c M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/x220/early_init.c M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/early_init.c M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/acpi/x4x.asl M src/northbridge/intel/x4x/bootblock.c M src/security/intel/stm/StmPlatformResource.c M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/common/block/pci/amd_pci_mmconf.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/fsp_m_params.c M src/soc/amd/stoneyridge/Kconfig M src/soc/cavium/cn81xx/Kconfig M src/soc/example/min86/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/systemagent.c M src/soc/intel/apollolake/systemagent.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/systemagent.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/systemagent.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/systemagent.c M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/systemagent.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/uncore.c M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/cimx/sb800/OEM.h 104 files changed, 205 insertions(+), 194 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index b8c2d57..6db1720 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -146,7 +146,7 @@ CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \ CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \ - CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \ + CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 0c5fdb3..a4ccfc7 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -9,7 +9,7 @@ project_git_branch=uefipayload_202107 upstream_git_repo=https://github.com/tianocore/edk2 -build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE +build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) project_git_branch=coreboot_fb diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 60f8c21..78c3fd3 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -266,7 +266,8 @@ static unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); + CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0, + CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); return current; } @@ -291,7 +292,7 @@ header->length = sizeof(acpi_mcfg_t); header->revision = get_acpi_table_revision(MCFG); - if (CONFIG(MMCONF_SUPPORT)) + if (CONFIG(ECAM_MMCONF_SUPPORT)) current = acpi_fill_mcfg(current); /* (Re)calculate length and checksum. */ diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl index ff148ae..7b9b2d8 100644 --- a/src/acpi/dsdt_top.asl +++ b/src/acpi/dsdt_top.asl @@ -31,13 +31,13 @@ PICM = Arg0 } -#if CONFIG(MMCONF_SUPPORT) +#if CONFIG(ECAM_MMCONF_SUPPORT) Scope(\_SB) { /* Base address of PCIe config space */ - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) + Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS) /* Length of PCIe config space, 1MB each bus */ - Name(PCLN, CONFIG_MMCONF_LENGTH) + Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH) /* PCIe Configuration Space */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 61dd106..5e69288 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -69,7 +69,7 @@ outl(value, 0xCFC); } -#if !CONFIG(MMCONF_SUPPORT) +#if !CONFIG(ECAM_MMCONF_SUPPORT) /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index abbd35c..51a5784 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -4,7 +4,7 @@ #define ARCH_I386_PCI_OPS_H #include <arch/pci_io_cfg.h> -#if CONFIG(MMCONF_SUPPORT) +#if CONFIG(ECAM_MMCONF_SUPPORT) #include <device/pci_mmio_cfg.h> #endif diff --git a/src/device/Kconfig b/src/device/Kconfig index ea3e241..cd8d8e9 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -499,13 +499,21 @@ if PCI -config NO_MMCONF_SUPPORT +config NO_ECAM_MMCONF_SUPPORT bool default n + help + Disable the use of the Enhanced Configuration + Access mechanism (ECAM) method for accessing PCI config + address space. -config MMCONF_SUPPORT +config ECAM_MMCONF_SUPPORT bool - default !NO_MMCONF_SUPPORT + default !NO_ECAM_MMCONF_SUPPORT + help + Enable the use of the Enhanced Configuration + Access mechanism (ECAM) method for accessing PCI config + address space. config PCIX_PLUGIN_SUPPORT bool @@ -540,20 +548,20 @@ bool default y -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS hex - depends on MMCONF_SUPPORT + depends on ECAM_MMCONF_SUPPORT -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int - depends on MMCONF_SUPPORT + depends on ECAM_MMCONF_SUPPORT -config MMCONF_LENGTH +config ECAM_MMCONF_LENGTH hex - depends on MMCONF_SUPPORT - default 0x04000000 if MMCONF_BUS_NUMBER = 64 - default 0x08000000 if MMCONF_BUS_NUMBER = 128 - default 0x10000000 if MMCONF_BUS_NUMBER = 256 + depends on ECAM_MMCONF_SUPPORT + default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64 + default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128 + default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256 default 0x0 config PCI_ALLOW_BUS_MASTER @@ -619,7 +627,7 @@ config PCIEXP_L1_SUB_STATE prompt "Enable PCIe ASPM L1 SubState" bool - depends on (MMCONF_SUPPORT || PCI_IO_CFG_EXT) + depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT) default n help Detect and enable ASPM on PCIe links. @@ -635,8 +643,8 @@ config PCIEXP_HOTPLUG_BUSES int "PCI Express Hotplug Buses" - default 8 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 64 - default 16 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 128 + default 8 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 64 + default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128 default 32 help This is the number of buses allocated for hotplug PCI express diff --git a/src/device/device_util.c b/src/device/device_util.c index 7b72a94..039e562 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -857,8 +857,8 @@ void mmconf_resource(struct device *dev, unsigned long index) { struct resource *resource = new_resource(dev, index); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_LENGTH; + resource->base = CONFIG_ECAM_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_ECAM_MMCONF_LENGTH; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 76d5e96..a4ef405 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -7,7 +7,7 @@ #include <device/pci_ops.h> #include <device/pci_type.h> -u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS; +u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS; /** * Given a device, a capability type, and a last position, return the next diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index f858c93..3ed73d3 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -103,9 +103,9 @@ timestamp_add_now(TS_START_ROMSTAGE); /* Display parameters */ - if (!CONFIG(NO_MMCONF_SUPPORT)) - printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", - CONFIG_MMCONF_BASE_ADDRESS); + if (!CONFIG(NO_ECAM_MMCONF_SUPPORT)) + printk(BIOS_SPEW, "CONFIG_ECAM_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_ECAM_MMCONF_BASE_ADDRESS); printk(BIOS_INFO, "Using FSP 1.1\n"); /* Display FSP banner */ diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 81faa9c..cabf5b7 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -25,17 +25,17 @@ uint32_t reg32[4096 / sizeof(uint32_t)]; }; -#if CONFIG(MMCONF_SUPPORT) +#if CONFIG(ECAM_MMCONF_SUPPORT) -#if CONFIG_MMCONF_BASE_ADDRESS == 0 -#error "CONFIG_MMCONF_BASE_ADDRESS undefined!" +#if CONFIG_ECAM_MMCONF_BASE_ADDRESS == 0 +#error "CONFIG_ECAM_MMCONF_BASE_ADDRESS undefined!" #endif -#if CONFIG_MMCONF_BUS_NUMBER * MiB != CONFIG_MMCONF_LENGTH -#error "CONFIG_MMCONF_LENGTH does not correspond with CONFIG_MMCONF_BUS_NUMBER!" +#if CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB != CONFIG_ECAM_MMCONF_LENGTH +#error "CONFIG_ECAM_MMCONF_LENGTH does not correspond with CONFIG_ECAM_MMCONF_BUS_NUMBER!" #endif -/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we +/* By not assigning this to CONFIG_ECAM_MMCONF_BASE_ADDRESS here we prevent some sub-optimal constant folding. */ extern u8 *const pci_mmconf; diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 41df1f1..0f18425 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -70,7 +70,7 @@ config HWBASE_DEFAULT_MMCONF hex - default MMCONF_BASE_ADDRESS + default ECAM_MMCONF_BASE_ADDRESS config HWBASE_DIRECT_PCIDEV def_bool y diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index 8653cec..ddac440 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -85,7 +85,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 8728e4e..dd11092 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_QEMU_X86 - select NO_MMCONF_SUPPORT + select NO_ECAM_MMCONF_SUPPORT select SOUTHBRIDGE_INTEL_I82371EB select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index e078aa9..155540d 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -56,10 +56,10 @@ config MAINBOARD_PART_NUMBER default "QEMU x86 q35/ich9" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xb0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index ec86c70a..98fcb62 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -11,12 +11,12 @@ { /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to + * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index 5c42921..7d5180e 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -14,7 +14,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -24,7 +24,7 @@ uint32_t make_pciexbar(void) { - return CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + return CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; } /* Check that MCFG is active. If it's not, QEMU was started for machine PC */ diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index ba30016..ed47fda 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -79,7 +79,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 088d538..0e2bb4f 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -88,7 +88,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index a11dc91..dd24f5b 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -57,7 +57,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 6b28e00..e08da8d 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -94,7 +94,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index df8112c..ada0a5c 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -17,7 +17,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index aa481dc..54baafb 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -54,7 +54,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 55902db0..8305648 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -59,7 +59,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 07a5dbd..edb5324 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -15,7 +15,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 37de919..3d5b3ba 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -13,7 +13,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index c18318d..d36c8f9 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -43,7 +43,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 3d4ad80..a885f5b 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -119,7 +119,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index d18da56..dbfc2d2 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -104,7 +104,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 27c9c21..941972b 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -11,10 +11,10 @@ hex default 0x100000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 endif # NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 3b66f56..5bb7cca 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -11,10 +11,10 @@ hex default 0x100000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index ee02865..8cf919a 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -11,10 +11,10 @@ hex default 0x100000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config VGA_BIOS_ID diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index c1fc9a8..27ae673 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -10,10 +10,10 @@ hex default 0x100000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config VGA_BIOS_ID diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index d9cf8af..c0711ee 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -7,7 +7,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y - select NO_MMCONF_SUPPORT + select NO_ECAM_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_CBFS_MCACHE select LEGACY_SMP_INIT diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index e3675db..3f632a1 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -23,10 +23,10 @@ string default "8086,2a42" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xf0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 64 diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 43d73e9..c4636be 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -16,7 +16,7 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index a9a1e8e..eb1aa0a 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -9,7 +9,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -21,17 +21,17 @@ { /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to + * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to * true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0); pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 61c201a..50acb09a 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -32,10 +32,10 @@ string default "8086,0166" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xf0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 64 diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 7dfae9f..513e960 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -125,7 +125,7 @@ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + // PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -161,7 +161,7 @@ } PMIN = Local0 - PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 PLEN = (PMAX - PMIN) + 1 Return (MCRS) @@ -178,7 +178,7 @@ Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE) - Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 1336582..03a715f 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -9,7 +9,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -21,15 +21,15 @@ { /* * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all + * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all * subsequent non-explicit config accesses use MCFG. This code also assumes * that bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 338b4d0..f71d117 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -349,7 +349,7 @@ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .hpet_address = CONFIG_HPET_ADDRESS, .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 0fcadce..4b1638c 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_INTEL_I440BX bool - select NO_MMCONF_SUPPORT + select NO_ECAM_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_CBFS_MCACHE select LEGACY_SMP_INIT diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index ac19fcc..7a05d20 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -35,10 +35,10 @@ for the LVDS port. A linear framebuffer is only supported for LVDS. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xf0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 64 diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 683ad37..f935b71 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -40,7 +40,7 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 448d5e4..1486a1b 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -9,7 +9,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -20,14 +20,16 @@ void bootblock_early_northbridge_init(void) { /* - * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit - * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final assumption is that - * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the + * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way + * all subsequent non-explicit config accesses use MCFG. This code also + * assumes that bootblock_northbridge_init() is the first thing called + * in the non-asm boot block code. The final assumption is that no + * assembly code is using the CONFIG(ECAM_MMCONF_SUPPORT) option to do + * PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index 9fb7769..a614058 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -39,10 +39,10 @@ The amount of anticipated stack usage in CAR by bootblock and other stages. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 256 config INTEL_GMA_BCLV_OFFSET diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 098dd13..b4bd8e9 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -14,7 +14,7 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 241eb43..58f49da 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -10,7 +10,7 @@ static uint32_t encode_pciexbar_length(void) { /* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */ - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 6 << 1; case 64: return 7 << 1; @@ -27,7 +27,7 @@ */ const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1); - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0); pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 3fb1c10..9a8b21e 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -21,7 +21,7 @@ #include "memmap.h" -#define QUICKPATH_BUS (CONFIG_MMCONF_BUS_NUMBER - 1) +#define QUICKPATH_BUS (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1) #include <southbridge/intel/ibexpeak/pch.h> diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index f85cd2e..b2a0730 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -19,10 +19,10 @@ string default "8086,a001" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 4b74469..4901c21 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -15,7 +15,7 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */ diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 61bd2ee..498d21a 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -8,7 +8,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -18,6 +18,6 @@ void bootblock_early_northbridge_init(void) { - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ae24690..3abbddf 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -83,12 +83,12 @@ string default "8086,0106" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xf0000000 help The MRC blob requires it to be at 0xf0000000. -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 64 diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 977d7a7..4ce4cb6 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -320,7 +320,7 @@ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + // PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -356,7 +356,7 @@ } PMIN = Local0 - PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 PLEN = PMAX - PMIN + 1 Return (MCRS) diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 1eba744..9e3708a 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -9,7 +9,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -21,15 +21,15 @@ { /* * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all + * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all * subsequent non-explicit config accesses use MCFG. This code also assumes * that bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index ee5f1c9..186ab59 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -231,7 +231,7 @@ pei_data->mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE; pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE; pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE; - pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS; pei_data->hpet_address = CONFIG_HPET_ADDRESS; pei_data->thermalbase = 0xfed08000; pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE); diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 8eda090..5318623 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -21,10 +21,10 @@ string default "8086,2e32" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 8ef0ca4..462cdf9 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -13,7 +13,7 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index f15d181..80375a7 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -10,7 +10,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -23,6 +23,6 @@ /* Disable LaGrande Technology (LT) */ read32((void *)TPM_BASE_ADDRESS); - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c index a8da98c..75d52a2 100644 --- a/src/security/intel/stm/StmPlatformResource.c +++ b/src/security/intel/stm/StmPlatformResource.c @@ -98,8 +98,8 @@ static void fixup_pciex_resource(void) { // Find max bus number and PCIEX length - rsc_pcie_mmio.length = CONFIG_MMCONF_LENGTH; // 0x10000000;// 256 MB - rsc_pcie_mmio.base = CONFIG_MMCONF_BASE_ADDRESS; + rsc_pcie_mmio.length = CONFIG_ECAM_MMCONF_LENGTH; // 0x10000000;// 256 MB + rsc_pcie_mmio.base = CONFIG_ECAM_MMCONF_BASE_ADDRESS; } /* diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index dbafa8c..16f1d3f 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -216,10 +216,10 @@ depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A default "apu/amdfw" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config MAX_CPUS diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl index f9956b6..08ccbe6 100644 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ b/src/soc/amd/cezanne/acpi/pci0.asl @@ -66,14 +66,14 @@ /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ MM1B = TOM1 - Local0 = CONFIG_MMCONF_BASE_ADDRESS + Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS Local0 -= TOM1 MM1L = Local0 CreateWordField(CRES, ^PSB0._MAX, BMAX) CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_MMCONF_BUS_NUMBER + BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 9f594d9..048b428 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -70,7 +70,7 @@ mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); - mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; + mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c index cb221e2..fb4db39 100644 --- a/src/soc/amd/common/block/pci/amd_pci_mmconf.c +++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c @@ -10,7 +10,7 @@ msr_t mmconf; mmconf.hi = 0; - mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN - | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; wrmsr(MMIO_CONF_BASE, mmconf); } diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6fc4825..92607a3 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -200,10 +200,10 @@ hex default 0x10000000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config VERSTAGE_ADDR diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 292cdd8..df21e9d 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -73,14 +73,14 @@ /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ MM1B = TOM1 - Local0 = CONFIG_MMCONF_BASE_ADDRESS + Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS Local0 -= TOM1 MM1L = Local0 CreateWordField(CRES, ^PSB0._MAX, BMAX) CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_MMCONF_BUS_NUMBER + BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/soc/amd/picasso/fsp_m_params.c b/src/soc/amd/picasso/fsp_m_params.c index 6a5c074..6483394 100644 --- a/src/soc/amd/picasso/fsp_m_params.c +++ b/src/soc/amd/picasso/fsp_m_params.c @@ -19,7 +19,7 @@ mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); - mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; + mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ec36b34..50e66b0 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -120,10 +120,10 @@ option is useful when PCI peripherals requesting large address ranges are present. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config VGA_BIOS_ID diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 87edf45..368581f 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -9,7 +9,7 @@ select UART_OVERRIDE_REFCLK select SOC_CAVIUM_COMMON select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS - select MMCONF_SUPPORT + select ECAM_MMCONF_SUPPORT select PCI if SOC_CAVIUM_CN81XX @@ -36,7 +36,7 @@ config STACK_SIZE default 0x2000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0x848000000000 endif diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig index 660bf36..d176752 100644 --- a/src/soc/example/min86/Kconfig +++ b/src/soc/example/min86/Kconfig @@ -16,7 +16,7 @@ def_bool y select ARCH_X86 select NO_MONOTONIC_TIMER - select NO_MMCONF_SUPPORT + select NO_ECAM_MMCONF_SUPPORT select UNKNOWN_TSC_RATE config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 214829a..58b9051 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -203,7 +203,7 @@ help This option allows you to select MMIO Base Address of sideband bus. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xc0000000 config CPU_BCLK_MHZ diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 6bd02ee..1736e32 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -25,7 +25,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, + { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index b8f7995..d6e23ac 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -18,7 +18,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, + { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, }; diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 9f1cb8e..c2d24b2 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -39,10 +39,10 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 5f20463..c994fda 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -144,7 +144,7 @@ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,,, LMEM) - /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ + /* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -184,7 +184,7 @@ /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) + Store (Subtract(CONFIG_ECAM_MMCONF_BASE_ADDRESS, 1), PMAX) Add (Subtract (PMAX, PMIN), 1, PLEN) Return (MCRS) @@ -198,7 +198,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) @@ -247,7 +247,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) - Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS) + Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS) Return (^RBUF) } } diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index fa8283c..3f07a6b 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -89,7 +89,7 @@ reg = 0; /* Clear the extended register. */ pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 1; + reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | 1; pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 8ccf043..f297b8f 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -54,10 +54,10 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 01d1bc0..8e765de 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -146,7 +146,7 @@ 0x00000000, 0x20000000, 0x201FFFFF, 0x00000000, 0x00200000,,, LMEM) - /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ + /* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -183,7 +183,7 @@ /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) + Store (Subtract(CONFIG_ECAM_MMCONF_BASE_ADDRESS, 1), PMAX) Add (Subtract (PMAX, PMIN), 1, PLEN) Return (MCRS) @@ -197,7 +197,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) @@ -246,7 +246,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) - Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS) + Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS) Return (^RBUF) } } diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index ae1c97a..545642f 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -100,7 +100,7 @@ reg = 0; /* Clear the extended register. */ pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 1; + reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | 1; pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index f02e810..766c226 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -33,10 +33,10 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xf0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config VGA_BIOS_ID diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c index bd88195..8c851ca 100644 --- a/src/soc/intel/broadwell/bootblock.c +++ b/src/soc/intel/broadwell/bootblock.c @@ -8,7 +8,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -20,15 +20,15 @@ { /* * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all + * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all * subsequent non-explicit config accesses use MCFG. This code also assumes * that bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index c8fbfca..db41b4b 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -15,7 +15,7 @@ pei_data->pei_version = PEI_VERSION; pei_data->board_type = BOARD_TYPE_ULT; pei_data->usbdebug = CONFIG(USBDEBUG); - pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS; pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE; pei_data->ehcibar = CONFIG_EHCI_BAR; pei_data->xhcibar = 0xd7000000; diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 0b5e8e3..a2bea45 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -20,7 +20,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, + { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 315c0f5..e9519bc 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -5,10 +5,10 @@ if SOC_INTEL_COMMON_BLOCK_SA -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 256 config SA_ENABLE_IMR diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 6808117..a77b307 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -29,7 +29,7 @@ pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); /* Get PCI Express Region Length */ - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: pciexbar_length = PCIEXBAR_LENGTH_256MB; break; @@ -42,7 +42,7 @@ default: dead_code(); } - reg = CONFIG_MMCONF_BASE_ADDRESS | (pciexbar_length << 1) + reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | (pciexbar_length << 1) | PCIEXBAR_PCIEXBAREN; pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index a84cf1e..0643384 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -44,10 +44,10 @@ select FSP_T_XIP if FSP_CAR select FSP_M_XIP -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index 26a6f2e..e415dc4 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -122,7 +122,7 @@ Name (PDRS, ResourceTemplate() { // PCIEXBAR memory range - Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadOnly, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) // TSEG Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB) }) diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 1aebab4..cb2503a 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -74,8 +74,8 @@ break; } - assert(base == CONFIG_MMCONF_BASE_ADDRESS); - assert(length == CONFIG_MMCONF_BUS_NUMBER); + assert(base == CONFIG_ECAM_MMCONF_BASE_ADDRESS); + assert(length == CONFIG_ECAM_MMCONF_BUS_NUMBER); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index e5e9a06..c220028 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -130,7 +130,7 @@ help This option allows you to select MMIO Base Address of sideband bus. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xc0000000 config CPU_BCLK_MHZ diff --git a/src/soc/intel/elkhartlake/systemagent.c b/src/soc/intel/elkhartlake/systemagent.c index aa9c87f..02ede59 100644 --- a/src/soc/intel/elkhartlake/systemagent.c +++ b/src/soc/intel/elkhartlake/systemagent.c @@ -19,7 +19,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, + { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index fcc0bfa..e99832d 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -118,7 +118,7 @@ help This option allows you to select MMIO Base Address of sideband bus. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xc0000000 config CPU_BCLK_MHZ diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index 2f0b706..4a24d39 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -15,7 +15,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, + { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 03f4705..7a73d98 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -126,7 +126,7 @@ help This option allows you to select MMIO Base Address of sideband bus. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xc0000000 config CPU_BCLK_MHZ diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index 45a83bc..fd04be5 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -19,7 +19,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, + { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 1a9bfef..ad885d5 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -10,7 +10,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select NO_MMCONF_SUPPORT + select NO_ECAM_MMCONF_SUPPORT select REG_SCRIPT select PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index f112087..6186734 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -34,7 +34,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, + { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 33e8b13..91f3316 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -161,7 +161,7 @@ help This option allows you to select MMIO Base Address of sideband bus. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xc0000000 config CPU_BCLK_MHZ diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index f1aa600..0e9488c 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -27,7 +27,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, + { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index fa8403a..d912f17 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -103,10 +103,10 @@ hex default 0x10000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0x80000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 256 config HEAP_SIZE diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 4f50980..e51efbd 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -137,7 +137,7 @@ * | P2SB PCR cfg BAR | (0xfd000000 - 0xfdffffff * | BAR space | [mem 0x90000000-0xfcffffff] available for PCI devices * +--------------------------+ 0x9000_0000 - * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB + * |PCIe MMCFG (relocatable) | CONFIG_ECAM_MMCONF_BASE_ADDRESS 64 or 256MB * | | (0x80000000 - 0x8fffffff, 0x40000) * +--------------------------+ TOLM * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 4103961..2317daf 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -1088,9 +1088,9 @@ #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) #endif -#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS) +#define CFG_PCI_MMIO_BASE (CONFIG_ECAM_MMCONF_BASE_ADDRESS) -#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER) +#define CFG_PCI_MMIO_SIZE (CONFIG_ECAM_MMCONF_BUS_NUMBER) #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index fa1bca1..798c1cc 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -2444,9 +2444,9 @@ #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) #endif -#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS) +#define CFG_PCI_MMIO_BASE (CONFIG_ECAM_MMCONF_BASE_ADDRESS) -#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER) +#define CFG_PCI_MMIO_SIZE (CONFIG_ECAM_MMCONF_BUS_NUMBER) #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 2a58869..8896b03 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -1451,9 +1451,9 @@ #define CFG_LHTC_TEMPERATURE_LIMIT (0) #endif -#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS) +#define CFG_PCI_MMIO_BASE (CONFIG_ECAM_MMCONF_BASE_ADDRESS) -#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER) +#define CFG_PCI_MMIO_SIZE (CONFIG_ECAM_MMCONF_BUS_NUMBER) #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h index d81f93c..c184c65 100644 --- a/src/vendorcode/amd/cimx/sb800/OEM.h +++ b/src/vendorcode/amd/cimx/sb800/OEM.h @@ -52,7 +52,7 @@ #ifdef MOVE_PCIEBAR_TO_F0000000 #define PCIEX_BASE_ADDRESS 0xF7000000 #else - #define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + #define PCIEX_BASE_ADDRESS CONFIG_ECAM_MMCONF_BASE_ADDRESS #endif /** -- To view, visit https://review.coreboot.org/c/coreboot/+/57333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Gerrit-Change-Number: 57333 Gerrit-PatchSet: 14 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [WIP,RFC] Clean up spinlocks
by Kyösti Mälkki (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Julius Werner, Karthikeyan Ramasubramanian, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59094 ) Change subject: [WIP,RFC] Clean up spinlocks ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59094/comment/98b42155_7c2d16ad PS2, Line 14: IMO commit a98d302fe9 x86/smp/spinlock: Disable thread coop when taking spinlock : is wrong and should be reverted too. > I'm fine doing that if we can come up with another way of preventing udelay from calling `thread_yie […] Do not hold spinlock while calling udelay(), use thread_mutex() instead to guard sections where context switching may happen. Now I am not going to -2 these threding and spinlock changes. Just understand your DMA performance currently relies on periodic context switches, and you really really should not rely on uart8250mem and printk() to satisfy that. Or am I missing something, I did not read the DMA code that thoroughly. -- To view, visit https://review.coreboot.org/c/coreboot/+/59094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba52febdeee78294f916775ee9ce8a82d6203570 Gerrit-Change-Number: 59094 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 17:20:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Tim Wawrzynczak (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Subrata Banik, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56628 ) Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... Patch Set 25: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 25 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 17:20:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Preload FSP-S
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59025 ) Change subject: soc/amd/cezanne: Preload FSP-S ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95 Gerrit-Change-Number: 59025 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 17:20:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Rename ECAM-specific MMCONF Kconfigs
by Tim Wawrzynczak (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Stefan Reinauer, Arthur Heymans, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Morgan Jang, Michal Motyl, Alexander Couzens, Tim Chu, Felix Held, Shelley Chen, Furquan Shaikh, Angel Pons, Lance Zhao, Jason Glenesk, Martin Roth, Damien Zammit, Lee Leahy, Marshall Dawson, Vanessa Eusebio, Huang Jin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57333 ) Change subject: Rename ECAM-specific MMCONF Kconfigs ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Gerrit-Change-Number: 57333 Gerrit-PatchSet: 13 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 17:19:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Use LZ4 for FSP-S
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59026 ) Change subject: soc/amd/cezanne: Use LZ4 for FSP-S ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Gerrit-Change-Number: 59026 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 17:18:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59029 ) Change subject: sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921 Gerrit-Change-Number: 59029 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 17:18:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: enable LPC decodes if platform uses LPC
by Raul Rangel (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Jeremy Soller, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59103 ) Change subject: soc/amd/cezanne: enable LPC decodes if platform uses LPC ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/soc/amd/cezanne/early_fch.c: https://review.coreboot.org/c/coreboot/+/59103/comment/e6292841_2de099c8 PS2, Line 24: lpc_configure_decodes Maybe in the future we can add an lpc_config so the decodes can be specified: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… -- To view, visit https://review.coreboot.org/c/coreboot/+/59103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67 Gerrit-Change-Number: 59103 Gerrit-PatchSet: 2 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 17:15:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lynxpoint/broadwell: Use `azalia_codecs_init()`
by Angel Pons (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59120 ) Change subject: lynxpoint/broadwell: Use `azalia_codecs_init()` ...................................................................... lynxpoint/broadwell: Use `azalia_codecs_init()` Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: Id25d2797a91b05264b1a76fa8faec0533dd5ac78 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/Kconfig M src/soc/intel/broadwell/pch/hda.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/azalia.c 4 files changed, 8 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/59120/1 diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 4e187ff..3fbaa79 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -24,6 +24,9 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SPI_FLASH +config AZALIA_MAX_CODECS + default 4 + config EHCI_BAR hex default 0xd8000000 diff --git a/src/soc/intel/broadwell/pch/hda.c b/src/soc/intel/broadwell/pch/hda.c index 5c5e08f..c292b94 100644 --- a/src/soc/intel/broadwell/pch/hda.c +++ b/src/soc/intel/broadwell/pch/hda.c @@ -11,20 +11,6 @@ #include <soc/rcba.h> #include <southbridge/intel/lynxpoint/hda_verb.h> -static void codecs_init(u8 *base, u32 codec_mask) -{ - int i; - - /* Can support up to 4 codecs */ - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size); - } - - if (pc_beep_verbs_size) - azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); -} - static void hda_pch_init(struct device *dev, u8 *base) { u8 reg8; @@ -94,7 +80,7 @@ if (codec_mask) { printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); - codecs_init(base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 891b06a..b7c719b 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -41,6 +41,9 @@ help Set this option to y for LynxPoint LP (Haswell ULT). +config AZALIA_MAX_CODECS + default 4 + config EHCI_BAR hex default 0xe8000000 diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 9201caa..1bde180 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -11,20 +11,6 @@ #include "pch.h" #include "hda_verb.h" -static void codecs_init(u8 *base, u32 codec_mask) -{ - int i; - - /* Can support up to 4 codecs */ - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size); - } - - if (pc_beep_verbs_size) - azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); -} - static void azalia_pch_init(struct device *dev, u8 *base) { u8 reg8; @@ -115,7 +101,7 @@ if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - codecs_init(base, codec_mask); + azalia_codecs_init(base, codec_mask); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/59120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25d2797a91b05264b1a76fa8faec0533dd5ac78 Gerrit-Change-Number: 59120 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/azalia_device: Drop unused function parameter
by Angel Pons (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59119 ) Change subject: device/azalia_device: Drop unused function parameter ...................................................................... device/azalia_device: Drop unused function parameter The `dev` parameter of the `azalia_codecs_init()` function is not used. Remove it, and update all call sites accordingly. Change-Id: Idbe4a6ee5e81d5a7fd451fb83e0fe91bd0c09f0e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c M src/include/device/azalia_device.h M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c 7 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59119/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 2305101..e61e1dc 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -270,7 +270,7 @@ mainboard_azalia_program_runtime_verbs(base, reg32); } -void azalia_codecs_init(struct device *dev, u8 *base, u16 codec_mask) +void azalia_codecs_init(u8 *base, u16 codec_mask) { int i; @@ -300,7 +300,7 @@ if (codec_mask) { printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask); - azalia_codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index d717fdd..1562e25 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -24,7 +24,7 @@ u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb); int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size); void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes); -void azalia_codecs_init(struct device *dev, u8 *base, u16 codec_mask); +void azalia_codecs_init(u8 *base, u16 codec_mask); void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index ae9b821..0a0b515 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -110,7 +110,7 @@ if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - azalia_codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } /* Enable dynamic clock gating */ diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 0730744..33a0cd8 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -95,7 +95,7 @@ if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - azalia_codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index c929be7..26144c3 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -78,7 +78,7 @@ if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - azalia_codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index c637f08..bb8aec4 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -78,7 +78,7 @@ if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - azalia_codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 32b4bb0..17db658 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -116,7 +116,7 @@ if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - azalia_codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } /* Enable dynamic clock gating */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbe4a6ee5e81d5a7fd451fb83e0fe91bd0c09f0e Gerrit-Change-Number: 59119 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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