coreboot-gerrit November 2021

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Change in coreboot[master]: WIP soc: Added dram information to cbmem WIP
by Ravi kumar (Code Review) 11 Nov '21

11 Nov '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: WIP soc: Added dram information to cbmem WIP ...................................................................... WIP soc: Added dram information to cbmem WIP Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 --- M src/soc/qualcomm/common/include/soc/mmu_common.h M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7280/memlayout.ld 5 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59195/1 diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h index b6c8aab..38909fd 100644 --- a/src/soc/qualcomm/common/include/soc/mmu_common.h +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -11,6 +11,7 @@ #define DEV_MEM (MA_DEV | MA_S | MA_RW) static struct region * const ddr_region = (struct region *)_ddr_information; +static struct region * const mem_chip_region = (struct region *)_mem_chip_info; void soc_mmu_dram_config_post_dram_init(void); void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size); diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index c906ef2..1f2ff16 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -22,6 +22,7 @@ #define QCLIB_TE_DDR_TRAINING_DATA "ddr_training_data" #define QCLIB_TE_LIMITS_CFG_DATA "limits_cfg_data" #define QCLIB_TE_QCSDI "qcsdi" +#define QCLIB_TE_MEM_CHIP_INFO "mem_chip_info" /* memchip info */ /* BA_BMASK_VALUES (blob_attributes bit mask values) */ #define QCLIB_BA_SAVE_TO_STORAGE 0x00000001 diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index 7560266..7a7edfe 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -26,5 +26,6 @@ DECLARE_REGION(shrm) DECLARE_REGION(dram_cpucp) DECLARE_REGION(dram_modem) +DECLARE_REGION(mem_chip_info) #endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index e016f25..3785505 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -18,6 +18,73 @@ #include <vb2_api.h> #define QCLIB_VERSION 0 +#define TEST_CODE 1 + +static void write_mem_chip_information(struct qclib_cb_if_table_entry *te); +void *mem_chip_offset; +uint32_t mem_chip_size; + +#if TEST_CODE /* Added this structure for testing purpose, will be remove once changes are reviewd */ +#define DDR_MAX_NUM_CH_TEST 2 +typedef struct +{ + uint64_t type; // enum that differentiates DDR3, LPDDR3, LPDDR4, etc. + uint64_t num_channels; // To know how may channels are available. + uint64_t reserved[6]; // Reserved [6] + struct + { + uint64_t density; // Total density Seen on channel + uint64_t io_width; // JEDEC MR8 - io width + uint64_t manufacturer_id; // JEDEC MR5 + uint64_t revision_id[2]; // JEDEC MR6, MR7 + uint64_t reserved[4]; // Reserved + uint64_t serial_id[8]; // for potential future LPDDR5 expansion + } channels[DDR_MAX_NUM_CH_TEST]; +}dram_info; +#endif /* End of TEST_CODE */ + +static void write_mem_chip_information(struct qclib_cb_if_table_entry *te) +{ + /* Save MEM CHIP info in SRAM region to share with ramstage */ + mem_chip_offset = (void *)te->blob_address; + mem_chip_size = te->size; + +#if TEST_CODE /* Added this for testing purpose, will be remove once changes are reviewd */ + dram_info memchip; + /* Test Code to print memchip information before adding cbmem_add */ + printk(BIOS_INFO, "%s:%s: Test Code to print memchip information before adding cbmem_add\n", __FILE__, __func__); + memcpy(&memchip, (struct dram_info *)te->blob_address, sizeof(memchip)); + printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); + printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); + printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); + printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); +#endif /* End of TEST_CODE */ +} + +static void add_mem_chip_info(int unused) +{ + void *mem_region_base; + + /* Add cbmem */ + mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, mem_chip_size); + ASSERT(mem_region_base != NULL); + + /* Migrate the data into CBMEM */ + memcpy(mem_region_base, mem_chip_offset, mem_chip_size); + +#if TEST_CODE /* Added this for testing purpose, will be remove once changes are reviewd */ + dram_info memchip; + /* Test Code to print memchip information after adding cbmem_addd */ + printk(BIOS_INFO, "%s:%s: Test Code to print memchip information after adding cbmem_add\n", __FILE__, __func__); + memcpy(&memchip, (struct dram_info *)mem_region_base, sizeof(memchip)); + printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); + printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); + printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); + printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); +#endif /* End of TEST_CODE */ +} + +ROMSTAGE_CBMEM_INIT_HOOK(add_mem_chip_info); struct qclib_cb_if_table qclib_cb_if_table = { .magic = QCLIB_MAGIC_NUMBER, @@ -86,6 +153,9 @@ sizeof(te->name))) { write_qclib_log_to_cbmemc(te); + } else if (!strncmp(QCLIB_TE_MEM_CHIP_INFO, te->name, + sizeof(te->name))) { + write_mem_chip_information(te); } else { @@ -139,6 +209,10 @@ qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, _ddr_training, REGION_SIZE(ddr_training), 0); + /* Attempt to read MEM CHIP information */ + qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, + _mem_chip_info, REGION_SIZE(mem_chip_info), 0); + /* Attempt to load PMICCFG Blob */ data_size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", _pmic, REGION_SIZE(pmic)); diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 1677dc4..3a9c3b5 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -48,6 +48,7 @@ REGION(pmic, 0x14866000, 96K, 4K) REGION(ddr_training, 0x1487E000, 32K, 4K) REGION(qclib, 0x14886000, 800K, 4K) + REGION(mem_chip_info, 0x1494E000, 1K, 1K) /* memchip info */ BSRAM_END(0x14950000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP src/lib: Added CBMEM tag id to parse ddr information WIP
by Ravi kumar (Code Review) 11 Nov '21

11 Nov '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59194 ) Change subject: WIP src/lib: Added CBMEM tag id to parse ddr information WIP ...................................................................... WIP src/lib: Added CBMEM tag id to parse ddr information WIP Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f --- M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 3 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/59194/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index a9cf7bd..92871f1 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -79,6 +79,7 @@ #define CBMEM_ID_FSP_LOGO 0x4c4f474f #define CBMEM_ID_SMM_COMBUFFER 0x53534d32 #define CBMEM_ID_TYPE_C_INFO 0x54595045 +#define CBMEM_ID_MEM_CHIP_INFO 0x10 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -147,5 +148,6 @@ { CBMEM_ID_FMAP, "FMAP "}, \ { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \ - { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"} + { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"}, \ + { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO "} #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 91da8e0..c47b2f6 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -91,6 +91,7 @@ LB_TAG_OPTION_ENUM = 0x00ca, LB_TAG_OPTION_DEFAULTS = 0x00cb, LB_TAG_OPTION_CHECKSUM = 0x00cc, + LB_TAG_MEM_CHIP_INFO = 0x00ce, /* memchip info */ }; /* Since coreboot is usually compiled 32bit, gcc will align 64bit diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d0cba80..ccb2320 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -253,6 +253,7 @@ {CBMEM_ID_FMAP, LB_TAG_FMAP}, {CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF}, {CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO}, + {CBMEM_ID_MEM_CHIP_INFO, LB_TAG_MEM_CHIP_INFO} }; int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/59194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f Gerrit-Change-Number: 59194 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP libpayload: Parse DDR Information through coreboot tables WIP
by Ravi kumar (Code Review) 11 Nov '21

11 Nov '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: WIP libpayload: Parse DDR Information through coreboot tables WIP ...................................................................... WIP libpayload: Parse DDR Information through coreboot tables WIP Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c 3 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59193/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 914cfa5..2e3a416 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -88,6 +88,7 @@ CB_TAG_OPTION_ENUM = 0x00ca, CB_TAG_OPTION_DEFAULTS = 0x00cb, CB_TAG_OPTION_CHECKSUM = 0x00cc, + CB_TAG_MEM_CHIP_INFO = 0x00ce, /* memchip info */ }; struct cbuint64 { diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index b34476d..6197fc4 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -83,6 +83,7 @@ uintptr_t compiler; uintptr_t linker; uintptr_t assembler; + uintptr_t mem_chip_base; uintptr_t cb_version; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index bd10411..3221416 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -128,6 +128,11 @@ info->macs[i] = macs->mac_addrs[i]; } +static void cb_parse_mem_chip_info(void *ptr, struct sysinfo_t *info) +{ + info->mem_chip_base = get_cbmem_addr(ptr); +} + static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) { info->tstamp_table = get_cbmem_addr(ptr); @@ -348,6 +353,9 @@ case CB_TAG_ASSEMBLER: cb_parse_string(ptr, &info->assembler); break; + case CB_TAG_MEM_CHIP_INFO: + cb_parse_mem_chip_info(ptr, info); + break; #if CONFIG(LP_NVRAM) case CB_TAG_CMOS_OPTION_TABLE: cb_parse_optiontable(ptr, info); -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by Ravi kumar (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Ravi kumar. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58545 to look at the new patch set (#6). Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. modem region to be handled in QC_SEC Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 --- M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/carve_out.c M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 5 files changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/58545/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by build bot (Jenkins) (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Sean Rhodes, Andy Pont, Paul Menzel, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 ) Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... Patch Set 28: (7 comments) File src/ec/starlabs/merlin/ec.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133009): https://review.coreboot.org/c/coreboot/+/58343/comment/11e1861a_0747d0e9 PS28, Line 247: { NULL, ITE_SMFI, PNP_IRQ0, 0xfff0, }, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133009): https://review.coreboot.org/c/coreboot/+/58343/comment/290850a6_47d2248a PS28, Line 250: /* Power Mangement I/F Channel 1 (PMC1) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133009): https://review.coreboot.org/c/coreboot/+/58343/comment/14a86c35_500aab99 PS28, Line 252: /* Power Mangement I/F Channel 2 (PMC2) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133009): https://review.coreboot.org/c/coreboot/+/58343/comment/55724ee9_514cd7e2 PS28, Line 258: /* Power Mangement I/F Channel 3 (PMC3) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133009): https://review.coreboot.org/c/coreboot/+/58343/comment/8e81fa1f_8af8c063 PS28, Line 260: /* Power Mangement I/F Channel 4 (PMC4) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133009): https://review.coreboot.org/c/coreboot/+/58343/comment/f252fcad_c76e2dce PS28, Line 262: /* Power Mangement I/F Channel 5 (PMC5) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133009): https://review.coreboot.org/c/coreboot/+/58343/comment/f71c9b30_66f9dde9 PS28, Line 274: }; adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 28 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:03:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google,intel: Add ChromeOS GPIOs to onboard.h
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Tim Wawrzynczak, Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59000 ) Change subject: mb/google,intel: Add ChromeOS GPIOs to onboard.h ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/butterfly/chromeos.c: https://review.coreboot.org/c/coreboot/+/59000/comment/e3cf9bad_007dc8b1 PS4, Line 16: #define DEVMODE_GPIO 54 > I thought of keeping it, assuming the switch existed but was deprecated from depthcharge. […] Done File src/mainboard/google/stout/chromeos.c: https://review.coreboot.org/c/coreboot/+/59000/comment/5b01809c_37ae68ba PS4, Line 79: CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), > Does deduplicating this have any side-effects? At least I'd mention this change in the commit messag […] Split to CB:59192 -- To view, visit https://review.coreboot.org/c/coreboot/+/59000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Gerrit-Change-Number: 59000 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 13:59:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add NVRAM counter for TPM 2.0
by Yu-Ping Wu (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Miriam Polzer, Andrey Pronin, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59097 ) Change subject: security/vboot: Add NVRAM counter for TPM 2.0 ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > I'm not really convinced this is necessary yet... please see my comment on your design doc. Could you point me to the design doc? -- To view, visit https://review.coreboot.org/c/coreboot/+/59097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I511dba3b3461713ce20fb2bda9fced0fee6517e1 Gerrit-Change-Number: 59097 Gerrit-PatchSet: 3 Gerrit-Owner: Miriam Polzer <mpolzer(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Miriam Polzer <mpolzer(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 13:44:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: google/stout: Removed duplicate recovery mode switch entry
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59192 ) Change subject: google/stout: Removed duplicate recovery mode switch entry ...................................................................... google/stout: Removed duplicate recovery mode switch entry Change-Id: I6e742b9d5256da2b7edcca0efda4faf999207465 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/stout/chromeos.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59192/1 diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 6bbc640..964217e 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -77,7 +77,6 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e742b9d5256da2b7edcca0efda4faf999207465 Gerrit-Change-Number: 59192 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google,intel: Add ChromeOS GPIOs to onboard.h
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Tim Wawrzynczak, Angel Pons. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59000 to look at the new patch set (#5). Change subject: mb/google,intel: Add ChromeOS GPIOs to onboard.h ...................................................................... mb/google,intel: Add ChromeOS GPIOs to onboard.h Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/chromeos.c A src/mainboard/google/auron/onboard.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/onboard.h M src/mainboard/google/link/chromeos.c M src/mainboard/google/link/onboard.h M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/onboard.h M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/slippy/onboard.h M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/onboard.h M src/mainboard/intel/baskingridge/chromeos.c A src/mainboard/intel/baskingridge/onboard.h M src/mainboard/intel/emeraldlake2/chromeos.c A src/mainboard/intel/emeraldlake2/onboard.h M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/strago/onboard.h 18 files changed, 92 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/59000/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Gerrit-Change-Number: 59000 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: samsung/lumpy,stumpy: Add get_power_switch()
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59002 ) Change subject: samsung/lumpy,stumpy: Add get_power_switch() ...................................................................... samsung/lumpy,stumpy: Add get_power_switch() Change-Id: I75c2e86e64943eb241db48482746317ed9ba47af Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59002 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/onboard.h M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/samsung/stumpy/onboard.h 4 files changed, 22 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index c6cdd66..22b936c 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -19,9 +19,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), @@ -30,7 +27,7 @@ {100, ACTIVE_HIGH, get_lid_switch(), "lid"}, /* Power Button */ - {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, + {101, ACTIVE_LOW, get_power_switch(), "power"}, /* Did we load the VGA Option ROM? */ /* -1 indicates that this is a pseudo GPIO */ @@ -54,6 +51,13 @@ return ec_read(0x83) & 1; } +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index d43e1bae..dd57076 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -18,4 +18,8 @@ /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ #define GPIO_REC_MODE 42 +#ifndef __ACPI__ +int get_power_switch(void); +#endif + #endif diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 1ed5d28..b845a91 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -15,9 +15,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), @@ -27,7 +24,7 @@ {100, ACTIVE_HIGH, 1, "lid"}, /* Power Button */ - {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, + {101, ACTIVE_LOW, get_power_switch(), "power"}, /* Did we load the VGA Option ROM? */ /* -1 indicates that this is a pseudo GPIO */ @@ -46,6 +43,13 @@ return !get_gpio(GPIO_REC_MODE); } +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/samsung/stumpy/onboard.h b/src/mainboard/samsung/stumpy/onboard.h index 602d456..b89c20c 100644 --- a/src/mainboard/samsung/stumpy/onboard.h +++ b/src/mainboard/samsung/stumpy/onboard.h @@ -9,4 +9,6 @@ /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ #define GPIO_SPI_WP 68 +int get_power_switch(void); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75c2e86e64943eb241db48482746317ed9ba47af Gerrit-Change-Number: 59002 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021